TWI366910B - Semiconductor package - Google Patents

Semiconductor package

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Publication number
TWI366910B
TWI366910B TW096137950A TW96137950A TWI366910B TW I366910 B TWI366910 B TW I366910B TW 096137950 A TW096137950 A TW 096137950A TW 96137950 A TW96137950 A TW 96137950A TW I366910 B TWI366910 B TW I366910B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
package
semiconductor
Prior art date
Application number
TW096137950A
Other languages
English (en)
Other versions
TW200828563A (en
Inventor
Rajendra D Pendse
Original Assignee
Stats Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Inc filed Critical Stats Chippac Inc
Publication of TW200828563A publication Critical patent/TW200828563A/zh
Application granted granted Critical
Publication of TWI366910B publication Critical patent/TWI366910B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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    • H01L2924/181—Encapsulation
TW096137950A 2006-12-07 2007-10-11 Semiconductor package TWI366910B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/608,164 US7608921B2 (en) 2006-12-07 2006-12-07 Multi-layer semiconductor package

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KR101517541B1 (ko) 2015-05-04
US20080136003A1 (en) 2008-06-12
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US7608921B2 (en) 2009-10-27
TWI495082B (zh) 2015-08-01
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JP2012235170A (ja) 2012-11-29
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US20100007002A1 (en) 2010-01-14
TW201130110A (en) 2011-09-01

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