TWI239609B - Method for manufacturing multi package module - Google Patents

Abstract

According to a method for manufacturing multi package module, firstly a substrate is provided. The upper surface of the substrate includes a plurality of mounting regions for chip scale packages (CSPs). Minimum width from the mounting regions to edges of the upper surface is not more than 1.0 mm. Before mounting the CSPs, a plurality of non-flow underfill materials is symmetrically applied on peripheries of the mounting regions, then the CSPs are mounted on the mounting regions. Solder balls of CSPs are re-flowed and the non-flow underfill materials are cured to symmetrically fix the CSPs, wherein the gap between the CSPs and the substrate don't need to fully fill with the non-flow underfill materials.

Description

1239609 V. Description of the invention (1) ^ ------ [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a multi-package module structure (Mu 丨 t Package Module, MPM). It is related to a manufacturing method of a multi-package module structure for dispensing on a small substrate size. [Prior technology] '' With the evolution and development of semiconductor packaging technology, the size of the semiconductor package structure can be close to the wafer size to produce chip-size packages (chi S2P: ckage, CSP), and more on the general-sized package substrate Multiple chip-size packages and other chips can be integrated into a multi-package module structure (Multi Package

Module (MPM) (MPM), in the future, people Γ, ^; ΛΘΘΛ, gystem In Package (SIp), do not need to integrate the system single chip (multiple processes: too 0: ⑴p, soc) and the size has been It can meet the requirements of the United Nations and has a high yield, so the current multi-package module structure is the graphics card, central processing unit and other portable electronics of the mobile device. And its process "reveals the conventional chip packaging module. As shown in Figure 1 of the previous case, a chip is packaged on the α soil plate and a surface is bonded to the substrate by bumps or materials. The upper surface is filled with ^ = (1: = the wafer without sealing the package,-the underfill gel is filled with #solid 4 j lnlmater ia 1) system to fill the package and the substrate. Chip-size packages are inherently protected,

1239609 V. Description of the invention 1 (2) When the packaging material is filled and covered with bumps (or solder balls) between the chip-size package and the substrate, it will cause excessive consumption of the packaging material and Inappropriate 'In addition, in order to achieve the full formation of the packaging material, the size of the substrate should be designed to be larger, so as to form the packaging material after the surface bonding of the package, but if the package is not glued, then The package ^ The bumps (or solder balls) around the substrate will withstand the stress of aggregation, and as the operation of the package heats up, the bumps (or solder balls) will soften and make the = component drop Detachment may also cause the package to tilt. [Summary of the Invention]

The main object of the present invention is to provide a method for manufacturing a multi-package module structure. The upper surface of a substrate includes a plurality of bonding areas. Before combining a plurality of wafer-size packages to the bonding areas, a plurality of bonding areas are combined. ^ The sticky colloids are symmetrically applied to the local periphery of each bonding area. After combining a plurality of chip size packages, the solder balls of the chip size packages are re-soldered and the viscous colloids are cured to make the The cured viscous colloid can stabilize the chip-size packages without filling the gap between the chip-size packages and the substrate.

• A second object of the present invention is to provide a method for manufacturing a multi-package module structure. A plurality of viscous colloidal systems are symmetrically coated on the periphery of each bonding region, for example, the viscous colloidal symmetrical points are coated as L. Shape, lumps " or straight bars, and the viscous glue system may not fill the gap between the chip-size packages and the substrate to save the consumption of the viscous glue: Another object is to provide a method for manufacturing a multi-package module structure. The symmetrical spot-coated viscous glue system includes soldering aid.

1239609 V. Description of the invention (3) h \ In order to avoid the cost of cold solder joints in the step of combining chip-size packages, and to re-solder the solder balls of these chip-size packages while curing the sticky temples The colloid 'achieves the effect of simplifying the process steps, and the substrate does not need to reserve a dispensing area' so that the minimum width of the bonding areas from the upper surface side of the substrate may not be greater than 1.0 mm to reduce the size of the substrate. Another object of the 4t invention is to provide a multi-package module structure 7 '. The upper surface of a substrate includes a plurality of bonding areas for bonding a plurality of chip-size packages, and the peripheral edges of each bonding area are formed by dot coating. There are a plurality of viscous colloids. The viscous gel systems may not fill the gaps between the chip-size packages and the substrate, and fix them at a low cost. The chip-size package # makes the board available. Small package size configuration. 1. A method for manufacturing a multi-package module structure according to the present invention, firstly, a substrate is provided. The upper surface of the substrate includes a plurality of bonding areas, each of which is connected with a plurality of connection pads. Preferably, it may not be reserved. Dispense the region so that the minimum width of the two regions from the upper surface side of the substrate is not greater than 1.0 mm. Then, apply a plurality of viscous colloidal symmetrical points to each bonding edge. The slightly colloidal symmetrical points are coated in two areas of [shape and lump shape, so that each wafer size is sealed; the joints ^ are connected; finally, the solder joints are reconnected =; = the ball connection corresponds to 1 and it is hard to cure the These viscous colloids are thicker than the chip size package and the substrate, and a gap is formed between the package and the substrate, so the cost is effectively and stably fixed. Some chip-size packages. Page 8 1239609 V. Description of the invention (4) [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. According to the manufacturing method of the multi-package module structure of the present invention, the first 1 to 1D diagrams are schematic cross-sectional views of a substrate in the manufacturing process, and the second diagram is a schematic diagram of the upper surface of the substrate provided, please refer to 1A and 1D. In FIG. 2, first, a substrate 110 is provided, which is a multilayer printed circuit board or a ceramic circuit board, which has an upper surface lu and a corresponding lower surface 112, and the upper surface 111 includes a plurality of Each bonding area 11 3 is provided with a plurality of connection pads 11 4 for bonding a plurality of chip scale packages (Chip Scale Packages, CSP) (as shown in FIG. 1D). Ground, the top surface 111 of the substrate 1 1 0 does not need to reserve the dispensing area, so that the junction area 11 3 is away from the top surface of the substrate 11 0. The minimum width of the side is not greater than 1.0 mm In this embodiment, the substrate 丨 丨 can be combined with a flip chip wafer 120 or other wire-bonded wafer on the upper surface 11 1. The flip chip wafer 1 20 can be a graphics processing wafer or other wafer. The flip-chip wafer 1 20 has an active surface 121 and a back surface 122. The surface 121 is provided with a plurality of bumps 123, which are bonded to the substrate with a flip chip 丨 1 (). Preferably, the active surface 121 of the flip-chip wafer 1 20 and the upper surface 1 of the substrate 110 11 is filled with an underfill material 124. Next, referring to FIG. 1B, before combining the chip size packages of $ 140, a plurality of viscous colloids 130 are symmetrically coated on each of the bonding areas 11 3 Local peripheries, in which the corners formed at the junction area 3 are preferred, but are not limited to the positions of the viscous colloids 130. The viscous colloids 130 can be selected in shape, quantity or amount Symmetrical way to paint on each

1239609

The peripheral edge of a bonding area 11 3 is not connected to each other, and serves as a corner bond of the chip-size packages 1 40. Please refer to FIG. 3. In a specific spot coating method, the sticky The colloids 丨 30 are two symmetrical L-shaped spots painted on each of the joint areas 丨 丨 3 around the periphery, or refer to Figure 4, in another specific point coating method, these viscous colloids 丨 3 〇 The dots are symmetrically applied to the periphery of each bonding area 1 1 3 in a quantity or quantity manner, and the dot painting pattern is a ball shape or any other shape, or please refer to FIG. 5. In another specific spot coating method, The viscous colloids 30 are spot-coated on the periphery of each bonding region 113 in a symmetrical straight strip manner, so the colloidal gels 130 do not need to completely cover the bonding regions 113. Preferably, the The viscous colloid 130 is a non-flowing underfilling material (non-f 10w underfilling material), which contains a thermosetting resin and a flux. In addition, since the viscous colloid 13 is previously spot-coated on the \ 10 的 接 = Area 113, the periphery of the substrate 11 does not need to be prepared Dispensing after two electrical two Ϊ T square substrate 11 having smaller dimensions, for mounting to a variety of portable, see FIG. 1C, a plurality of chip size package 14〇

ϋ = ΐJunction area 113 'Each wafer size package "0 contains, semiconductor B chip 141, an active layer 142 and a plurality of tin-lead solder balls 143 are formed on the active surface of the wafer 141, the sealing compound The protection of the layers 142 掸 -141 and the robustness of the recording balls 143 make the semiconducting body ^ film = it is not necessary to fill the conventional underfill material in the chip-size packages 丨 4〇 the private In the process of surface bonding, since the viscous colloids 130 will be affected, the 143 tracks of the solder balls of the chip size package 14 will be made.

The solder balls 143 are re-soldered and the viscous colloids 130 are cured to make a multi-package module structure 100, so that the solder balls 143 will be more firmly connected to the connection pads 11 and After curing, the viscous colloid 130 is an electrical test step for sticking the crystals. Before re-soldering the solder balls 43 and curing the viscous colloid 130, the multi-package module structure 1 is electrically tested. 〇 () and these 1239609 V. Description of the invention (6) Connect the corresponding connection pads 1 1 4 to be electrically conductive. Finally, referring to FIG. ID, the symmetrical sides of the chip-size package 1 40 are on the substrate 11. Even if the temperature is increased, the viscous colloids 1 30 after curing still have good adhesion to stabilize the These chip-size packages 1 40 will not tilt or fall off "and the viscous colloids 130 after curing can not form a gap between the chip-size packages 410 and the substrate 110? 1. Therefore, these wafer-size packages 14 can be stabilized at low cost and effectively. The present invention may further include a specific wafer size package 140. If there is a defective wafer size package 140, it can be removed by rework before curing the viscous colloids 30. Therefore, according to the manufacturing method of the multi-package module structure of the present invention, a plurality of wafer-size packages 140 and at least one wafer 120 can be combined with high density on a limited-size substrate 110, and the wafer-size packages 140 The viscous colloids 130 formed by symmetrical point coating are used for fixing. During the curing process of the viscous colloids 130, the amount of the miscellaneous amount is predetermined to be insufficient to fill the corresponding wafers 140 and the substrate. The gap of 110, so even though the viscous colloids 13 are uncured and slightly flowing, which causes some changes in the shape of the viscous colloids 130, the viscous colloids 130 will not be connected to each other. In order to prevent the gas / inner package, in addition, the substrate does not need to be reserved in the design of the substrate.

Page 11 1239609_ V. Description of the invention (7) Dispensing area of board 110, to obtain concrete and feasible multi-package molds, structures, and build 100. The scope of protection of the present invention shall be defined by the scope of the attached patent application In case, any changes and modifications made by anyone skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention.

Page 1239609 Brief description of the drawings [Simplified description of the drawings] Sections 1A to ID®: Manufacturing method of a multi-package module structure according to the present invention 'A cross-sectional view of a substrate in the manufacturing process; Figure 2 according to the present invention Schematic diagram of the upper surface of the substrate provided by the manufacturing method of the multi-package module structure; Figure 3 · Diagram · According to one embodiment of the present invention, a schematic diagram of the upper surface of a substrate coated with a plurality of viscous colloids symmetrically, Figure 4: A schematic diagram of the upper surface of a substrate coated with a plurality of viscous colloids at symmetrical points according to another embodiment of the present invention; and Figure 5: a plurality of symmetrical points coated at a symmetrical point according to another embodiment of the present invention Schematic diagram of the upper surface of a substrate with a viscous colloid. Simple explanation of component symbols: 10 0 multi-package module structure 112 lower surface 1 2 2 back surface 1 4 3 solder ball 11 0 substrate 111 upper surface 11 3 bonding area 114 connection pad 120 chip wafer 121 active surface 1 2 3 bump 1 2 4 Underfill material 1 3 0 Viscous colloid 1 4 0 Wafer size package 4 Cow 141 Wafer 142 Sealant layer P1 Gap Page 13

Claims (1)

1239609 [Scope of patent application] 1. Two kinds of manufacturing methods of multi-package module structure, including providing a substrate. The upper surface of the substrate includes 2 small regions. The bonding region is provided with a plurality of connection pads. The bonding symmetrical point is coated with a plurality of viscous colloids due to a local circumference of each bonding region. One chip size package (Chip Scale Package, #, ;; two t bonding regions, the wafer size package has a plurality of welding requirements). 'Connect the corresponding connection 塾; and re-solder the solder balls and cure the viscous colloids. ^ A method for making a multi-package module structure as described in the first item of the patent scope of claim M, wherein The viscous glue systems at the periphery of the zone have a symmetrical L-shape. J. The Xe method for manufacturing a multi-package module structure as described in item 1 of the initial patent application range, wherein the viscous glues at the periphery of the joint zone The system is a ball-like shape. 4. The manufacturing method of the multi-package module structure described in item 1 of the application of the kiss kiss patent, wherein the viscous glue systems at the periphery of the bonding area are straight-shaped. 5 The method for manufacturing a multi-package module structure as described in claim 1 of the patent scope, wherein the viscous glue system has a non-flow underfill material (non-flow underfill material). 6. The manufacturing method of the multi-package module structure described in item 1 or 5 of the scope of patent application ', wherein the viscous adhesive systems include a flux. Page 14 1239609 7. The manufacturing method of a plurality of PEI component module structures as described in item 丨 of the patent application range, wherein the substrate is bonded to a wafer before the viscous colloids are spot-coated. 8. The method k for manufacturing a multi-package module structure as described in item 7 of the scope of the patent application, wherein the wafer is a flip-chip wafer. 9. The manufacturing method of the multi-package module structure as described in item 丨 of the patent application scope, wherein the viscous glue systems are not filled between the chip-size package and the substrate and are not connected to each other after curing. . 10. The method for manufacturing a multi-package module structure as described in item 丨 of the patent application scope, wherein the minimum width of the bonding areas from the upper surface side of the substrate is not greater than 1.0 mm. 12 The manufacturing method of the multi-package module structure described in item 1 of the declared patent scope, further comprising an electrical test step, before re-soldering the solder balls and curing the viscous colloids, using electrical properties Test on this substrate: the ruler + package. 1 2. A multi-package module structure, including: a substrate 'the upper surface of the substrate includes at least one bonding pad with a plurality of connection pads; a plurality of viscous colloids, which are formed by dot coating A local periphery of a bonding area; and at least one Chip Scale Package (Chip Scale Package), which is bonded to the bonding areas, the chip size package has f solder balls, which are re-soldered to Connect the corresponding connection pads, and the viscous glue system is cured and not connected to each other to stabilize the wafer ruler Page 15 1239609 ----- I-VI. Scope of patent application Inch package. 1 3. According to the scope of application for patent No. i 2, the shape is at the periphery of the joint area. 1 4. If the scope of patent application is i 2 where the perimeter of the joint zone is 1 5; if the scope of patent application is i 2 where the perimeter of the junction is 16; if the patent scope is 2; those are sticky Underfill material) 〇1 7. If the patent application range is i 2, the viscous colloids 18, such as the patent application range i 2, where the viscous rubber system does not form a gap between the plates. . 19. If the scope of the patent application is No. 2 where the distance between the bonding areas is greater than 1. · 0mm 〇 2 0. If the scope of the patent application is No. 1 2 it also includes a chip-on-wafer, 2 1. If the scope of the patent application is No. 2 〇 Wherein the flip-chip wafer is combined with the multi-package module structure described in item, some viscous glue systems have the multi-package module structure described in item L in symmetry, and the viscous glue systems are clusters. Many of the package module structures described in the item above, these viscous glue systems are straight makeup. The multi-package module structure described in the item, non-fiow material (non-fiow or the multi-package module structure described in the item 16 includes a flux. The multi-package module structure described in the item, fill in Full of the chip size package and the multi-package module structure described in the basic item, the minimum width of the upper side of the surface of the board is not the multi-package module structure described in the item, which is combined with the substrate. The upper surface of the multi-package module structure described in the item, the center of the upper surface of the substrate.