US20100078788A1 - Package-on-package assembly and method - Google Patents
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- US20100078788A1 US20100078788A1 US12/239,499 US23949908A US2010078788A1 US 20100078788 A1 US20100078788 A1 US 20100078788A1 US 23949908 A US23949908 A US 23949908A US 2010078788 A1 US2010078788 A1 US 2010078788A1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the anisotropic conductive film 14 with the conductive particles 16 electrically and mechanically couples the first and second integrated circuit packages 12 and 20 .
- the elasticity of the compressed trapped conductive particles 16 between the first and second integrated circuit packages 12 and 20 causes them to press outward on contact points thereby facilitating the electrical and mechanical connections between the first and second integrated circuit packages 12 and 20 .
- a second integrated circuit package is disposed on a top surface of the anisotropic conductive film.
- a bottom surface of the second integrated circuit package includes a solder paste disposed in a plurality of locations to bond the second integrated circuit package with the anisotropic conductive film.
- FIG. 4 illustrates an exemplary configuration 70 for bonding the anisotropic conductive film 14 to the first integrated circuit package 12 of the package-on-package assembly 10 of FIG. 1 .
- the first integrated circuit 12 includes the die 24 coupled to the substrate 26 through the collapse chip connection bumps 28 .
- the anisotropic conductive film 14 is laminated to the top surface 18 of the first integrated circuit package 12 .
- the first integrated circuit package 12 includes a plurality of copper pads disposed on the top surface 18 of the first integrated circuit package 12 .
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A package-on-package (PoP) assembly is provided. The package-on-package (PoP) assembly includes a first integrated circuit package and an anisotropic conductive film (ACF) disposed on a top surface of the first integrated circuit package, wherein the anisotropic conductive film comprises a plurality of conductive particles. The package-on-package (PoP) assembly also includes a second integrated circuit package disposed on a top surface of the anisotropic conductive film.
Description
- With recent advancements in the semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. To reduce the dimensions of such components, the structures by which these components are packages and assembled with circuit boards must become more compact.
- Package-on-package stacking of semiconductor devices is one known packaging technique in the art. Typically, such packages include a top integrated circuit package and a bottom integrated circuit package. One method of connecting the top integrated circuit package to the bottom integrated circuit package is through solder balls. In order to meet a desired gap height of the packaged assembly, a solder ball size may be increased. However, this may result in a large package font factor and may also cause solder bridging.
- Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which:
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FIG. 1 illustrates a package-on-package (PoP) assembly in accordance with embodiments of present technique; -
FIG. 2 illustrates an exemplary process for forming the package-on-package assembly ofFIG. 1 in accordance with embodiments of present technique; -
FIG. 3 illustrates an exemplary configuration of the anisotropic conductive film employed in the package-on-package assembly ofFIG. 1 in accordance with embodiments of present technique; -
FIG. 4 illustrates an exemplary configuration for bonding the anisotropic conductive film to the first integrated circuit package of the package-on-package assembly ofFIG. 1 in accordance with embodiments of present technique; -
FIG. 5 illustrates an exemplary configuration for bonding the first integrated circuit package to the anisotropic conductive film ofFIG. 4 in accordance with embodiments of present technique; and -
FIG. 6 illustrates an embodiment of a computer system. - Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.
- As discussed in detail below, the embodiments of the present invention function to provide a method of forming interconnections for a package-on-package assembly. In particular, the technique uses an anisotropic conductive film having conductive particles to connect two stacking packages in the package-on-package assembly.
- References in the specification to “one embodiment”, “an embodiment”, “an exemplary embodiment”, indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- The following description includes terms, such as top, bottom etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of the device or article described herein can be manufactured or used in a number of positions and orientations.
- Referring first to
FIG. 1 , a package-on-package (PoP)assembly 10 is illustrated. The package-on-package (PoP)assembly 10 includes a firstintegrated circuit package 12. Further, package-on-package (PoP)assembly 10 includes an anisotropic conductive film (ACF) 14 having a plurality ofconductive particles 16 disposed on atop surface 18 of the firstintegrated circuit package 12. The anisotropicconductive film 14 is a lead free and an environment friendly epoxy system and is readily available in the market. The package-on-package (PoP)assembly 10 also includes a secondintegrated circuit package 20 disposed on atop surface 22 of the anisotropicconductive film 14. - In this exemplary embodiment, the first integrated circuit package includes a die 24 coupled to a
substrate 26. Thesubstrate 26 may be formed of a variety of materials including ceramic and printed circuit boards. Further, thesubstrate 26 may be a one-layer board or a multi-layer board. In certain embodiments, the die 24 forms one of a data storage device, a digital signal processor, a micro-controller and a hand-held device. Typically, the die 24 is attached to one side of thesubstrate 26 and the attachment may be through a plurality of controlled collapse chip connection (C4)bumps 28. However, other attachment techniques may be envisaged. Similarly, the second integratedcircuit package 20 includes a die 30 coupled to asubstrate 32 through a plurality of controlled collapsechip connection bumps 34. - In this exemplary embodiment, the anisotropic
conductive film 14 with theconductive particles 16 electrically and mechanically couples the first and second integratedcircuit packages conductive particles 16 between the first and second integratedcircuit packages circuit packages - In one exemplary embodiment, the anisotropic
conductive film 14 comprises a polyester film. In one exemplary embodiment, a thickness of the anisotropicconductive film 14 is about 180 microns. In the illustrated embodiment, the anisotropicconductive film 14 comprises a uniform array ofconductive rods 16 disposed within the anisotropicconductive film 14. In one exemplary embodiment, a diameter of each of theconductive rods 16 is about 50 microns. A plurality of shapes of theconductive particles 16 may be envisaged. Exemplary shapes include, but are not limited to, cylindrical, square, and cubical shapes. - In one exemplary embodiment, a pitch of the
conductive particles 16 is about 100 microns. In one exemplary embodiment, a thickness of the each of the conductive particles is about 150 microns. In certain embodiments, agap height 36 between the first and secondintegrated circuit packages conductive film 14 and provides better control of atotal thickness 38 of the package-on-package assembly 10. The anisotropicconductive film 14 with uniformly alignedconductive particles 16 provides relatively better interconnection properties such as fine pitch and low contact resistance. Moreover, the material of the anisotropicconductive film 14 is selected such that it maintains surface flatness and provides better bonding between the first and secondintegrated circuit packages - In the illustrated embodiment, the first
integrated circuit package 12 includes a plurality ofcopper pads 40 disposed on thetop surface 18 of the firstintegrated circuit package 12. Further, the second integratedcircuit package 20 includes asolder paste 42 disposed in a plurality of locations on abottom surface 44 of the second integratedcircuit package 20. The anisotropicconductive film 14 is disposed between the first and secondintegrated circuit packages conductive particles 16 are aligned between the plurality ofcopper pads 40 of the firstintegrated circuit package 12 and thecorresponding solder paste 42 of the secondintegrated circuit package 20. -
FIG. 2 illustrates anexemplary process 50 for forming the package-on-package assembly 10 ofFIG. 1 in accordance with embodiments of present technique. Atblock 50, an anisotropic conductive film is provided. In this exemplary embodiment, the anisotropic conductive film comprises a plurality of conductive particles disposed within the anisotropic conductive film. In one exemplary embodiment, the plurality of conductive particles comprises conductive rods. In one embodiment, a thickness of the anisotropic conductive film and a thickness of each of the plurality of conductive particles is selected to achieve a desired gap height between two packages of the package-on-package assembly. In one exemplary embodiment, the anisotropic conductive film comprises a polyester film. - At
block 54, the anisotropic conductive film is laminated to a first integrated circuit package. In this embodiment, the anisotropic conductive film is bonded to a top surface of the first integrated circuit package through a thermocompression technique. The anisotropic conductive film is placed on the top surface of the first integrated circuit package and sufficient pressure is applied to the anisotropic conductive film for bonding the anisotropic conductive film to a plurality of copper pads disposed on the first integrated circuit package. In one exemplary embodiment, a temperature for bonding the anisotropic conductive film to the first integrated circuit package is between about 90° C. and about 100° C. Further, a bonding time is between about 3 seconds to about 5 seconds. - At
block 56, a second integrated circuit package is disposed on a top surface of the anisotropic conductive film. In this exemplary embodiment, a bottom surface of the second integrated circuit package includes a solder paste disposed in a plurality of locations to bond the second integrated circuit package with the anisotropic conductive film. - Further, at
block 58, the first and second integrated circuit packages are bonded to align the plurality of conductive particles between the first and second integrated circuit packages. In this exemplary embodiment, the first and second integrated circuit packages are subjected to thermocompression to attach the first and second integrated circuit packages. Further, the thermcompression process also cures adhesive material of the anisotropic conductive film thereby eliminating the need of mechanical connection between the first and second packages. - In one exemplary embodiment, the structure described above is bonded at a temperature of between about 150° C. and about 210° C. In one exemplary embodiment, a bonding time is between about 5 seconds to about 20 seconds. In this exemplary embodiment, the conductive particles are disposed between the plurality of copper pads of the first integrated circuit package and corresponding solder paste of the second integrated package. In certain embodiments, a gap height between the first and second integrated circuit packages may be controlled by controlling the thickness of the anisotropic conductive film.
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FIG. 3 illustrates anexemplary configuration 60 of the anisotropicconductive film 14 employed in the package-on-package assembly 10 ofFIG. 1 . In the illustrated embodiment, the anisotropicconductive film 60 includes anadhesive film 62 and the plurality of conductive particles, such as represented byreference numeral 16 disposed within theadhesive film 62. Further, the anisotropicconductive film 60 includes arelease liner 64 disposed on atop surface 66 of theadhesive film 62. In operation, therelease liner 64 prevents bondhead from adhering to the anisotropicconductive film 60 during the lamination process. Therelease liner 64 is subsequently removed to prevent damage to the anisotropicconductive film 60. In one exemplary embodiment, the anisotropicconductive film 60 includes a polyester film with a silicone release liner disposed on thetop surface 66 of the polyester film. - In certain embodiments, the plurality of
conductive particles 16 include cylindrical, or square, or cubical, or round shaped metal coated conductive particles. However, other shapes of the plurality ofconductive particles 16 may be envisaged. In one embodiment, the plurality ofconductive particles 16 comprise a polymer coated with gold. In another embodiment, the plurality ofconductive particles 16 comprise a polymer coated with nickel and gold. In another embodiment, the plurality ofconductive particles 16 comprise gold coated with nickel. In yet another embodiment, the plurality ofconductive particles 16 comprise a glass bead coated with silver. However, a variety of other materials may be employed for the plurality ofconductive particles 16. - In this exemplary embodiment, the anisotropic
conductive film 60 has a square form factor. In one exemplary embodiment, a thickness of the anisotropicconductive film 60 is between about 20 microns to about 80 microns. In certain embodiments, the thickness of the anisotropicconductive film 60 is selected to achieve a desired gap height 36 (seeFIG. 1 ) between the first and second integrated circuit packages 12 and 20 (seeFIG. 1 ) of the package-on-package assembly 10. -
FIG. 4 illustrates anexemplary configuration 70 for bonding the anisotropicconductive film 14 to the firstintegrated circuit package 12 of the package-on-package assembly 10 ofFIG. 1 . In the illustrated embodiment, the firstintegrated circuit 12 includes the die 24 coupled to thesubstrate 26 through the collapse chip connection bumps 28. Further, the anisotropicconductive film 14 is laminated to thetop surface 18 of the firstintegrated circuit package 12. In this exemplary embodiment, the firstintegrated circuit package 12 includes a plurality of copper pads disposed on thetop surface 18 of the firstintegrated circuit package 12. - In one embodiment, a
loader 72 is employed to apply sufficient pressure for bonding the anisotropicconductive film 14 to the firstintegrated circuit package 12. In one exemplary embodiment, the pressure applied to the anisotropic conductive film is between about 2 Kg/cm2 to about 3 Kg/cm2. In one exemplary embodiment, a temperature for bonding the anisotropic conductive film to the first integrated circuit package is between about 90° C. and about 100° C. Further, a bonding time is between about 3 seconds to about 5 seconds. -
FIG. 5 illustrates anexemplary configuration 80 for bonding the firstintegrated circuit package 20 to the anisotropicconductive film 14 ofFIG. 4 . As illustrated, the secondintegrated circuit package 20 includes the die 30 coupled to thesubstrate 32 through the plurality of controlled collapse chip connection bumps 34. Further, the secondintegrated circuit package 20 includes thesolder paste 42 disposed in a plurality of locations on thebottom surface 44 of the secondintegrated circuit package 20. - In this exemplary embodiment, the second
integrated circuit package 20 is stacked on the anisotropicconductive film 14 and undergoes a thermocompression process for bonding and curing theadhesive film 62. Again, aloader 82 may be employed to apply sufficient pressure to provide the bonding between thesolder paste 42 of the secondintegrated circuit package 20 and the anisotropicconductive film 14. - In one exemplary embodiment, a bonding temperature is between about 150° C. and about 210° C. In one exemplary embodiment, a bonding time is between about 5 seconds to about 20 seconds. In this exemplary embodiment, the
conductive particles 14 are disposed between the plurality ofcopper pads 40 of the firstintegrated circuit package 12 andcorresponding solder paste 42 of the secondintegrated package 20 to form the package-on-package assembly 10 illustrated inFIG. 1 . - The device described above may be disposed in a computer system, a wireless communicator and a hand-held device.
FIG. 6 illustrates an embodiment of acomputer system 90. Thecomputer system 90 includes abus 92 to which the various components are coupled. In certain embodiments, thebus 92 includes a collection of a plurality of buses such as a system bus, a Peripheral Component Interface (PCI) bus, a Small Computer System Interface (SCSI) bus, etc. Representation of these buses as asingle bus 92 is provided for ease of illustration, and it should be understood that thesystem 90 is not so limited. Those of ordinary skill in the art will appreciate that thecomputer system 90 may have any suitable bus architecture and may include any number of combination of buses. - A
processor 94 is coupled to thebus 92. Theprocessor 94 may include any suitable processing device or system, including a microprocessor (e.g., a single core or a multi-core processor), a network processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), or any similar device. It should be noted that althoughFIG. 6 shows asingle processor 94, thecomputer system 90 may include two or more processors. - The
computer system 90 further includessystem memory 96 coupled to thebus 92. Thesystem memory 96 may include any suitable type and number of memories, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), or double data rate DRAM (DDRDRAM). During operation of thecomputer system 90, an operating system and other applications may be resident in thesystem memory 96. - The
computer system 90 may further include a read-only memory (ROM) 98 coupled to thebus 92. TheROM 98 may store instructions for theprocessor 94. Thecomputer system 90 may also include a storage device (or devices) 100 coupled to thebus 92. Thestorage device 100 includes any suitable non-volatile memory, such as, for example, a hard disk drive. The operating system and other programs may be stored in thestorage device 100. Further, adevice 102 for accessing removable storage media (e.g., a floppy disk drive or a CD ROM drive) may be coupled to thebus 92. - The
computer system 90 may also include one or more Input/Output (I/O)devices 104 coupled to thebus 92. Common input devices include keyboards, pointing devices such as a mouse, as well as other data entry devices. Further, common output devices include video displays, printing devices, and audio output devices. It will be appreciated that these are but a few examples of the types of I/O devices that may be coupled to thecomputer system 90. - The
computer system 90 may further comprise anetwork interface 106 coupled to thebus 92. Thenetwork interface 106 comprises any suitable hardware, software, or combination of hardware and software that is capable of coupling thesystem 90 with a network (e.g., a network interface card). Thenetwork interface 106 may establish a link with the network over any suitable medium (e.g., wireless, copper wire, fiber optic, or a combination thereof) supporting exchange of information via any suitable protocol such as TCP/IP (Transmission Control protocol/Internet Protocol), HTTP (Hyper-Text Transmission Protocol, as well as others. - It should be understood that the
computer system 90 illustrated inFIG. 6 is intended to represent an embodiment of such a system and, further, that this system may include any additional components, which have been omitted for clarity and ease of understanding. By way of example, thesystem 90 may include a direct memory access (DMA) controller, a chip set associated with theprocessor 94, additional memory (e.g., cache memory) as well as additional signal lines and buses. Also, it should be understood that thecomputer system 90 may not include all the components shown inFIG. 6 . Thecomputer system 90 may comprise any type of computing device, such as a desktop computer, a laptop computer, a server, a hand-held computing device, a wireless communication device, an entertainment system etc. - In this embodiment, the
computer system 90 may include the device as described in the embodiments above. By way of example, thecomputer system 90 may include at least one package-on-package assembly. The package-on-package assembly may include a first integrated circuit package and an anisotropic conductive film (ACF) having a plurality of conductive particles disposed on a top surface of the first integrated circuit package. The package-on-package assembly may also include a second integrated circuit package disposed on a top surface of the anisotropic conductive film. - The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for a clear and comprehensive understanding of the disclosed embodiments and no unnecessary limitations are to be understood therefrom. Numerous additions, deletions, and modifications to the embodiments described herein, as well as alternative arrangements, may be devised by those skilled in the art without departing from the spirit of the disclosed embodiments and the scope of the appended claims.
Claims (21)
1. A package-on-package (PoP) assembly, comprising:
a first integrated circuit package including a first substrate;
an anisotropic conductive film (ACF) disposed on a top surface of the first substrate wherein the anisotropic conductive film comprises a plurality of conductive particles; and
a second integrated circuit package disposed on a top surface of the anisotropic conductive film.
2. The package on package assembly of claim 1 , wherein the anisotropic conductive film is electrically coupled to the first and second integrated circuit packages.
3. The package-on-package assembly of claim 1 , wherein the anisotropic conductive film comprises a polyester film.
4. The package-on-package assembly of claim 2 , wherein a thickness of the anisotropic conductive film is between about 20 microns to about 80 microns.
5. The package-on-package assembly of claim 1 , wherein the anisotropic conductive film comprises a uniform array of the conductive particles disposed within the anisotropic conductive film.
6. The package-on-package assembly of claim 5 , wherein a thickness of each of the conductive particles is about 150 microns.
7. The package-on-package assembly of claim 5 , wherein a pitch of the conductive particles is about 100 microns.
8. The package-on-package assembly of claim 1 , wherein the first integrated circuit package comprises a plurality of copper pads disposed on the top surface of the first substrate and the second integrated circuit package comprises a solder paste disposed in a plurality of locations on the top surface of the second integrated circuit package.
9. The package-on-package assembly of claim 8 , wherein the anisotropic conductive film is disposed between the plurality of copper pads and the corresponding solder paste.
10. The package-on-package assembly of claim 1 , further comprising a release liner disposed on a top surface of the anisotropic conductive film.
11-15. (canceled)
16. A system, comprising:
a network interface; and
a package-on-package assembly coupled to the network interface, wherein the package-on-package assembly comprises:
a first integrated circuit package including a first substrate;
an anisotropic conductive film (ACF) having a plurality of conductive particles disposed on a top surface of the first substrate; and
a second integrated circuit package disposed on a top surface of the anisotropic conductive film.
17. The system of claim 16 , wherein the plurality of conductive particles are aligned between a plurality of copper pads disposed on a top surface of the first substrate and a solder paste disposed on corresponding locations on the second integrated circuit package.
18. The system of claim 16 , wherein a package form factor of the package-on-package assembly is about 15 millimeters.
19. The system of claim 16 , wherein the anisotropic conductive film is to electrically and mechanically couple the first and second integrated circuit packages.
20. The system of claim 16 , wherein the anisotropic conductive film comprises a polyester film.
21. A package-on-package (PoP) assembly, comprising:
a first integrated circuit package including a first substrate;
an anisotropic conductive film (ACF) disposed on a top surface of the first substrate, wherein the anisotropic conductive film comprises a plurality of conductive particles; and
a second integrated circuit package disposed on a top surface of the anisotropic conductive film, and wherein the anisotropic conductive film is electrically coupled to the first and second integrated circuit packages.
22. The package-on-package assembly of claim 21 , wherein the anisotropic conductive film comprises a polyester film, and wherein the plurality of conductive particles includes a shape selected from cylindrical, square, cubical, and round.
23. The package-on-package assembly of claim 21 , wherein the plurality of conductive particles includes an objected selected from a polymer coated with gold, a polymer coated with nickel and gold, a gold coated with nickel, and a glass bead coated with silver.
24. The package-on-package assembly of claim 21 , wherein a thickness of each of the conductive particles is about 150 microns, and wherein a pitch of the conductive particles is about 100 microns.
25. The package-on-package assembly of claim 1 , wherein the first integrated circuit package comprises a plurality of copper pads disposed on the top surface of the first substrate and the second integrated circuit package comprises a solder paste disposed in a plurality of locations on the top surface of the second integrated circuit package, and wherein the anisotropic conductive film is disposed between the plurality of copper pads and the corresponding solder paste.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/239,499 US20100078788A1 (en) | 2008-09-26 | 2008-09-26 | Package-on-package assembly and method |
US14/278,737 US9070787B2 (en) | 2008-09-26 | 2014-05-15 | Package-on-package assembly and method |
Applications Claiming Priority (1)
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US12/239,499 US20100078788A1 (en) | 2008-09-26 | 2008-09-26 | Package-on-package assembly and method |
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US14/278,737 Division US9070787B2 (en) | 2008-09-26 | 2014-05-15 | Package-on-package assembly and method |
Publications (1)
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US20100078788A1 true US20100078788A1 (en) | 2010-04-01 |
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US12/239,499 Abandoned US20100078788A1 (en) | 2008-09-26 | 2008-09-26 | Package-on-package assembly and method |
US14/278,737 Expired - Fee Related US9070787B2 (en) | 2008-09-26 | 2014-05-15 | Package-on-package assembly and method |
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US14/278,737 Expired - Fee Related US9070787B2 (en) | 2008-09-26 | 2014-05-15 | Package-on-package assembly and method |
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Also Published As
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US20140248741A1 (en) | 2014-09-04 |
US9070787B2 (en) | 2015-06-30 |
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