CN104377182A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN104377182A
CN104377182A CN201310375631.7A CN201310375631A CN104377182A CN 104377182 A CN104377182 A CN 104377182A CN 201310375631 A CN201310375631 A CN 201310375631A CN 104377182 A CN104377182 A CN 104377182A
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China
Prior art keywords
substrate
semiconductor package
semiconductor
making
package part
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CN201310375631.7A
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English (en)
Inventor
施嘉凯
王隆源
江政嘉
徐逐崎
童世豪
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN104377182A publication Critical patent/CN104377182A/zh
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

一种半导体封装件及其制法，该半导体封装件，包括：第一基板、设于该第一基板上的第一半导体组件、设于该第一半导体组件上的第二基板、以及设于该第一基板与第二基板之间的第一封装层，且该第二基板以多个导电组件电性连接该第一基板。藉由该第二基板结合至该第一半导体组件上，使该第一与第二基板之间的距离固定，而能控制该些导电组件的高度与体积。

Description

半导体封装件及其制法
技术领域
本发明涉及一种封装结构，特别是关于一种半导体封装件及其制法。
背景技术
随着近年來可携式电子产品的蓬勃发展，各類相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势而走，各式样的堆栈封装(package on package，PoP)也因而配合推陈出新，以期能符合轻薄短小与高密度的要求。
如图1所示，其为现有堆栈式半导体封装件1的剖视示意图。该半导体封装件1包括两相叠的第一封装结构1a与第二封装结构1b、及粘固该第一封装结构1a与第二封装结构1b的封装胶体13。该第一封装结构1a包含第一基板10、以多个导电凸块110覆晶结合该第一基板10的第一半导体组件11、及包覆该些导电凸块110的底胶111。该第二封装结构1b包含第二基板12、以多个导电凸块140覆晶结合该第二基板12的第二半导体组件14、及包覆该些导电凸块140的底胶141。该第二基板12藉由焊锡球120叠设且电性连接于该第一基板10上，且该封装胶体13形成于该第一基板10与第二基板12之间以包覆该些焊锡球120。
然而，现有半导体封装件1中，该第一与第二封装结构1a,1b之间会形成间隙，且该焊锡球120于回焊后的体积及高度的公差大，不仅接点容易产生缺陷，导致电性连接品质不良，而且该焊锡球120所排列成的栅状数组(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该第一与第二封装结构1a,1b之间呈倾斜接置，甚至产生接点偏移的问题。
此外，若以铜柱取代焊锡球120做为支撑，虽可避免倾斜接置的问题，但铜柱的成本较高，所以不符合经济效益。
另外，于该基板与该半导体组件之间填充底胶111,141，将会提高生产成本。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明的主要目的为提供一种半导体封装件及其制法，能控制该些导电组件的高度与体积。
本发明的半导体封装件，包括：第一基板；设于该第一基板上的第一半导体组件；设于该第一半导体组件上的第二基板，且该第二基板藉由多个导电组件电性连接该第一基板；以及设于该第一基板与第二基板之间的第一封装层，以由该第一封装层包覆该第一半导体组件与该些导电组件。
本发明还提供一种半导体封装件的制法，包括：提供一第一基板，该第一基板上设有第一半导体组件；结合第二基板至该第一半导体组件上，且该第二基板藉由多个导电组件电性连接该第一基板；以及形成第一封装层于该第一基板与第二基板之间，以由该第一封装层包覆该第一半导体组件与该些导电组件。
前述的制法中，还包括于结合该第二基板前，先将该第二基板进行切单制程。
前述的制法中，还包括进行切单制程，以制成多个半导体封装件。
前述的半导体封装件及其制法中，该第一半导体组件藉由多个导电凸块设于该第一基板上，且该些导电凸块由该第一封装层所包覆。
前述的半导体封装件及其制法中，该第一封装层粘接该第一基板与该第二基板。
前述的半导体封装件及其制法中，还包括于结合该第二基板前，形成结合层于该第一半导体组件上，以于结合该第二基板时，该第二基板接触结合于该结合层上。
前述的半导体封装件及其制法中，还包括设置第二半导体组件于该第二基板上，且可形成第二封装层于该第二基板上，以由该第二封装层包覆该第二半导体组件。
前述的半导体封装件及其制法中，还包括设置至少一封装件于该第二基板上。
由上可知，本发明的半导体封装件及其制法中，藉由该第二基板结合至该第一半导体组件上，使该第一与第二基板之间的距离固定，所以可控制该些导电组件的高度与体积，以避免该些导电组件产生缺陷而导致电性连接品质不良、共面性不良、倾斜接置等问题，因而不仅可提高产品良率，且无须使用成本较高的铜柱。
另外，该第一封装层直接填入该第一基板与该第一半导体组件之间以包覆该些导电凸块，因而无需使用底胶，所以能节省材料成本。
附图说明
图1为现有堆栈式半导体封装件的剖面示意图；以及
图2A至图2D为本发明半导体封装件的制法的剖面示意图；其中，图2B’为图2B的另一实施例，图2D’为图2D的另一实施例。
符号说明
1,2,2’,2”     半导体封装件
1a              第一封装结构
1b              第二封装结构
10,20           第一基板
11,21           第一半导体组件
110,140,210     导电凸块
111,141         底胶
12,22,22’      第二基板
120             焊锡球
13              封装胶体
14,24           第二半导体组件
20a,20b         第一线路层
200             焊球
211,241         结合层
22a,22b         第二线路层
220             导电组件
23              第一封装层
240             焊线
25              第二封装层
26              封装件
260             载体
261             第三半导体组件
262             封装体
263             导电组件
S               切割路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，提供一第一基板20与一第二基板22。该第一基板20上设有至少一第一半导体组件21，且于该第一半导体组件21上形成有一如非导电材料的结合层211，又该第二基板22下侧上形成有多个导电组件220。
于本实施例中，该第一与第二基板20,22为线路板，其分别具有多个第一线路层20a,20b与多个第二线路层22a,22b。
此外，该第一与第二基板20,22也可为其它承载芯片的承载件，并无特别限制。
又，该第一半导体组件21藉由多个导电凸块210以覆晶方式设于该第一基板20上侧的第一线路层20a上。
另外，该导电组件220为焊锡材料且形成于该第二基板22下侧的第二线路层22b上。
如图2B所示，将该第二基板22结合至该第一半导体组件21上，即该第二基板22接触结合于该结合层211上，使该结合层211位于该第二基板22与该第一半导体组件21之间，又该第二基板22藉由该些导电组件220支撑于该第一基板20上，且该些导电组件220电性连接该第一基板20上侧的第一线路层20a与该第二基板22下侧的第二线路层22b。
于本实施例中，于该第一半导体组件21上方粘合该结合层211，以供支撑与粘着第二基板22，可得到较佳的支撑效果。
于其它实施例中，如图2B’所示，可先将该第二基板22进行切单制程，再结合切单后的该第二基板22’至该第一半导体组件21上。
如图2C所示，形成第一封装层23于该第一基板20上侧与该第二基板22下侧之间，使该第一封装层23粘接该第一基板20与该第二基板22，且该第一封装层23包覆该第一半导体组件21、该些导电组件220与该些导电凸块210。
接着，进行切单制程，即切割路径S切割该封装结构，以制成多个半导体封装件2。
于本实施例中，由于该结合层211形成于该第二基板22与该第一半导体组件21之间，所以该第一封装层23不会填入该第二基板22与该第一半导体组件21之间。
此外，该第一基板20下侧的第一线路层20b上可形成有如焊球200的导电组件，以供接置如电路板或另一线路板的电子结构上。
如图2D所示，于后续制程中，可藉由一结合层241设置至少一第二半导体组件24于该第二基板22上侧上，再形成第二封装层25于该第二基板22上侧上，且该第二封装层25包覆该第二半导体组件24，以制成另一半导体封装件2’的实施例。
于本实施例中，该第二半导体组件24藉由多个焊线240以打线方式电性连接该第二基板22上侧的第二线路层22a，且该第二封装层25复包覆该些焊线240。于其它实施例中，该第二半导体组件22也可以覆晶方式设于该第二基板22上侧。
此外，也可先制成另一半导体封装件2’的实施例，再沿图2C所示的切割路径S进行切单制程。
另外，如图2D’所示，也可设置至少一封装件26于该第二基板22上，且切单制程可依需求先前进行或后续进行。
于本实施例中，该封装件26包含一载体260、设置并电性连接至该载体260的第三半导体组件261、及包覆该第三半导体组件261的封装体262。
此外，该载体260藉由多个如焊球的导电组件263电性连接该第二基板22，且该第三半导体组件261的封装方式可为打线（如图2D’所示）、覆晶或嵌埋等，但并无特别限制。
本发明的制法中，藉由该第二基板22直接接触结合至该第一半导体组件21上，使该第二基板22与该第一基板20之间的距离固定，所以可控制该些导电组件220的高度与体积，以于回焊该些导电组件220后，该些导电组件220所构成的接点不会产生缺陷，因而维持良好的电性连接品质，且该些导电组件220所排列成的栅状数组(grid array)的共面性(coplanarity)良好，因而接点应力(stress)保持平衡而不会造成该两基板之间呈倾斜接置，以避免产生接点偏移的问题。因此，本发明的制法不仅能提高产品良率，且无须使用成本较高的铜柱。
另外，该第一封装层23直接填入该第一基板20与该第一半导体组件21之间以包覆该些导电凸块210，因而无需使用底胶，所以能节省材料成本。
本发明提供一种半导体封装件2,2,2”，其包括：第一基板20、设于该第一基板20上的第一半导体组件21、设于该第一半导体组件21上的第二基板22、以及设于该第一基板20与第二基板22之间的第一封装层23。
所述的第一半导体组件21藉由多个导电凸块210设于该第一基板20上。
所述的第二基板22藉由多个导电组件220电性连接该第一基板20。
所述的第一封装层23粘接该第一基板20与该第二基板22，且该第一封装层23包覆该第一半导体组件21、该些导电凸块210与该些导电组件220。
于一实施例中，一结合层211设于该第一半导体组件21上，使该第二基板22接触结合于该结合层211上，且该结合层211位于该第一半导体组件21与该第二基板22之间。
于一实施例中，如图2D所示，该半导体封装件2’还包括设于该第二基板22上的第二半导体组件24及第二封装层25，且该第二封装层25包覆该第二半导体组件24。
于一实施例中，如图2D’所示，该半导体封装件2”还包括设于该第二基板22上的至少一封装件26，且该封装件26包含一载体260、设置并电性连接至该载体260的第三半导体组件261、及包覆该第三半导体组件261的封装体262。
综上所述，本发明的半导体封装件及其制法，主要藉由该第二基板直接接触结合至该第一半导体组件上，使该第二基板与该第一基板之间的距离固定，所以能控制该些导电组件的高度与体积，以提升该导电组件的接点品质，因而能维持良好的电性连接品质与共面性，且因接点应力保持平衡而不会造成倾斜接置。因此，本发明的制法不仅能提高产品良率，且无须使用成本较高的铜柱。
另外，该第一封装层直接填入该第一基板与该第一半导体组件之间以包覆该些导电凸块，因而无需使用底胶，所以能节省材料成本。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种半导体封装件，包括：
第一基板；
第一半导体组件，其设于该第一基板上；
第二基板，其设于该第一半导体组件上，且该第二基板藉由多个导电组件电性连接该第一基板；以及
第一封装层，其设于该第一基板与第二基板之间，以由该第一封装层包覆该第一半导体组件与该些导电组件。
2.根据权利要求1所述的半导体封装件，其特征在于，该第一半导体组件藉由多个导电凸块设于该第一基板上，且该些导电凸块由该第一封装层所包覆。
3.根据权利要求1所述的半导体封装件，其特征在于，该第一封装层粘接该第一基板与该第二基板。
4.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括结合层，其设于该第一半导体组件上，使该第二基板接触结合于该结合层上。
5.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括第二半导体组件，其设于该第二基板上。
6.根据权利要求5所述的半导体封装件，其特征在于，该半导体封装件还包括第二封装层，其设于该第二基板上，以由该第二封装层包覆该第二半导体组件。
7.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括封装件，其设于该第二基板上。
8.一种半导体封装件的制法，其包括：
提供一第一基板，该第一基板上设有第一半导体组件；
结合第二基板至该第一半导体组件上，且该第二基板藉由多个导电组件电性连接该第一基板；以及
形成第一封装层于该第一基板与第二基板之间，以由该第一封装层包覆该第一半导体组件与该些导电组件。
9.根据权利要求8所述的半导体封装件的制法，其特征在于，该第一半导体组件藉由多个导电凸块设于该第一基板上，且该些导电凸块由该第一封装层所包覆。
10.根据权利要求8所述的半导体封装件的制法，其特征在于，该第一封装层粘接该第一基板与该第二基板。
11.根据权利要求8所述的半导体封装件的制法，其特征在于，该制法还包括于结合该第二基板前，形成结合层于该第一半导体组件上，以于结合该第二基板时，该第二基板接触结合于该结合层上。
12.根据权利要求8所述的半导体封装件的制法，其特征在于，该制法还包括于结合该第二基板前，先将该第二基板进行切单制程。
13.根据权利要求8所述的半导体封装件的制法，其特征在于，该制法还包括设置第二半导体组件于该第二基板上。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该制法还包括形成第二封装层于该第二基板上，以由该第二封装层包覆该第二半导体组件。
15.根据权利要求8所述的半导体封装件的制法，其特征在于，该制法还包括设置至少一封装件于该第二基板上。
16.根据权利要求8、14或15所述的半导体封装件的制法，其特征在于，该制法还包括进行切单制程，以制成多个半导体封装件。
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