CN102867801A - 半导体承载件暨封装件及其制法 - Google Patents

半导体承载件暨封装件及其制法 Download PDF

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Publication number
CN102867801A
CN102867801A CN2011102080312A CN201110208031A CN102867801A CN 102867801 A CN102867801 A CN 102867801A CN 2011102080312 A CN2011102080312 A CN 2011102080312A CN 201110208031 A CN201110208031 A CN 201110208031A CN 102867801 A CN102867801 A CN 102867801A
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China
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nickel
gold
encapsulated layer
electrical contact
semiconductor
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CN2011102080312A
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林邦群
蔡岳颖
陈泳良
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN102867801A publication Critical patent/CN102867801A/zh
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Abstract

一种半导体承载件暨封装件及其制法，该半导体封装件包括：第一封装层、电性接点、多路线路、半导体芯片与第二封装层，该第一封装层具有多个贯穿的顶宽底窄的锥形孔，该电性接点形成于各该锥形孔中而呈锥形，该等线路形成于该第一封装层的顶面上，各该线路的一端连接各该电性接点，另一端形成有焊指垫，该等焊指垫以围绕配置的方式定义出一置晶区，以供半导体芯片设置于该置晶区中的第一封装层顶面上，并令该半导体芯片电性连接各该焊指垫，且该第二封装层覆盖该半导体芯片、线路与第一封装层。本发明能有效避免电性接点脱落、并缩减导电组件的长度。

Description

半导体承载件暨封装件及其制法
技术领域
本发明有关于一种承载件暨封装件及其制法，尤指一种半导体承载件暨封装件及其制法。
背景技术
四方平面无导脚(Quad Flat No Lead，简称QFN)半导体封装件为一种使芯片座和接脚底面外露于封装层底部表面的封装单元，一般是采用表面粘着技术(surface mount technology，简称SMT)将四方平面无导脚半导体封装件接置于印刷电路板上，借此以形成一具有特定功能的电路模块。
请参阅图1，美国专利第6635957号、第6872661号、第7009286号、第7081403号、与第7371610号等先前技术揭示一种现有的四方平面无导脚半导体封装件的剖视图，其先于承载板10中形成多个固定孔径的通孔100，并以电镀方式于各该通孔100中形成电性接点11，其中，各该电性接点11是由多次电镀不同金属层所叠接形成，之后再将半导体芯片12接置于该承载板10上，并进行打线制程，以将该半导体芯片12电性连接至各该电性接点11，最后，以封装层13包覆该半导体芯片12、电性接点11与承载板10。
现有的四方平面无导脚半导体封装件具有制作简单、及电镀方式形成的电性接点较小的优点；然而，由于容置该电性接点的通孔为固定孔径，所以该电性接点容易从该通孔中脱落；此外，由于部分电性接点距离半导体芯片较远，故其打线须耗费较长的金属线材(例如金线)，而造成整体成本的上升。
因此，如何避免上述现有技术中的种种问题，以使四方平面无导脚半导体封装件的电性接点不易脱落，并减低打线所需的材料成本，实已成为目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明的主要目的在于提供一种半导体承载件暨封装件及其制法，能有效避免电性接点脱落、并缩减导电组件的长度。
提供一种半导体承载件，其包括：第一封装层，具有多个贯穿的顶宽底窄的锥形孔；电性接点，其形成于各该锥形孔中而呈锥形；以及多路线路，其形成于该第一封装层的顶面上，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层的顶面上定义出一置晶区。
本发明提供一种半导体封装件，其包括：具有多个贯穿的顶宽底窄的锥形孔的第一封装层；形成于各该锥形孔中而呈锥形的电性接点；形成于该第一封装层的顶面上的多路线路，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层的顶面上定义出一置晶区；设置于该置晶区中的该第一封装层的顶面上的半导体芯片；将该半导体芯片电性连接至各该焊指垫的多个导电组件；以及覆盖该半导体芯片、导电组件、线路与第一封装层的第二封装层。
本发明还提供一种半导体承载件的制法，其包括：于一承载板上形成第一封装层；于该第一封装层中形成多个顶宽底窄的锥形孔，以外露该承载板；以及于各该锥形孔中形成锥形的电性接点，并于该第一封装层上形成多路线路，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层上定义出一置晶区。
本发明还提供一种半导体封装件的制法，其包括：于一承载板上形成第一封装层；于该第一封装层中形成多个顶宽底窄的锥形孔，以外露该承载板；于各该锥形孔中形成锥形的电性接点，并于该第一封装层上形成多路线路，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层上定义出一置晶区；于该置晶区中的该第一封装层上接置半导体芯片；形成多个导电组件，以借由该导电组件将该半导体芯片电性连接至该焊指垫；形成覆盖该半导体芯片、导电组件、线路与第一封装层的第二封装层；以及移除该承载板。
由上可知，本发明的半导体承载件暨封装件于第一封装层中形成孔径渐缩的锥形孔，所以该电性接点无法从该锥形孔滑出或脱落，而能提升整体可靠度；此外，本发明的封装件可于接置有半导体芯片的该侧的表面上布设多个连接各该电性接点的线路，并借由该线路的焊指垫以拉近导电组件的打线距离，故能有效缩减导电组件所需的长度，进而减低整体制造成本。
附图说明
图1为一种现有的四方平面无导脚半导体封装件的剖视图。
图2A至图2L为本发明的半导体承载件暨封装件及其制法的剖视图，其中，图2F’为部分图2F的俯视图。
主要组件符号说明
10，20    承载板
100       通孔
11        电性接点
12        半导体芯片
13        封装层
2         半导体封装件
21        第一封装层
210       锥形孔
22        阻层
220       阻层开口区
231       电性接点
232       线路
232a      焊指垫
24        粘着层
25        半导体芯片
26        导电组件
27        第二封装层
28        焊球
A        区域
B        置晶区。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“顶”、“底”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，也当视为本发明可实施的范畴。
请参阅图2A至图2L，其为本发明的半导体承载件暨封装件及其制法的剖视图，其中，图2F’为部分图2F的俯视图。
如图2A所示，准备一承载板20。
如图2B所示，于该承载板20上形成第一封装层21。
如图2C所示，以例如雷射钻孔或机械钻孔的技术于该第一封装层21中形成多个顶宽底窄的锥形孔210，以外露该承载板20。
如图2D所示，于该具有锥形孔210的第一封装层21上形成阻层22，该阻层22具有多个外露该锥形孔210与第一封装层21的阻层开口区220。
如图2E所示，于该阻层开口区220中的锥形孔210中形成电性接点231，并于该阻层开口区220中的电性接点231与第一封装层21上形成线路232；要注意的是，该电性接点231与线路232可如前述地一体成型，或者，该电性接点231与线路232可分别成型，即先形成该电性接点231，之后再形成该线路232，然而由于此分别成型的步骤是本发明所属技术领域的通常知识者所能轻易了解，故在此并未加以图标说明。
如图2F与图2F’所示，移除该阻层22，由图可知，该线路232的一端连接各该电性接点231，各该线路232的另一端具有焊指垫(finger)232a，该等焊指垫232a以围绕方式配置，以于该第一封装层21上定义出一置晶区B；其中，图2F’为图2F的区域A的俯视图。
要注意的是，至此即完成本发明的半导体承载件，但是本发明的半导体承载件可不具有该承载板20，因此也可于此时即移除该承载板20，然而由于此步骤为本发明所属技术领域的通常知识者所能轻易了解，故在此并未加以图标说明。
如图2G所示，借由粘着层24而于该置晶区B中的该第一封装层21上接置半导体芯片25。
如图2H所示，形成多个导电组件26，以借由该导电组件26将该半导体芯片25电性连接至该焊指垫232a，其中，该导电组件26可为金属线。
如图2I所示，形成覆盖该半导体芯片25、导电组件26、线路232与第一封装层21的第二封装层27。
如图2J所示，移除该承载板20。
如图2K所示，于该第一封装层21底面的各该电性接点231上形成焊球28。
如图2L所示，进行切单制程，以得到多个四方平面无导脚半导体封装件2。
本发明还提供一种半导体承载件，其包括：第一封装层21，具有多个贯穿的顶宽底窄的锥形孔210；电性接点231，其形成于各该锥形孔210中而呈锥形；以及多路线路232，其形成于该第一封装层21的顶面上，各该线路232的一端连接各该电性接点231，各该线路232的另一端形成有焊指垫(finger)232a，该等焊指垫232a以围绕方式配置，以于该第一封装层21的顶面上定义出一置晶区B。
于前述的半导体封承载件中，还可包括承载板20，其设于该第一封装层21的底面上。
依上所述的半导体承载件，该电性接点231可为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
于本实施例的半导体承载件中，该电性接点与线路可一体成型或分别成型。
本发明还提供一种半导体封装件2，其包括：第一封装层21，具有多个贯穿的顶宽底窄的锥形孔210；电性接点231，其形成于各该锥形孔210中而呈锥形；多路线路232，其形成于该第一封装层21的顶面上，各该线路232的一端连接各该电性接点231，各该线路232的另一端形成有焊指垫(finger)232a，该等焊指垫232a以围绕方式配置，以于该第一封装层21的顶面上定义出一置晶区B；半导体芯片25，其设置于该置晶区B中的该第一封装层21的顶面上；多个导电组件26，其将该半导体芯片25电性连接至各该焊指垫232a；以及第二封装层27，其覆盖该半导体芯片25、导电组件26、线路232与第一封装层21。
于前述的半导体封装件2中，还可包括焊球28，其形成于该第一封装层21底面的各该电性接点231上。
所述的半导体封装件2中，于该半导体芯片25与该第一封装层21的间还可包括粘着层24，且该粘着层24的材质可为玻璃粉(glass frit)、环氧树脂(epoxy)、或干膜(dry film)。
依上所述的半导体封装件2，该电性接点231可为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
于本实施例的半导体封装件2中，该电性接点与线路可一体成型或分别成型。
综上所述，相较于现有技术，本发明的半导体承载件暨封装件于第一封装层中形成顶宽底窄的锥形孔，所以于该锥形孔中所形成的电性接点在最终封装完成后不会有滑出或脱落的问题发生，而能提升整体可靠度；其次，本发明的封装件可于接置有半导体芯片的该侧的表面上布设多个连接各该电性接点的线路，且各该线路具有邻近半导体芯片的焊指垫，使得导电组件不需连接在距离较远的电性接点位置处，而仅需连接在距离较近的焊指垫上，再经由该线路而连接至电性接点，故可有效缩减导电组件的长度，进而减低整体制造成本。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (25)

1.一种半导体承载件，包括：
第一封装层，具有多个贯穿的顶宽底窄的锥形孔；
电性接点，形成于各该锥形孔中而呈锥形；以及
多路线路，形成于该第一封装层的顶面上，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层的顶面上定义出一置晶区。
2.根据权利要求1所述的半导体承载件，其特征在于，该半导体承载件还包括承载板，其设于该第一封装层的底面上。
3.根据权利要求1所述的半导体承载件，其特征在于，该电性接点为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
4.根据权利要求1所述的半导体承载件，其特征在于，该电性接点与线路为一体成型或分别成型。
5.一种半导体封装件，其包括：
第一封装层，具有多个贯穿的顶宽底窄的锥形孔；
电性接点，形成于各该锥形孔中而呈锥形；
多路线路，形成于该第一封装层的顶面上，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层的顶面上定义出一置晶区；
半导体芯片，设置于该置晶区中的该第一封装层的顶面上；
多个导电组件，用于将该半导体芯片电性连接至各该焊指垫；以及
第二封装层，其覆盖该半导体芯片、导电组件、线路与第一封装层。
6.根据权利要求5所述的半导体封装件，其特征在于，该半导体封装件还包括焊球，其形成于该第一封装层底面的各该电性接点上。
7.根据权利要求5所述的半导体封装件，其特征在于，于该半导体芯片与该第一封装层之间还包括粘着层。
8.根据权利要求7所述的半导体封装件，其特征在于，该粘着层的材质为玻璃粉、环氧树脂、或干膜。
9.根据权利要求5所述的半导体封装件，其特征在于，该电性接点为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
10.根据权利要求5所述的半导体封装件，其特征在于，该电性接点与线路为一体成型或分别成型。
11.一种半导体承载件的制法，包括：
于一承载板上形成第一封装层；
于该第一封装层中形成多个顶宽底窄的锥形孔，以外露该承载板；以及
于各该锥形孔中形成锥形的电性接点，并于该第一封装层上形成多路线路，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层上定义出一置晶区。
12.根据权利要求11所述的半导体承载件的制法，其特征在于，该半导体承载件还包括移除该承载板。
13.根据权利要求11所述的半导体承载件的制法，其特征在于，该电性接点与线路的形成步骤包括：
于该具有锥形孔的第一封装层上形成阻层，该阻层具有多个外露该锥形孔与第一封装层的阻层开口区；
于该阻层开口区中形成该电性接点与线路；以及
移除该阻层。
14.根据权利要求11所述的半导体承载件的制法，其特征在于，该电性接点为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
15.根据权利要求11所述的半导体承载件的制法，其特征在于，形成该锥形孔的方式为雷射钻孔或机械钻孔。
16.根据权利要求11所述的半导体承载件的制法，其特征在于，该电性接点与线路为一体成型或分别成型。
17.一种半导体封装件的制法，其包括：
于一承载板上形成第一封装层；
于该第一封装层中形成多个顶宽底窄的锥形孔，以外露该承载板；
于各该锥形孔中形成锥形的电性接点，并于该第一封装层上形成多路线路，各该线路的一端连接各该电性接点，各该线路的另一端形成有焊指垫，该等焊指垫以围绕方式配置，以于该第一封装层上定义出一置晶区；
于该置晶区中的该第一封装层上接置半导体芯片；
形成多个导电组件，以借由该导电组件将该半导体芯片电性连接至该焊指垫；
形成覆盖该半导体芯片、导电组件、线路与第一封装层的第二封装层；以及
移除该承载板。
18.根据权利要求17所述的半导体封装件的制法，其特征在于，该电性接点与线路的形成步骤包括：
于该具有锥形孔的第一封装层上形成阻层，该阻层具有多个外露该锥形孔与第一封装层的阻层开口区；
于该阻层开口区中形成该电性接点与线路；以及
移除该阻层。
19.根据权利要求17所述的半导体封装件的制法，其特征在于，该半导体封装件还包括于该第一封装层底面的各该电性接点上形成焊球。
20.根据权利要求17或19所述的半导体封装件的制法，其特征在于，该半导体封装件还包括进行切单制程。
21.根据权利要求17所述的半导体封装件的制法，其特征在于，该半导体芯片是借由粘着层而接置于该第一封装层上。
22.根据权利要求21所述的半导体封装件的制法，其特征在于，该粘着层的材质为玻璃粉、环氧树脂、或干膜。
23.根据权利要求17所述的半导体封装件的制法，其特征在于，该电性接点为金/钯/镍/钯、金/镍/铜/镍/金、金/镍/铜/镍/银、金/镍/铜/银、钯/镍/钯、金/镍/金、或钯/镍/金的自底部依序构成的多层金属。
24.根据权利要求17所述的半导体封装件的制法，其特征在于，形成该锥形孔的方式为雷射钻孔或机械钻孔。
25.根据权利要求17所述的半导体封装件的制法，其特征在于，该电性接点与线路为一体成型或分别成型。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097758A (zh) * 2014-05-05 2015-11-25 日月光半导体制造股份有限公司 衬底、其半导体封装及其制造方法
WO2016078520A1 (zh) * 2014-11-19 2016-05-26 清华大学 转接板及其制作方法、封装结构及用于转接板的键合方法
CN105810650A (zh) * 2015-01-16 2016-07-27 爱思开海力士有限公司 半导体封装及其制造方法、包括其的电子系统和存储卡

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI499013B (zh) 2013-01-22 2015-09-01 矽品精密工業股份有限公司 半導體封裝件及其製法
WO2017218894A1 (en) 2016-06-16 2017-12-21 Cutispharma, Inc. Composition and method for proton pump inhibitor suspension
JP7230419B2 (ja) * 2018-10-16 2023-03-01 富士電機株式会社 半導体装置、半導体装置の製造方法
US10751333B1 (en) 2019-07-16 2020-08-25 Cutispharma, Inc. Compositions and kits for omeprazole suspension
JP7293142B2 (ja) * 2020-01-07 2023-06-19 東芝デバイス＆ストレージ株式会社 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064012B1 (en) * 2004-06-11 2006-06-20 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps
US20080182360A1 (en) * 2007-01-26 2008-07-31 Chi Chih Lin Fabrication method of semiconductor package
CN101295650A (zh) * 2007-04-25 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
US20090108444A1 (en) * 2007-10-31 2009-04-30 Taiwan Solutions Systems Corp. Chip package structure and its fabrication method
US7548430B1 (en) * 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
CN101740539A (zh) * 2008-11-07 2010-06-16 矽品精密工业股份有限公司 四方平面无导脚封装单元及其制法和其导线架

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115989A (ja) * 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2003031710A (ja) * 2001-07-12 2003-01-31 Mitsumi Electric Co Ltd モノリシックｉｃパッケージ
US7867688B2 (en) * 2006-05-30 2011-01-11 Eastman Kodak Company Laser ablation resist
EP2084744A2 (en) * 2006-10-27 2009-08-05 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7548430B1 (en) * 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US7064012B1 (en) * 2004-06-11 2006-06-20 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps
US20080182360A1 (en) * 2007-01-26 2008-07-31 Chi Chih Lin Fabrication method of semiconductor package
CN101295650A (zh) * 2007-04-25 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
US20090108444A1 (en) * 2007-10-31 2009-04-30 Taiwan Solutions Systems Corp. Chip package structure and its fabrication method
CN101740539A (zh) * 2008-11-07 2010-06-16 矽品精密工业股份有限公司 四方平面无导脚封装单元及其制法和其导线架

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097758A (zh) * 2014-05-05 2015-11-25 日月光半导体制造股份有限公司 衬底、其半导体封装及其制造方法
US10879159B2 (en) 2014-05-05 2020-12-29 Advanced Semiconductor Engineering, Inc. Substrate, semiconductor package thereof and process of making same
WO2016078520A1 (zh) * 2014-11-19 2016-05-26 清华大学 转接板及其制作方法、封装结构及用于转接板的键合方法
CN105810650A (zh) * 2015-01-16 2016-07-27 爱思开海力士有限公司 半导体封装及其制造方法、包括其的电子系统和存储卡
CN105810650B (zh) * 2015-01-16 2020-06-05 爱思开海力士有限公司 半导体封装及其制造方法、包括其的电子系统和存储卡

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