TWI499013B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI499013B
TWI499013B TW102102301A TW102102301A TWI499013B TW I499013 B TWI499013 B TW I499013B TW 102102301 A TW102102301 A TW 102102301A TW 102102301 A TW102102301 A TW 102102301A TW I499013 B TWI499013 B TW I499013B
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substrate
passive component
passive
semiconductor wafer
semiconductor package
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TW102102301A
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TW201431009A (zh
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蔡宗賢
朱恆正
林建成
邱志賢
鍾興隆
朱育德
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矽品精密工業股份有限公司
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Priority to TW102102301A priority Critical patent/TWI499013B/zh
Priority to CN201310047475.1A priority patent/CN103943620B/zh
Priority to US14/087,554 priority patent/US9337250B2/en
Publication of TW201431009A publication Critical patent/TW201431009A/zh
Application granted granted Critical
Publication of TWI499013B publication Critical patent/TWI499013B/zh
Priority to US15/094,125 priority patent/US9997477B2/en

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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件及其製法，尤指一種打線型式之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，市面上的電子產品多以輕量、小型、高速及多功能為訴求。電子產品能否達到輕、薄、短、小、快之理想境界，取決於IC元件在高記憶容量、高操作頻率及低電壓需求之發展，惟IC元件能否持續提高記憶容量與操作頻率並降低電壓需求，端視IC元件上電子電路與電子元件積體化的程度、以及作為提供電子電路訊號與電源傳遞媒介所用之輸入/輸出接腳(I/O Connector)密度而定。
為了在一個半導體裝置中容納較多電子元件(Electronic Components)(如電容器、電阻器、電感器、振盪器(RF passive device)等之被動元件)以符合業界之需求，遂發展出球柵陣列(BGA)半導體裝置。
然而，某些半導體應用裝置，例如通訊或射頻(RF)半導體裝置中，常需要將電阻器、電感器、電容器及振盪 器等複數被動元件電性連接至所封裝之半導體晶片，俾使該半導體晶片具有特定之電流特性。以BGA半導體裝置為例，複數被動元件雖安置於基板表面，但是為了避免該等被動元件阻礙半導體晶片與複數電性連接墊(Bonding Fingers)間之電性連結及配置，傳統上多將該等被動元件安置於基板角端位置或半導體晶片接置區域以外的基板之額外佈局面積上。
惟，限定被動元件的設置位置將縮小基板線路佈局(Routability)之靈活性，且電性連接墊位置更會導致該等被動元件佈設數量受到侷限，不利半導體裝置高度集積化之發展趨勢。此外，被動元件之佈設數量隨著半導體封裝件高性能之要求而相對地遽增，如採用習知方法，該基板表面必須同時容納複數半導體晶片以及較多被動元件，而造成封裝基板面積加大，進而迫使封裝件體積增大，亦不符合半導體封裝件輕薄短小之發展潮流。
請參閱第1圖，基於上述問題，習知半導體封裝件1將複數被動元件11接置於半導體晶片13與電性連接墊100之間之區域上。然而，隨著半導體裝置內單位面積上之輸出/輸入連接端數量的增加，銲線14數量亦隨之提昇，且一般被動元件11之高度(0.8毫米)係高於半導體晶片13(0.55毫米)，因此為避免銲線14觸及被動元件11而造成短路，銲線14需拉高並橫越該被動元件11之正上方，提昇銲接困難度，亦使得線弧(Wire Loop)長度增加。又，銲線14本身具有重量，拉高之銲線14若缺乏支撐，易因本 身重力崩塌(Sag)觸及被動元件11而產生短路，且銲線14本身係由金、鋁材質製成，故此法不僅增加製程複雜性，且增長銲線14之線弧長度將明顯提升銲線14成本。
因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：基板，其一表面上形成有複數電性連接墊與複數圍繞該等電性連接墊的打線墊；複數被動元件，係設置於該基板的電性連接墊上；絕緣層，係形成於該基板之該表面上，以令部份該被動元件嵌埋於其中；半導體晶片，係設於該絕緣層之頂面上，該半導體晶片在垂直基板方向的投影區域係部分涵蓋最外側之該被動元件；複數銲線，係電性連接該半導體晶片與該打線墊；以及封裝膠體，係形成於該基板之該表面上，俾使該絕緣層、銲線及半導體晶片嵌埋於其中。
本發明復提供一種半導體封裝件之製法，係包括：提供一表面上形成有複數電性連接墊與複數圍繞該等電性連接墊的打線墊之基板；設置並電性連接複數被動元件於該電性連接墊上；於該基板之該表面上形成絕緣層，使部分該被動元件嵌埋於其中；於該絕緣層之頂面上設置半導體晶片，並藉由複數銲線使該半導體晶片電性連接至該打線墊，該半導體晶片在垂直基板方向的投影區域係部分涵蓋最外側之該被動元件；以及於該基板之該表面上形成封裝 膠體，俾使該絕緣層、銲線及半導體晶片嵌埋於其中。
於本發明之半導體封裝件之一實施例中，該半導體晶片在垂直基板方向的投影區域係部分涵蓋最外側之該被動元件，並使其突出該投影區域邊緣0.1至1.5毫米，以避免習知銲線易觸及被動元件所造成之短路問題。
於本發明之半導體封裝件中，該被動元件係包括非射頻被動元件及射頻被動元件。
由上可知，本發明之半導體封裝件及其製法係藉由將半導體晶片設置於嵌埋有被動元件之絕緣層上，以克服習知技術中將被動元件設置於基板角端或額外佈局於基板上之缺點，可有效提升被動元件之設置密度。
此外，本發明之半導體封裝件及其製法更藉由使該半導體晶片在垂直基板方向的投影區域完全或部分涵蓋最外側之該被動元件，能降低製程複雜性，且有效降低銲線之線弧長度。
1、2、3‧‧‧半導體封裝件
100、200a‧‧‧電性連接墊
200b‧‧‧打線墊
11、21‧‧‧被動元件
13、23‧‧‧半導體晶片
14、24‧‧‧銲線
20‧‧‧基板
21a‧‧‧射頻被動元件
21b‧‧‧非射頻被動元件
22‧‧‧絕緣層
25‧‧‧封裝膠體
D‧‧‧距離
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2D圖係為本發明之半導體封裝件之製法的第一實施例之剖面示意圖；以及第3圖係為本發明之半導體封裝件之第二實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解 本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「圍繞」、「頂」、「突出」、「投影區域」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
第2A至2D圖係為本發明之半導體封裝件2之製法的第一實施例之剖面示意圖。
如第2A圖所示，提供一表面上形成有複數電性連接墊200a與複數圍繞該等電性連接墊200a的打線墊200b之基板20，於該電性連接墊200a上設置並電性連接複數被動元件21，該等被動元件21係包括至少一射頻被動元件21a(例如石英振盪器、T/R開關或濾波器)及複數非射頻被動元件21b(例如電阻、電容或電感)，該等非射頻被動元件21b係圍繞於該射頻被動元件21a之外圍。
如第2B圖所示，於該基板20之該表面上形成絕緣層22，以令該射頻被動元件21a嵌埋於其中。
於本實施例中，對於該絕緣層22之形成方式與材料並未有特殊限制，於此不再贅述。
如第2C圖所示，於該絕緣層22之頂面上設置半導體晶片23，並使該半導體晶片23藉由銲線24電性連接至該基板20之打線墊200b，部分該非射頻被動元件21b係突出於該半導體晶片23在垂直基板20方向的投影區域一段距離D，即該半導體晶片23在垂直基板20方向的投影區域係部分涵蓋最外側之該被動元件21。
如第2D圖所示，形成封裝膠體25於該基板20之該表面上，以包覆該絕緣層22、半導體晶片23、非射頻被動元件21b及銲線24，而製得本發明之半導體封裝件2。
於本實施例中，有關封裝膠體25之形成方式及材料，在此不再贅述。
本實施例經實際測試後，發現該距離D於介於0.1至1.5毫米之間時，能有效防止用以電性連接該半導體晶片23與打線墊200b之銲線24觸及非射頻被動元件21b而短路之問題。
第二實施例
第3圖係為本發明之半導體封裝件3的第二實施例之剖面示意圖，本實施例大致相同於前一實施例，主要不同之處在於該絕緣層22係包覆該等被動元件21，最外側之該被動元件21係突出於該半導體晶片23在垂直基板20方向的投影區域一段距離D，且該距離D係介於0.1至1.5毫米之間。至於本實施例之詳細製法係所屬技術領域具有 通常知識者依本說明書與圖式所能瞭解者，故不再贅述。
於本實施例中，該被動元件21可為非射頻被動元件或射頻被動元件，其中，該非射頻被動元件係包括但不限於電阻、電容及電感；該射頻被動元件係包括但不限於石英振盪器、T/R開關及濾波器。
本發明係提供一種半導體封裝件2,3，係包括：基板20，其一表面上形成有複數電性連接墊200a與複數圍繞該等電性連接墊200a的打線墊200b；複數被動元件21，係設置於該基板20的電性連接墊200a上；絕緣層22，係形成於該基板20之該表面上，以令部份該被動元件21嵌埋於其中；半導體晶片23，係設於該絕緣層22之頂面上，該半導體晶片23在基板20的投影區域係部分涵蓋最外側之該被動元件21；複數銲線24，係電性連接該半導體晶片23與該打線墊200b；以及封裝膠體25，係形成於該基板20之該表面上，俾使該絕緣層22、銲線24及半導體晶片23嵌埋於其中。
於前述實施例中，最外側之該被動元件21係突出於該半導體晶片23在基板20的投影區域一段距離D，該距離D係介於0.1至1.5毫米之間。
前述之半導體封裝件中，該等被動元件21係包括複數非射頻被動元件21b及一射頻被動元件21a。
於一實施例中，該射頻被動元件21a係被該絕緣層22所覆蓋，且該等非射頻被動元件21b係圍繞於該射頻被動元件21a之外圍。
綜上所述，本發明之半導體封裝件及其製法係先將被動元件設置於基板上，再將半導體晶片設置於該等被動元件上方，不僅能克服習知半導體封裝件將被動元件設置於基板角端位置或基板之額外佈局面積上之缺點，並可有效提升被動元件之設置密度，此外，本發明之半導體封裝件及其製法更藉由使該半導體晶片在垂直基板方向的投影區域完全或部分涵蓋最外側之該被動元件，以避免習知銲線易觸及被動元件所造成之短路問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧基板
200a‧‧‧電性連接墊
200b‧‧‧打線墊
21‧‧‧被動元件
21a‧‧‧射頻被動元件
21b‧‧‧非射頻被動元件
22‧‧‧絕緣層
23‧‧‧半導體晶片
24‧‧‧銲線
25‧‧‧封裝膠體
D‧‧‧距離

Claims (8)

  1. 一種半導體封裝件，係包括：基板，其一表面上形成有複數電性連接墊與複數圍繞該等電性連接墊的打線墊；複數被動元件，係設置於該基板的電性連接墊上；絕緣層，係形成於該基板之該表面上，以令部份該被動元件嵌埋於其中；半導體晶片，係設於該絕緣層之頂面上，該半導體晶片在垂直基板方向的投影區域係部分涵蓋最外側之該被動元件，其中，最外側之該被動元件係突出該投影區域邊緣0.1至1.5毫米；複數銲線，係電性連接該半導體晶片與該打線墊；以及封裝膠體，係形成於該基板之該表面上，俾使該絕緣層、銲線及半導體晶片嵌埋於其中。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該等被動元件係包括複數非射頻被動元件及至少一射頻被動元件。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該射頻被動元件係被該絕緣層所覆蓋。
  4. 如申請專利範圍第2項所述之半導體封裝件，其中，該等非射頻被動元件係圍繞於該射頻被動元件之外圍。
  5. 一種半導體封裝件之製法，係包括： 提供一表面上形成有複數電性連接墊與複數圍繞該等電性連接墊的打線墊之基板；設置並電性連接複數被動元件於該電性連接墊上；於該基板之該表面上形成絕緣層，使部分該被動元件嵌埋於其中；於該絕緣層之頂面上設置半導體晶片，並藉由複數銲線使該半導體晶片電性連接至該打線墊，該半導體晶片在垂直基板方向的投影區域係部分涵蓋最外側之該被動元件，其中，最外側之該被動元件係突出該投影區域邊緣0.1至1.5毫米；以及於該基板之該表面上形成封裝膠體，俾使該絕緣層、銲線及半導體晶片嵌埋於其中。
  6. 如申請專利範圍第5項所述之半導體封裝件之製法，其中，該等被動元件係包括複數非射頻被動元件及至少一射頻被動元件。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該射頻被動元件係被該絕緣層所覆蓋。
  8. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該等非射頻被動元件係圍繞於該射頻被動元件之外圍。
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US20140203395A1 (en) 2014-07-24
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US9997477B2 (en) 2018-06-12
US20160225728A1 (en) 2016-08-04
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