TWI550816B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI550816B
TWI550816B TW102100528A TW102100528A TWI550816B TW I550816 B TWI550816 B TW I550816B TW 102100528 A TW102100528 A TW 102100528A TW 102100528 A TW102100528 A TW 102100528A TW I550816 B TWI550816 B TW I550816B
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Taiwan
Prior art keywords
substrate
electrical connection
connection pad
semiconductor
semiconductor component
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TW102100528A
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English (en)
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TW201428926A (zh
Inventor
黃富堂
柯俊吉
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102100528A priority Critical patent/TWI550816B/zh
Priority to CN201310015592.XA priority patent/CN103915418B/zh
Priority to US13/855,221 priority patent/US20140191376A1/en
Publication of TW201428926A publication Critical patent/TW201428926A/zh
Application granted granted Critical
Publication of TWI550816B publication Critical patent/TWI550816B/zh
Priority to US15/669,273 priority patent/US10192834B2/en

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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種具電磁屏蔽功能之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，市面上的電子產品以輕量、小型、高速及多功能為訴求，使產品內部的半導體封裝件，朝高運算速度、高元件密度、高複雜度發展，更將其他生物、光學、機械、電機、磁性等多功能之電子元件整合於同一晶片中。
為符合半導體封裝件體積輕薄短小的趨勢，系統級封裝(System in Package，SiP)發展出晶片堆疊(stacked die)的封裝結構。然而，此種結構使元件密度增加，導致上、下晶片間產生電磁干擾(electromagnetic interference，EMI)之現象。
為解決上、下晶片間電磁干擾的問題，習知技術係於上晶片的底面以濺鍍方式形成金屬層，使該金屬層位於上晶片(top die)及下晶片(bottom die)之間，並將該金屬層接地之後可達成電磁屏蔽(EMI shielding)的效果。
請參閱第1圖，係為目前業界開發之半導體封裝件1之剖面示意圖。如第1圖所示，習知半導體封裝件1包括：具有接地墊100之基板10；第一半導體元件11，設置並以導電凸塊電性連接於該基板10上；濺鍍有金屬層12之第二半導體元件13，係以該金屬層12之側設置於該第一半導體元件11上，且該金屬層12係接地連接至該基板10上之接地墊100；以及形成於基板10上之封裝膠體14，使該第一半導體元件11及第二半導體元件13嵌埋於該封裝膠體14中。
然而，習知技術係以濺鍍方式形成該金屬層12，而達成電磁屏蔽(EMI shielding)的效果，此方式之製程較為複雜，且成本較高。
因此，如何克服習知技術中之電磁干擾之問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：基板；第一半導體元件，係設於該基板上，且該第一半導體元件具有接地連接該基板之第一電性連接墊；導電層，係形成於該第一半導體元件上且電性連接該第一電性連接墊；第二半導體元件，係設於該導電層上；以及封裝膠體，係形成於該基板上，以包覆該第一及第二半導體元件。
前述之半導體封裝件之製法，係包括：提供一基板；設置第一半導體元件於該基板上，且該第一半導體元件具 有第一電性連接墊；接地連接該第一電性連接墊及該基板；形成導電層於該第一半導體元件上，且該導電層係電性連接該第一電性連接墊；設置第二半導體元件於該導電層上；以及形成封裝膠體於該基板上，以包覆該第一及第二半導體元件。
前述之半導體封裝件及其製法中，該第一電性連接墊係以銲線接地連接至該基板。
前述之半導體封裝件及其製法中，該第一半導體元件具有位於該第一電性連接墊上之線路重佈結構，且該導電層設於該線路重佈結構上，以令該線路重佈結構電性連接該第一電性連接墊與導電層並接地連接至該基板。例如，該線路重佈結構復具有電性連接該第一電性連接墊之電性接觸墊，且該電性接觸墊係藉由銲線接地連接該基板。
前述之半導體封裝件及其製法中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一電性連接墊。
本發明復提供一種半導體封裝件，係包括：基板；第一半導體元件，係設於該基板上，且該第一半導體元件具有相互電性連接之第一電性連接墊與第二電性連接墊，該第二電性連接墊係接地連接至該基板；導電層，係形成於該第一半導體元件上且電性連接該第一電性連接墊；第二半導體元件，係固設於該導電層上；以及封裝膠體，係形成於該基板上，以包覆該第一及第二半導體元件。
前述之半導體封裝件之製法，係包括：提供一基板； 設置第一半導體元件於該基板上，且該第一半導體元件具有相互電性連接之第一電性連接墊與第二電性連接墊；接地連接該第二電性連接墊及該基板；形成導電層於該第一半導體元件上，且該導電層係電性連接該第一電性連接墊；設置第二半導體元件於該導電層上；以及形成封裝膠體於該基板上，以包覆該第一及第二半導體元件。
前述之半導體封裝件及其製法中，該第一電性連接墊係以銲線電性連接該第二電性連接墊。或者，該第一半導體元件復具有內部線路，以供該第一電性連接墊藉由該內部線路電性連接該第二電性連接墊。
前述之半導體封裝件及其製法中，該第二電性連接墊係以銲線接地連接至該基板。
前述之半導體封裝件及其製法中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一及第二電性連接墊。
前述之兩種半導體封裝件及其製法中，該基板具有接地用之接地墊。
前述之兩種半導體封裝件及其製法中，該第二半導體元件係電性連接該基板。
前述之兩種半導體封裝件及其製法中，該導電層之材質為導電膠。
另外，前述之兩種半導體封裝件及其製法中，復包括設置電子元件於該基板上，且接地連接該基板與該第一半導體元件。
由上可知，本發明之半導體封裝件及其製法中，藉由設置於第一半導體元件與第二半導體元件之間的導電層達到電磁屏蔽的效果，以避免半導體元件間之電磁干擾。
1、2、3、4、5、6‧‧‧半導體封裝件
10、20‧‧‧基板
100、200‧‧‧接地墊
11、21‧‧‧第一半導體元件
12‧‧‧金屬層
13、23‧‧‧第二半導體元件
14、24‧‧‧封裝膠體
201‧‧‧接地孔
210、70‧‧‧內部線路
211、211'、71‧‧‧第一電性連接墊
212、212'、72‧‧‧第二電性連接墊
213‧‧‧連接墊
22‧‧‧導電層
25‧‧‧銲線
30、30’‧‧‧線路重佈結構
300a、300b‧‧‧電性接觸墊
7‧‧‧電子元件
第1圖係為習知半導體封裝件之剖面示意圖；第2A至2D圖係為本發明之半導體封裝件之製法的剖面示意圖，其中，第2A’圖為第2A圖之俯視圖，第2B’圖為第2B圖之俯視圖，以及第2C’圖為第2C圖之俯視圖；第3及3’圖係為本發明半導體封裝件之一實施例之剖面及俯視示意圖，其中，第3’圖係為第3圖之俯視圖；第4及4’圖係為本發明半導體封裝件之另一實施例之剖面示意圖，其中，第4’圖係為第4圖之俯視圖；第5圖係為本發明半導體封裝件之再一實施例之剖面示意圖；第6圖係為本發明半導體封裝件之又一實施例之剖面示意圖；以及第7圖係為本發明半導體封裝件之另一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之半導體封裝件2之製法的剖面示意圖，其中，第2A’圖為第2A圖之俯視圖；第2B’圖為第2B圖之俯視圖；以及第2C’圖為第2C圖之俯視圖。
如第2A及2A’圖所示，提供一具有複數接地墊200及接地孔201之基板20，並設置一第一半導體元件21於該基板20上，且該第一半導體元件21具有複數用以接地連接該基板20之第一電性連接墊211。
於本實施例中，該第一電性連接墊211係以銲線25電性連接該接地墊200。
再者，該第一半導體元件21係為晶片或經封裝之元件。
如第2B圖所示，形成一導電層22於該第一半導體元件21上，且該導電層22係覆蓋該第一電性連接墊211，並包覆銲線25連接該第一電性連接墊211之一端，以電性連接各該第一電性連接墊211。
於本實施例中，該第一半導體元件21亦具有其它之連接墊213，但該導電層22並未覆蓋於該些連接墊213上，如第2B’圖所示。
再者，形成該導電層22之材質為含有金屬材質之導電膠，且該金屬材料具有屏障並阻絕電磁干擾之功能，藉以達到電磁屏蔽之效果。
如第2C圖所示，設置一第二半導體元件23於該導電層22上，使該第二半導體元件23堆疊於該第一半導體元件21上，並令該第二半導體元件23電性連接於該基板20。
於本實施例中，該第二半導體元件23係以銲線25電性連接至該基板20。
再者，該第二半導體元件23係為晶片或經封裝之元件。
如第2D圖所示，形成封裝膠體24於該基板20上，以包覆該第一半導體元件21及第二半導體元件23，而製成本發明之半導體封裝件2。
於本實施例中，有關封裝膠體24之形成方式及材料，為習知者即能適用，在此不再贅述。
於一實施例中，如第3及3’圖所示，該第一半導體元件21復具有電性連接該第一電性連接墊211之第二電性連接墊212，且該第二電性連接墊212係以銲線25電性連接至該基板20，其中，該第一電性連接墊211係以銲線25電性連接該第二電性連接墊212。
於另一態樣中，如第4及4’圖所示，該第一半導體元 件21復具有內部線路210，以電性連接該第一電性連接墊211與該第二電性連接墊212。
於另一實施例中，如第5圖所示，該第一半導體元件21具有位於該第一電性連接墊211上之線路重佈結構30，且該導電層22設置並電性連接於該線路重佈結構30上，其中，該線路重佈結構30具有電性連接該第一電性連接墊211之電性接觸墊300a,300b，又其中一部分之該電性接觸墊300b係藉由銲線25接地連接該基板20。
於另一態樣中，如第6圖所示，亦可將該些相互電性連接之第一電性連接墊211’及第二電性連接墊212’形成於線路重佈結構30’之中。
本發明係利用該導電層22之設計，能有效將餘電導出到該基板20以進行接地，以克服該第一半導體元件21與第二半導體元件23間之電磁干擾之問題，使本發明之半導體封裝件2,3,4,5,6具有更佳之電磁屏蔽效果。
另外，如第7圖所示，係增設一電子元件7於該半導體封裝件2之基板20上，且該電子元件7係接地連接至該基板20與第一電性連接墊211。
於本實施例中，該電子元件7係可視為第4圖所示之半導體封裝件4之晶片結構，使該電子元件7之第二電性連接墊72係用以接地連接該基板20及電性連接該半導體封裝件2之第一電性連接墊211，且該電子元件7之第一電性連接墊71係藉由內部線路70電性連接該電子元件7之第二電性連接墊72。
本發明係提供一種半導體封裝件2,3,4,5,6，係包括：一基板20、設於該基板20上之一第一半導體元件21、形成於該第一半導體元件21上之一導電層22、固設於該導電層22上之一第二半導體元件23、以及形成於該基板20上之封裝膠體24。
所述之基板20具有複數接地墊200。
所述之第一半導體元件21係具有以銲線25接地連接至該接地墊200之複數第一電性連接墊211。
於一實施例中，該第一半導體元件21復具有以銲線25或內部線路電性連接該第一電性連接墊211之第二電性連接墊212，且該第二電性連接墊212係以銲線25電性連接至該基板20。
所述之導電層22係電性連接該第一電性連接墊211。
於一實施例中，該導電層22之材質為導電膠。
所述之第二半導體元件22係電性連接該基板20。
所述之封裝膠體24係包覆該第一及第二半導體元件21,22。
於一實施例中，該第一半導體元件21具有位於該第一電性連接墊211上之線路重佈結構30，且該導電層22設於該線路重佈結構30上，以令該線路重佈結構30電性連接該第一電性連接墊211與導電層22並接地連接至該基板20。具體地，該線路重佈結構30復具有電性連接該第一電性連接墊211之電性接觸墊300a,300b，且該電性接觸墊300b係藉由銲線25接地連接該基板20。
於另一實施例中，線路重佈結構30’係具有該第一電性連接墊211’。
綜上所述，本發明之半導體封裝件及其製法，藉由導電層之設計，不僅克服習知半導體封裝件，使用晶片堆疊結構產生電磁干擾之缺點，更賦予其具有製程簡單、成本低及應用更為廣泛等優點。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧基板
200‧‧‧接地墊
201‧‧‧接地孔
21‧‧‧第一半導體元件
211‧‧‧第一電性連接墊
213‧‧‧連接墊
22‧‧‧導電層
23‧‧‧第二半導體元件
24‧‧‧封裝膠體
25‧‧‧銲線

Claims (28)

  1. 一種半導體封裝件，係包括：基板；第一半導體元件，係設於該基板上，且該第一半導體元件具有接地連接該基板之第一電性連接墊；導電層，係形成於該第一半導體元件上，並覆蓋於該第一電性連接墊，且接觸並電性連接該第一電性連接墊；第二半導體元件，係設於該導電層上；以及封裝膠體，係形成於該基板上，以包覆該第一及第二半導體元件。
  2. 一種半導體封裝件，係包括：基板；第一半導體元件，係設於該基板上，且該第一半導體元件具有相互電性連接之第一電性連接墊與第二電性連接墊，該第二電性連接墊係接地連接至該基板；導電層，係形成於該第一半導體元件上，並覆蓋於該第一電性連接墊，且接觸並電性連接該第一電性連接墊；第二半導體元件，係固設於該導電層上；以及封裝膠體，係形成於該基板上，以包覆該第一及第二半導體元件。
  3. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該基板具有接地用之接地墊。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一電性連接墊係以銲線接地連接至該基板。
  5. 如申請專利範圍第2項所述之半導體封裝件，其中，該第二電性連接墊係以銲線接地連接至該基板。
  6. 如申請專利範圍第2項所述之半導體封裝件，其中，該第一電性連接墊係以銲線電性連接該第二電性連接墊。
  7. 如申請專利範圍第2項所述之半導體封裝件，其中，該第一半導體元件復具有內部線路，以供該第一電性連接墊藉由該內部線路電性連接該第二電性連接墊。
  8. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該第二半導體元件係電性連接該基板。
  9. 一種半導體封裝件，係包括：基板；第一半導體元件，係設於該基板上，且該第一半導體元件具有接地連接該基板之第一電性連接墊與接觸並電性連接該第一電性連接墊之線路重佈結構，其中，該線路重佈結構復具有電性連接該第一電性連接墊之電性接觸墊；導電層，係設於該線路重佈結構上，並覆蓋於該電性接觸墊，以令該線路重佈結構電性連接該第一電性連接墊與導電層並接地連接至該基板；第二半導體元件，係設於該導電層上；以及封裝膠體，係形成於該基板上，以包覆該第一及 第二半導體元件。
  10. 如申請專利範圍第9項所述之半導體封裝件，其中，該電性接觸墊係藉由銲線接地連接該基板。
  11. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一電性連接墊。
  12. 如申請專利範圍第2項所述之半導體封裝件，其中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一及第二電性連接墊。
  13. 如申請專利範圍第1或2項所述之半導體封裝件，其中，該導電層之材質係為導電膠。
  14. 如申請專利範圍第1或2項所述之半導體封裝件，復包括電子元件，係置於該基板上，且接地連接該基板與該第一半導體元件。
  15. 一種半導體封裝件之製法，係包括：提供一基板；設置第一半導體元件於該基板上，且該第一半導體元件具有第一電性連接墊；接地連接該第一電性連接墊及該基板；形成導電層於該第一半導體元件上，並覆蓋於該第一電性連接墊，且該導電層係接觸並電性連接該第一電性連接墊；設置第二半導體元件於該導電層上；以及形成封裝膠體於該基板上，以包覆該第一及第二 半導體元件。
  16. 一種半導體封裝件之製法，係包括：提供一基板；設置第一半導體元件於該基板上，且該第一半導體元件具有相互電性連接之第一電性連接墊與第二電性連接墊；接地連接該第二電性連接墊及該基板；形成導電層於該第一半導體元件上，並覆蓋於該第一電性連接墊，且該導電層係接觸並電性連接該第一電性連接墊；設置第二半導體元件於該導電層上；以及形成封裝膠體於該基板上，以包覆該第一及第二半導體元件。
  17. 如申請專利範圍第15或16項所述之半導體封裝件之製法，其中，該基板具有接地用之接地墊。
  18. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該第一電性連接墊係以銲線接地連接至該基板。
  19. 如申請專利範圍第16項所述之半導體封裝件之製法，其中，該第二電性連接墊係以銲線接地連接至該基板。
  20. 如申請專利範圍第16項所述之半導體封裝件之製法，其中，該第一電性連接墊係以銲線電性連接該第二電性連接墊。
  21. 如申請專利範圍第16項所述之半導體封裝件之製法，其中，該第一半導體元件復具有內部線路，以供該第 一電性連接墊藉由該內部線路電性連接該第二電性連接墊。
  22. 如申請專利範圍第15或16項所述之半導體封裝件之製法，其中，該第二半導體元件係電性連接該基板。
  23. 一種半導體封裝件之製法，係包括：提供一基板；設置第一半導體元件於該基板上，且該第一半導體元件具有第一電性連接墊與接觸並電性連接該第一電性連接墊之線路重佈結構，其中，該線路重佈結構復具有電性連接該第一電性連接墊之電性接觸墊；接地連接該線路重佈結構及該基板；形成導電層於該線路重佈結構上，並覆蓋於該電性接觸墊，且該導電層係接觸並電性連接該線路重佈結構之電性接觸墊，以令該線路重佈結構電性連接該第一電性連接墊與導電層並接地連接至該基板；設置第二半導體元件於該導電層上；以及形成封裝膠體於該基板上，以包覆該第一及第二半導體元件。
  24. 如申請專利範圍第23項所述之半導體封裝件之製法，其中，該電性接觸墊係藉由銲線接地連接該基板。
  25. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一電性連接墊。
  26. 如申請專利範圍第16項所述之半導體封裝件之製法， 其中，該第一半導體元件具有線路重佈結構，且該線路重佈結構具有該第一及第二電性連接墊。
  27. 如申請專利範圍第15或16項所述之半導體封裝件之製法，其中，該導電層之材質為導電膠。
  28. 如申請專利範圍第15或16項所述之半導體封裝件之製法，復包括設置電子元件於該基板上，且接地連接該基板與該第一半導體元件。
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