CN103915418B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103915418B
CN103915418B CN201310015592.XA CN201310015592A CN103915418B CN 103915418 B CN103915418 B CN 103915418B CN 201310015592 A CN201310015592 A CN 201310015592A CN 103915418 B CN103915418 B CN 103915418B
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substrate
connection pad
electric connection
semiconductor
semiconductor subassembly
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CN103915418A (zh
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黄富堂
柯俊吉
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件，包括：基板；第一半导体组件，其设于该基板上，且该第一半导体组件具有接地连接该基板的第一电性连接垫；形成于该第一半导体组件上的导电层，且该导电层电性连接该基板；第二半导体组件，其通过该导电层设于该第一半导体组件上；以及形成于该基板上的封装胶体，使该第一半导体组件及第二半导体组件嵌埋于该封装胶体中，以利用导电层电性连接该基板的接地垫达到电磁屏蔽的效果。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种具电磁屏蔽功能的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，市面上的电子产品以轻量、小型、高速及多功能为诉求，使产品内的半导体封装件，朝高运算速度、高组件密度、高复杂度发展，更将其它生物、光学、机械、电机、磁性等多功能的电子组件整合于同一芯片中。
为符合半导体封装件体积轻薄短小的趋势，系统级封装(System in Package，SiP)发展出芯片堆栈(stacked die)的封装结构。然而，此种结构使组件密度增加，导致上、下芯片间产生电磁干扰(electromagnetic interference，EMI)的现象。
为解决上、下芯片间电磁干扰的问题，现有技术通过于上芯片的底面以溅镀方式形成金属层，使该金属层位于上芯片(top die)及下芯片(bottom die)之间，并将该金属层接地之后可达成电磁屏蔽(EMI shielding)的效果。
请参阅图1，其为目前业界开发的半导体封装件1的剖面示意图。如图1所示，现有半导体封装件1包括：具有接地垫100的基板10；第一半导体组件11，设置并以导电凸块电性连接于该基板10上；溅镀有金属层12的第二半导体组件13，其以该金属层12之侧设置于该第一半导体组件11上，且该金属层12接地连接至该基板10上的接地垫100；以及形成于基板10上的封装胶体14，使该第一半导体组件11及第二半导体组件13嵌埋于该封装胶体14中。
然而，现有技术以溅镀方式形成该金属层12，而达成电磁屏蔽(EMI shielding)的效果，此方式的工艺较为复杂，且成本较高。
因此，如何克服现有技术中的电磁干扰的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺点，本发明的主要目的在于提供一种半导体封装件及其制法，利用导电层电性连接该基板的接地垫达到电磁屏蔽的效果。
本发明的半导体封装件，其包括：基板；第一半导体组件，其设于该基板上，且该第一半导体组件具有接地连接该基板的第一电性连接垫；导电层，其形成于该第一半导体组件上且电性连接该第一电性连接垫；第二半导体组件，其设于该导电层上；以及封装胶体，其形成于该基板上，以包覆该第一及第二半导体组件。
前述的半导体封装件的制法，其包括：提供一基板；设置第一半导体组件于该基板上，且该第一半导体组件具有第一电性连接垫；接地连接该第一电性连接垫及该基板；形成导电层于该第一半导体组件上，且该导电层电性连接该第一电性连接垫；设置第二半导体组件于该导电层上；以及形成封装胶体于该基板上，以包覆该第一及第二半导体组件。
前述的半导体封装件及其制法中，该第一电性连接垫以焊线接地连接至该基板。
前述的半导体封装件及其制法中，该第一半导体组件具有位于该第一电性连接垫上的线路重布结构，且该导电层设于该线路重布结构上，以令该线路重布结构电性连接该第一电性连接垫与导电层并接地连接至该基板。例如，该线路重布结构还具有电性连接该第一电性连接垫的电性接触垫，且该电性接触垫通过焊线接地连接该基板。
前述的半导体封装件及其制法中，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一电性连接垫。
本发明还提供一种半导体封装件，其包括：基板；第一半导体组件，其设于该基板上，且该第一半导体组件具有相互电性连接的第一电性连接垫与第二电性连接垫，该第二电性连接垫接地连接至该基板；导电层，其形成于该第一半导体组件上且电性连接该第一电性连接垫；第二半导体组件，其固设于该导电层上；以及封装胶体，其形成于该基板上，以包覆该第一及第二半导体组件。
前述的半导体封装件的制法，其包括：提供一基板；设置第一半导体组件于该基板上，且该第一半导体组件具有相互电性连接的第一电性连接垫与第二电性连接垫；接地连接该第二电性连接垫及该基板；形成导电层于该第一半导体组件上，且该导电层电性连接该第一电性连接垫；设置第二半导体组件于该导电层上；以及形成封装胶体于该基板上，以包覆该第一及第二半导体组件。
前述的半导体封装件及其制法中，该第一电性连接垫以焊线电性连接该第二电性连接垫。或者，该第一半导体组件还具有内部线路，以供该第一电性连接垫通过该内部线路电性连接该第二电性连接垫。
前述的半导体封装件及其制法中，该第二电性连接垫以焊线接地连接至该基板。
前述的半导体封装件及其制法中，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一及第二电性连接垫。
前述的两种半导体封装件及其制法中，该基板具有接地用的接地垫。
前述的两种半导体封装件及其制法中，该第二半导体组件电性连接该基板。
前述的两种半导体封装件及其制法中，该导电层的材质为导电胶。
另外，前述的两种半导体封装件及其制法中，还包括设置电子组件于该基板上，且接地连接该基板与该第一半导体组件。
由上可知，本发明的半导体封装件及其制法中，通过设置于第一半导体组件与第二半导体组件之间的导电层达到电磁屏蔽的效果，以避免半导体组件间的电磁干扰。
附图说明
图1为现有半导体封装件的剖面示意图；
图2A至图2D为本发明的半导体封装件的制法的剖面示意图，其中，图2A’为图2A的俯视图，图2B’为图2B的俯视图，以及图2C’为图2C的俯视图；
图3及图3’为本发明半导体封装件的一实施例的剖面及俯视示意图，其中，图3’为图3的俯视图；
图4及图4’为本发明半导体封装件的另一实施例的剖面示意图，其中，图4’为图4的俯视图；
图5为本发明半导体封装件的再一实施例的剖面示意图；
图6为本发明半导体封装件的又一实施例的剖面示意图；以及
图7为本发明半导体封装件的另一实施例的剖面示意图。
符号说明
1、2、3、4、5、6 半导体封装件
10、20 基板
100、200 接地垫
11、21 第一半导体组件
12 金属层
13、23 第二半导体组件
14、24 封装胶体
201 接地孔
210、70 内部线路
211、211'、71 第一电性连接垫
212、212'、72 第二电性连接垫
213 连接垫
22 导电层
25 焊线
30、30’ 线路重布结构
300a、300b 电性接触垫
7 电子组件。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的半导体封装件2的制法的剖面示意图，其中，图2A’为图2A的俯视图；图2B’为图2B的俯视图；以及图2C’为图2C的俯视图。
如图2A及图2A’所示，提供一具有多个接地垫200及接地孔201的基板20，并设置一第一半导体组件21于该基板20上，且该第一半导体组件21具有多个用以接地连接该基板20的第一电性连接垫211。
于本实施例中，该第一电性连接垫211以焊线25电性连接该接地垫200。
此外，该第一半导体组件21为芯片或经封装的组件。
如图2B所示，形成一导电层22于该第一半导体组件21上，且该导电层22覆盖该第一电性连接垫211，并包覆焊线25连接该第一电性连接垫211的一端，以电性连接各该第一电性连接垫211。
于本实施例中，该第一半导体组件21也具有其它的连接垫213，但该导电层22并未覆盖于该些连接垫213上，如图2B’所示。
此外，形成该导电层22的材质为含有金属材质的导电胶，且该金属材料具有屏障并阻绝电磁干扰的功能，藉以达到电磁屏蔽的效果。
如图2C所示，设置一第二半导体组件23于该导电层22上，使该第二半导体组件23堆栈于该第一半导体组件21上，并令该第二半导体组件23电性连接于该基板20。
于本实施例中，该第二半导体组件23以焊线25电性连接至该基板20。
此外，该第二半导体组件23为芯片或经封装的组件。
如图2D所示，形成封装胶体24于该基板20上，以包覆该第一半导体组件21及第二半导体组件23，而制成本发明的半导体封装件2。
于本实施例中，有关封装胶体24的形成方式及材料，为现有者即能适用，在此不再赘述。
于一实施例中，如图3及图3’所示，该第一半导体组件21还具有电性连接该第一电性连接垫211的第二电性连接垫212，且该第二电性连接垫212以焊线25电性连接至该基板20，其中，该第一电性连接垫211以焊线25电性连接该第二电性连接垫212。
于另一实施例中，如图4及图4’所示，该第一半导体组件21还具有内部线路210，以电性连接该第一电性连接垫211与该第二电性连接垫212。
于另一实施例中，如图5所示，该第一半导体组件21具有位于该第一电性连接垫211上的线路重布结构30，且该导电层22设置并电性连接于该线路重布结构30上，其中，该线路重布结构30具有电性连接该第一电性连接垫211的电性接触垫300a,300b，又其中一部分的该电性接触垫300b通过焊线25接地连接该基板20。
于另一实施例中，如图6所示，也可将该些相互电性连接的第一电性连接垫211’及第二电性连接垫212’形成于线路重布结构30’之中。
本发明利用该导电层22的设计，能有效将余电导出到该基板20以进行接地，以克服该第一半导体组件21与第二半导体组件23间的电磁干扰的问题，使本发明的半导体封装件2,3,4,5,6具有更佳的电磁屏蔽效果。
另外，如图7所示，通过增设一电子组件7于该半导体封装件2的基板20上，且该电子组件7接地连接至该基板20与第一电性连接垫211。
于本实施例中，该电子组件7可视为图4所示的半导体封装件4的芯片结构，使该电子组件7的第二电性连接垫72用以接地连接该基板20及电性连接该半导体封装件2的第一电性连接垫211，且该电子组件7的第一电性连接垫71通过内部线路70电性连接该电子组件7的第二电性连接垫72。
本发明提供一种半导体封装件2,3,4,5,6，其包括：一基板20、设于该基板20上的一第一半导体组件21、形成于该第一半导体组件21上的一导电层22、固设于该导电层22上的一第二半导体组件23、以及形成于该基板20上的封装胶体24。
所述的基板20具有多个接地垫200。
所述的第一半导体组件21具有以焊线25接地连接至该接地垫200的多个第一电性连接垫211。
于一实施例中，该第一半导体组件21还具有以焊线25或内部线路电性连接该第一电性连接垫211的第二电性连接垫212，且该第二电性连接垫212以焊线25电性连接至该基板20。
所述的导电层22电性连接该第一电性连接垫211。
于一实施例中，该导电层22的材质为导电胶。
所述的第二半导体组件23电性连接该基板20。
所述的封装胶体24包覆该第一及第二半导体组件21,23。
于一实施例中，该第一半导体组件21具有位于该第一电性连接垫211上的线路重布结构30，且该导电层22设于该线路重布结构30上，以令该线路重布结构30电性连接该第一电性连接垫211与导电层22并接地连接至该基板20。具体地，该线路重布结构30还具有电性连接该第一电性连接垫211的电性接触垫300a,300b，且该电性接触垫300b通过焊线25接地连接该基板20。
于另一实施例中，线路重布结构30’具有该第一电性连接垫211’。
综上所述，本发明的半导体封装件及其制法，通过导电层的设计，不仅克服现有半导体封装件，使用芯片堆栈结构产生电磁干扰的缺点，更赋予其具有工艺简单、成本低及应用更为广泛等优点。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (23)

1.一种半导体封装件，其包括：
基板；
第一半导体组件，其设于该基板上，且该第一半导体组件具有接地连接该基板的第一电性连接垫，该第一电性连接垫以焊线接地连接至该基板；
导电层，其形成于该第一半导体组件上并覆盖该第一电性连接垫，且接触并接地连接该第一电性连接垫，其中，该导电层的材质为导电胶，且覆盖部分该焊线；
第二半导体组件，其设于该导电层上；以及
封装胶体，其形成于该基板上，以包覆该第一及第二半导体组件。
2.一种半导体封装件，其包括：
基板；
第一半导体组件，其设于该基板上，且该第一半导体组件具有相互电性连接的第一电性连接垫与第二电性连接垫，该第二电性连接垫以焊线接地连接至该基板；
导电层，其形成于该第一半导体组件上并覆盖该第一电性连接垫，且接触并电性连接该第一电性连接垫，其中，该导电层的材质为导电胶，且覆盖部分该焊线；
第二半导体组件，其固设于该导电层上；以及
封装胶体，其形成于该基板上，以包覆该第一及第二半导体组件。
3.根据权利要求1或2所述的半导体封装件，其特征在于，该基板具有接地用的接地垫。
4.根据权利要求2所述的半导体封装件，其特征在于，该第一电性连接垫以焊线电性连接该第二电性连接垫。
5.根据权利要求2所述的半导体封装件，其特征在于，该第一半导体组件还具有内部线路，以供该第一电性连接垫通过该内部线路电性连接该第二电性连接垫。
6.根据权利要求1或2所述的半导体封装件，其特征在于，该第二半导体组件电性连接该基板。
7.根据权利要求1所述的半导体封装件，其特征在于，该第一半导体组件具有位于该第一电性连接垫上的线路重布结构，且该导电层设于该线路重布结构上，以令该线路重布结构电性连接该第一电性连接垫与导电层并接地连接至该基板。
8.根据权利要求7所述的半导体封装件，其特征在于，该线路重布结构还具有电性连接该第一电性连接垫的电性接触垫，且该电性接触垫通过焊线接地连接该基板。
9.根据权利要求1所述的半导体封装件，其特征在于，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一电性连接垫。
10.根据权利要求2所述的半导体封装件，其特征在于，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一及第二电性连接垫。
11.根据权利要求1或2所述的半导体封装件，其特征在于，该半导体封装件还包括电子组件，其置于该基板上，且接地连接该基板与该第一半导体组件。
12.一种半导体封装件的制法，其包括：
提供一基板；
设置第一半导体组件于该基板上，且该第一半导体组件具有第一电性连接垫；
以焊线接地连接该第一电性连接垫及该基板；
形成导电层于该第一半导体组件上并覆盖该第一电性连接垫，且该导电层接触并电性连接该第一电性连接垫，其中，该导电层的材质为导电胶，且覆盖部分该焊线；
设置第二半导体组件于该导电层上；以及
形成封装胶体于该基板上，以包覆该第一及第二半导体组件。
13.一种半导体封装件的制法，其包括：
提供一基板；
设置第一半导体组件于该基板上，且该第一半导体组件具有相互电性连接的第一电性连接垫与第二电性连接垫；
以焊线接地连接该第二电性连接垫及该基板；
形成导电层于该第一半导体组件上并覆盖该第一电性连接垫，且该导电层接触并电性连接该第一电性连接垫，其中，该导电层的材质为导电胶，且覆盖部分该焊线；
设置第二半导体组件于该导电层上；以及
形成封装胶体于该基板上，以包覆该第一及第二半导体组件。
14.根据权利要求12或13所述的半导体封装件的制法，其特征在于，该基板具有接地用的接地垫。
15.根据权利要求13所述的半导体封装件的制法，其特征在于，该第一电性连接垫以焊线电性连接该第二电性连接垫。
16.根据权利要求13所述的半导体封装件的制法，其特征在于，该第一半导体组件还具有内部线路，以供该第一电性连接垫通过该内部线路电性连接该第二电性连接垫。
17.根据权利要求12或13所述的半导体封装件的制法，其特征在于，该第二半导体组件电性连接该基板。
18.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一半导体组件具有位于该第一电性连接垫上的线路重布结构，且该导电层设于该线路重布结构上，以令该线路重布结构电性连接该第一电性连接垫与导电层并接地连接至该基板。
19.根据权利要求18所述的半导体封装件的制法，其特征在于，该线路重布结构还具有电性连接该第一电性连接垫的电性接触垫，且该电性接触垫通过焊线接地连接该基板。
20.根据权利要求12所述的半导体封装件的制法，其特征在于，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一电性连接垫。
21.根据权利要求13所述的半导体封装件的制法，其特征在于，该第一半导体组件具有线路重布结构，且该线路重布结构具有该第一及第二电性连接垫。
22.根据权利要求12或13所述的半导体封装件的制法，其特征在于，该导电层的材质为导电胶。
23.根据权利要求12或13所述的半导体封装件的制法，其特征在于，该制法还包括设置电子组件于该基板上，且接地连接该基板与该第一半导体组件。
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