CN103456703A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN103456703A
CN103456703A CN2012103842197A CN201210384219A CN103456703A CN 103456703 A CN103456703 A CN 103456703A CN 2012103842197 A CN2012103842197 A CN 2012103842197A CN 201210384219 A CN201210384219 A CN 201210384219A CN 103456703 A CN103456703 A CN 103456703A
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China
Prior art keywords
semiconductor package
package part
electric contact
substrate
semiconductor
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CN2012103842197A
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English (en)
Inventor
林建成
许聪贤
朱恒正
杨超雅
郑志铭
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN103456703A publication Critical patent/CN103456703A/zh
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：具有电性接触垫的基板、设于该基板上的半导体组件、形成于该半导体组件顶面及侧面上且延伸至该电性接触垫上的导电胶、以及设于该导电胶上的电子组件。借由该导电胶与电性接触垫作为屏蔽结构，使该半导体组件与电子组件间的电磁不会相互干扰。

Description

半导体封装件及其制法
技术领域
本发明关于一种半导体封装件，更详言之，本发明为一种防电磁干扰的半导体封装件及其制法。
背景技术
随着电子产品轻薄短小及系统整合的趋势，遂将一个或多个芯片、被动组件等不同的电子组件整合在同一个封装件中以形成系统级封装（System in package;SIP），但邻近的电子组件间容易互相电磁干扰（Electromagnetic Interference,EMI），且封装件中的电子组件的积集度日益增加，使得各该电子组件之间的相对位置越来越靠近，所以各该电子组件之间的EMI问题更显重要。
第7049682号美国专利揭露一种半导体封装件1a，如图1A所示，于一基板10a上排设且电性连接多个电子组件11a,14a，再以封装胶体15a包覆各该电子组件11a,14a以形成多个封装体12a，再以盖体13a分别盖设于各该封装体12a外，以防止各该电子组件11a,14a之间发生EMI现象。
然而，利用并排式（side by side）设置多个电子组件11a,14a，当该些电子组件11a,14a的数目增加时，该基板20的使用面积会随之增加，因而造成封装成本过高及整体封装结构尺寸过大等缺点。
此外，以盖体13a作为屏蔽结构的成本极高，不符合经济效益。
为解决上述问题，其使用垂直式的堆栈方法增加组件的数量，以节省基板的使用空间。如图1B所示，其为第8049119号美国专利所揭露的半导体封装件1b，其将一芯片11b覆晶结合于一内部具有第一屏蔽层100的基板10b上，且堆栈一电子组件14b于该芯片11b，该电子组件14b的底部以溅镀方式形成一第二屏蔽层140，并借由导电胶13b电性连接该第一与第二屏蔽层100,140，以借由第一与第二屏蔽层100,140防止该芯片11b与外部电子装置发生EMI现象，再进行模压（molding）工艺，使封装胶体15b包覆该电子组件14b，且该封装胶体15b形成有一开口150，以令该电子组件14b的部分表面外露于该开口150，从而供接置其它电子组件。
然而，现有半导体封装件1b中，利用溅镀方式形成该第二屏蔽层140，其生产成本仍过高。
此外，该封装胶体15b具有该开口150，所以于模压工艺时，模具必须针对不同尺寸的外形而设计，以形成所需的开口150大小，因而同一模具无法泛用于不同尺寸的电子组件14b，以致于生产成本提高。
然而，如何克服现有技术的种种问题，实为一重要课题。
发明内容
为解决上述现有技术的种种问题，本发明的主要目的在于揭露一种半导体封装件及其制法，使该半导体组件与电子组件间的电磁不会相互干扰。
本发明的半导体封装件，包括：一基板，具有多个第一电性接触垫与至少一第二电性接触垫；至少一半导体组件，设于该基板上且电性连接该些第一电性接触垫；以及导电胶，形成于该半导体组件上且延伸至该基板的第二电性接触垫上，以令该导电胶与该第二电性接触垫构成屏蔽结构。
前述的半导体封装件中，该导电胶沿该半导体组件的侧面延伸至该第二电性接触垫上。
本发明还提供一种半导体封装件的制法，包括：提供一具有多个第一电性接触垫与至少一第二电性接触垫的基板；设置至少一半导体组件于该基板上，且该半导体组件电性连接该些第一电性接触垫；以及形成导电胶于该半导体组件上，以覆盖该半导体组件，且该导电胶由该半导体组件延伸至该基板的第二电性接触垫上，以令该导电胶与该第二电性接触垫构成屏蔽结构。
前述的制法中，形成该导电胶的方式为点胶工艺、网版涂布工艺、转印工艺或膜贴工艺。
前述的半导体封装件及其制法，该基板中还具有导电孔，以电性连接该第二电性接触垫。该导电孔为接地孔。
前述的半导体封装件及其制法，该第二电性接触垫为接地垫。
前述的半导体封装件及其制法，该半导体组件借由多个导电凸块电性连接该些第一电性接触垫，且还包括形成底胶于该半导体组件与该基板之间，以包覆该些导电凸块。
前述的半导体封装件及其制法，该基板还具有多个第三电性接触垫，且还包括设置至少一电子组件于该导电胶上，且该电子组件电性连接该些第三电性接触垫；该电子组件为封装体或芯片。还包括形成封装胶体于该基板上，以包覆该半导体组件、电子组件与该导电胶。
另外，前述的半导体封装件及其制法，还包括形成底胶于该半导体组件与该基板之间，使该导电胶还形成于该底胶上。
由上可知，本发明半导体封装件及其制法，借由该半导体组件的表面形成导电胶，且将导电胶连接到第二电性接触垫上，使该导电胶具有接地效果，所以于导电胶上堆栈电子组件，可避免该半导体组件与电子组件的电磁相互干扰。
此外，形成该导电胶的材质的方式相当简单，所以相比于现有溅镀方式或制作盖体的方式，本发明能有效降低生产成本。
再者，该封装胶体无需形成开口，所以于模压工艺时，模具不须考量开口大小，因而同一模具能泛用于不同尺寸的电子组件，以达到降低生产成本的目的。
附图说明
图1A为显示第7049682号美国专利的半导体封装件的剖面示意图；
图1B为显示第8049119号美国专利的半导体封装件的剖面示意图；
图2A至图2C为本发明半导体封装件的制法的剖面示意图；以及
图2D至图2E为本发明半导体封装件的制法的另一实施例的剖面示意图。
主要组件符号说明
1a、1b、2、3    半导体封装件
10a、10b、20        基板
100                 第一屏蔽层
11a、14a、14b、24   电子组件
11b                 芯片
12a                 封装体
13a                 盖体
13b                 导电胶
140                 第二屏蔽层
15a、15b、25        封装胶体
150                 开口
201                 第一电性接触垫
202                 第二电性接触垫
203                 第三电性接触垫
204                 导电孔
21                  半导体组件
21a                 作用面
21b                 非作用面
21c、22a            侧面
210                 导电凸块
22                  底胶
23                  导电胶
240                 焊线
S                   屏蔽结构。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“侧面”、“第一”、“第二”、“第三”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
以下即配合图2A至图2C详细说明本发明的半导体封装件2的制法。
如图2A所示，提供一基板20，该基板20具有多个第一电性接触垫201、多个第二电性接触垫202与多个导电孔204，且该些导电孔204电性连接该些第二电性接触垫202。
于本实施例中，该第二电性接触垫202为接地垫，且该导电孔204为接地孔。
此外，于其它实施例中，可依需求，仅形成一个第二电性接触垫202。
再者，该基板20中还形成有其它功能的导电孔或线路（图略）。
另外，有关基板20及其内部结构的种类繁多，并不限于上述，特此述明。
如图2B所示，设置一半导体组件21于该基板20上，且该半导体组件21借由多个导电凸块210电性连接该些第一电性接触垫201。
接着，形成底胶22于该半导体组件21与该基板20之间，以包覆该些导电凸块210。
于本实施例中，该半导体组件21为半导体芯片，且具有相对的作用面21a与非作用面21b及侧面21c，该作用面21a用以结合该些导电凸块210，以令该半导体组件21接置于该基板20上。
如图2C所示，形成导电胶23于该半导体组件21的非作用面21b与侧面21c上以覆盖该半导体组件21，且该导电胶23由该半导体组件21的侧面21c沿该底胶22的侧面22a延伸至该基板20的第二电性接触垫202上，以令该导电胶23与该第二电性接触垫202构成屏蔽结构S。
于本实施例中，该导电胶23为导电胶，且形成该导电胶23的方式为点胶工艺、网版涂布（screen printing）工艺、转印（transfer printing）工艺或膜贴（film type adhesive layer）工艺。
图2D至图2E为本发明的半导体封装件3的制法的另一实施例。本实施例与上述实施例的相同处不再赘述。
如图2D所示，该基板20还具有多个第三电性接触垫203，且该第二电性接触垫202的位置不干涉该第三电性接触垫203的位置。
接着，经上述图2A至图2C的工艺后，设置一电子组件24于该导电胶23上，且该电子组件24借由多个焊线240电性连接该些第三电性接触垫203。
于本实施例中，该电子组件24为封装体或芯片。
如图2E所示，进行模压工艺，以形成封装胶体25于该基板20上，使该封装胶体25包覆该电子组件24、焊线240与该导电胶23，以完成另一半导体封装件3的制作。
本发明的制法中，借由该半导体组件21的表面形成该导电胶23以作为屏蔽层，再于导电胶23上堆栈电子组件24，以避免该半导体组件21与电子组件24间的电磁相互干扰，所以使该半导体组件21与电子组件24可保持应有的功效。
此外，于单一封装件内进行组件堆栈，所以能节省该基板20的使用空间。
再者，该封装胶体25无需形成开口，所以于模压工艺时，模具不须考量开口大小，也就是模具不需针对不同尺寸的外形作设计。因此，同一模具能泛用于不同尺寸的基板20、电子组件24或芯片，所以本发明的制法有效降低生产成本。
另外，形成该导电胶23的材质为胶体，而形成胶体的方式相当简单，所以相比于现有溅镀方式或制作盖体的方式，本发明能有效降低生产成本。
本发明提供一种半导体封装件3，其包括：一基板20、一半导体组件21、底胶22、导电胶23、一电子组件24以及封装胶体25。
所述的基板20具有多个第一电性接触垫201、第二电性接触垫202、第三电性接触垫203与导电孔204，该第二电性接触垫202为接地垫，且该导电孔204为接地孔并电性连接该第二电性接触垫202。
所述的半导体组件21设于该基板20上，且借由多个导电凸块210电性连接该些第一电性接触垫201。
所述的底胶22形成于该半导体组件21与该基板20之间，以包覆该些导电凸块210。
所述的导电胶23为导电胶，其形成于该半导体组件21上且沿该底胶22的侧面22a延伸至该第二电性接触垫202上，以令该导电胶23与该第二电性接触垫202构成屏蔽结构S。
所述的电子组件24为封装体或芯片，其设于该导电胶23上，且借由多个焊线240电性连接该些第三电性接触垫203。
所述的封装胶体25形成于该基板20上，以包覆该电子组件24、该些焊线240与该导电胶23。
综上所述，本发明的半导体封装件及其制法中，主要借由导电胶与第二电性接触垫作为屏蔽结构，使该半导体组件与电子组件间的电磁不会相互干扰。
此外，形成该导电胶的方式相当简单，所以能有效降低生产成本。
再者，该封装胶体无需形成开口，所以于模压工艺时，模具不须考量开口大小，因而同一模具能泛用于不同尺寸的基板或芯片，以达到降低生产成本的目的。
上述该些实施样态仅例示性说明本发明的功效，而非用于限制本发明，任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述该些实施例进行修饰与改变。此外，在上述该些实施例中的组件的数量仅为例示性说明，亦非用于限制本发明。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种半导体封装件，包括：
一基板，具有多个第一电性接触垫与至少一第二电性接触垫；
至少一半导体组件，设于该基板上且电性连接该些第一电性接触垫；以及
导电胶，形成于该半导体组件上且延伸至该基板的第二电性接触垫上，以令该导电胶与该第二电性接触垫构成屏蔽结构。
2.根据权利要求1所述的半导体封装件，其特征在于，该基板中还具有电性连接该第二电性接触垫的导电孔。
3.根据权利要求2所述的半导体封装件，其特征在于，该导电孔为接地孔。
4.根据权利要求1所述的半导体封装件，其特征在于，该第二电性接触垫为接地垫。
5.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件借由多个导电凸块电性连接该些第一电性接触垫。
6.根据权利要求5所述的半导体封装件，其特征在于，该半导体封装件还包括底胶，其形成于该半导体组件与该基板之间，以包覆该些导电凸块。
7.根据权利要求1所述的半导体封装件，其特征在于，该导电胶沿该半导体组件的侧面延伸至该第二电性接触垫上。
8.根据权利要求1所述的半导体封装件，其特征在于，该基板还具有多个第三电性接触垫，且该半导体封装件还包括至少一电子组件，设于该导电胶上且电性连接该些第三电性接触垫。
9.根据权利要求8所述的半导体封装件，其特征在于，该电子组件为封装体或芯片。
10.根据权利要求8所述的半导体封装件，其特征在于，该半导体封装件还包括封装胶体，形成于该基板上，以包覆该半导体组件、电子组件与该导电胶。
11.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括底胶，形成于该半导体组件与该基板之间，令该导电胶还形成于该底胶上。
12.一种半导体封装件的制法，其包括：
提供一具有多个第一电性接触垫与至少一第二电性接触垫的基板；
设置至少一半导体组件于该基板上，且该半导体组件电性连接该些第一电性接触垫；以及
形成导电胶于该半导体组件上，以覆盖该半导体组件，且该导电胶由该半导体组件延伸至该基板的第二电性接触垫上，以令该导电胶与该第二电性接触垫构成屏蔽结构。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，该基板中还具有电性连接该第二电性接触垫的导电孔。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该导电孔为接地孔。
15.根据权利要求12所述的半导体封装件的制法，其特征在于，该第二电性接触垫为接地垫。
16.根据权利要求12所述的半导体封装件的制法，其特征在于，该半导体组件借由多个导电凸块电性连接该些第一电性接触垫。
17.根据权利要求16所述的半导体封装件的制法，其特征在于，该制法还包括形成底胶于该半导体组件与该基板之间，以包覆该些导电凸块。
18.根据权利要求12所述的半导体封装件的制法，其特征在于，形成该导电胶的方式为点胶工艺、网版涂布工艺、转印工艺或膜贴工艺。
19.根据权利要求12所述的半导体封装件的制法，其特征在于，该基板还具有多个第三电性接触垫，且该制法还包括设置至少一电子组件于该导电胶上，且该电子组件电性连接该些第三电性接触垫。
20.根据权利要求19所述的半导体封装件的制法，其特征在于，该电子组件为封装体或芯片。
21.根据权利要求19所述的半导体封装件的制法，其特征在于，该制法还包括形成封装胶体于该基板上，以包覆该半导体组件、电子组件与该导电胶。
22.根据权利要求12所述的半导体封装件的制法，其特征在于，该制法还包括形成底胶于该半导体组件与该基板之间，使该导电胶还形成于该底胶上。
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