CN104517922B - 层叠式封装结构及其制法 - Google Patents

层叠式封装结构及其制法 Download PDF

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CN104517922B
CN104517922B CN201310478867.3A CN201310478867A CN104517922B CN 104517922 B CN104517922 B CN 104517922B CN 201310478867 A CN201310478867 A CN 201310478867A CN 104517922 B CN104517922 B CN 104517922B
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layer
dielectric layer
metal column
perforate
resistance layer
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CN104517922A (zh
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林邦群
王维宾
李春源
唐绍祖
蔡瀛洲
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Siliconware Precision Industries Co Ltd
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Abstract

一种层叠式封装结构及其制法，该制法包括：提供第一封装件，其包括：介电层，其具有相对的第一表面与第二表面；层叠线路层，其嵌埋于该介电层中，且外露于该第一表面与第二表面；多个金属柱，其设于该介电层的第一表面上，且电性连接该层叠线路层；半导体芯片，其接置于该介电层的第一表面上，且电性连接该层叠线路层；及封装胶体，其形成于该介电层的第一表面上，并包覆该半导体芯片与金属柱，且具有多个对应外露该金属柱的顶端的封装胶体开孔；以及于该封装胶体上接置第二封装件，使该第二封装件电性连接该等金属柱。本发明能有效增进产能与良率。

Description

层叠式封装结构及其制法
技术领域
本发明有关于一种封装结构及其制法，尤指一种层叠式封装结构及其制法。
背景技术
随着电子产品逐渐朝微型化发展，印刷电路板（PCB）表面可供设置半导体封装件的面积越来越小，因此遂发展出一种半导体封装件的立体堆栈技术，其通过于一半导体封装件上叠置另一半导体封装件，而成为一层叠式封装结构（package on package，简称POP），以符合小型表面接合面积与高密度组件设置的要求。
图1所示者，其现有的层叠式封装结构的剖视图。
如图所示，其于底封装件11上形成封装胶体111后，以激光烧灼形成多个贯穿且外露电性连接垫112的封装胶体开孔1110，接着，在该封装胶体开孔1110中的电性连接垫112上接置导电组件113，另一方面，在顶封装件12的底面接置多个焊球121，然后，将该顶封装件12接置于该底封装件11上，使该顶封装件12的焊球121电性连接该底封装件11的导电组件113。
惟，前述现有的层叠式封装结构须使用激光将该封装胶体打穿，即激光钻孔的深度较深，进而拉长制程时间，降低产能；此外，随着电子产品的数入/输出（I/O）数量增加，电性连接垫之间的间距随之缩小，而容易在堆栈封装件时发生焊料桥接（solder bridge）现象，降低整体良率。
因此，如何避免上述现有技术中的种种问题，实已成为目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明的主要目的为提供一种层叠式封装结构及其制法，能有效增进产能与良率。
本发明的层叠式封装结构的制法包括：提供第一封装件，其包括：介电层，其具有相对的第一表面与第二表面；层叠线路层，其嵌埋于该介电层中，且外露于该第一表面与第二表面；多个金属柱，其设于该介电层的第一表面上，且电性连接该层叠线路层；半导体芯片，其接置于该介电层的第一表面上，且电性连接该层叠线路层；及封装胶体，其形成于该介电层的第一表面上，并包覆该半导体芯片与金属柱，且具有多个对应外露该金属柱的顶端的封装胶体开孔；以及于该封装胶体上接置第二封装件，使该第二封装件电性连接该等金属柱。
于本实施例的制法中，该第一封装件的制作步骤包括：于一具有相对的第三表面与第四表面的承载板的第四表面上形成具有第一阻层开孔的第一阻层，形成该承载板的材质为金属板或导电材料；于该第一阻层开孔中形成第一线路；于该第一阻层与第一线路上形成具有第二阻层开孔的第二阻层；于该第二阻层开孔中形成第二线路，该第一线路与第二线路构成该层叠线路层；移除该第一阻层与第二阻层；形成包覆该第一线路与第二线路且外露该第二线路的该介电层；形成贯穿该承载板的承载板开孔，并使剩余该承载板构成该等金属柱；于该介电层的第一表面上接置电性连接该层叠线路层的该半导体芯片；于该介电层的第一表面上形成包覆该半导体芯片与金属柱的该封装胶体；以及形成多个对应外露该金属柱的顶端的该封装胶体开孔。
所述的层叠式封装结构的制法中，该第一封装件的制作步骤包括：于一具有相对的第三表面与第四表面的承载板中形成多个贯穿的承载板通孔，形成该承载板的材质为金属板或导电材料；于各该承载板通孔中形成该金属柱；于该承载板的第四表面上形成具有第一阻层开孔的第一阻层；于该第一阻层开孔中形成第一线路；于该第一阻层与第一线路上形成具有第二阻层开孔的第二阻层；于该第二阻层开孔中形成第二线路，该第一线路与第二线路构成该层叠线路层；移除该第一阻层与第二阻层；形成包覆该第一线路与第二线路且外露该第二线路的该介电层；移除该承载板，并留下该等金属柱；于该介电层的第一表面上接置电性连接该层叠线路层的该半导体芯片；于该介电层的第一表面上形成包覆该半导体芯片与金属柱的该封装胶体；以及形成多个对应外露该金属柱的顶端的该封装胶体开孔。
于本发明的制法中，形成该封装胶体开孔的方式以激光烧灼该封装胶体，且该第二封装件还包括用以对应连接该金属柱的顶端的导电组件。
依前所述的制法，该导电组件为焊球，且于提供该第一封装件之后，还包括对该第一封装件进行切单步骤。
本发明还提供一种层叠式封装结构，包括：第一封装件，其包括：介电层，其具有相对的第一表面与第二表面；层叠线路层，其嵌埋于该介电层中，且外露于该第一表面与第二表面；多个金属柱，其设于该介电层的第一表面上，且电性连接该层叠线路层；半导体芯片，其接置于该介电层的第一表面上，且电性连接该层叠线路层；及封装胶体，其形成于该介电层的第一表面上，并包覆该半导体芯片与金属柱，且具有多个对应外露该金属柱的顶端的封装胶体开孔；以及第二封装件，其接置于该封装胶体上，且电性连接该等金属柱。
于本实施例的层叠式封装结构中，该第二封装件还包括用以对应连接该金属柱的顶端的导电组件，且该导电组件为焊球。
由上可知，本发明通过于第一封装件上形成有多个金属柱，并于接置芯片与包覆封装胶体后，形成外露该金属柱的顶端的封装胶体开孔，由于本发明的封装胶体开孔的深度较浅，故可有效减少制程时间，增进产能。
附图说明
图1所示者为现有的层叠式封装结构的剖视图。
图2A至图2N所示者为本发明的层叠式封装结构及其制法的剖视图。
图3A至图3G所示者为本发明的层叠式封装结构的第一封装件的另一制法的剖视图。
符号说明
11 底封装件
111、26 封装胶体
1110 封装胶体开孔
112 电性连接垫
113、31 导电组件
12 顶封装件
121、27 焊球
20、40 承载板
200 承载板开孔
201、41 金属柱
202 支撑部
20a、40a 第三表面
20b、40b 第四表面
21 第一阻层
210 第一阻层开孔
22a 第一线路
22b 第二线路
22 层叠线路层
23 第二阻层
230 第二阻层开孔
24 介电层
24a 第一表面
24b 第二表面
25 半导体芯片
260 封装胶体开孔
2 第一封装件
3 第二封装件
400 承载板通孔。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「上」、「顶端」及「一」等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
第一实施例
图2A至图2N所示者，为本发明的层叠式封装结构及其制法的剖视图。
如图2A所示，提供一具有相对的第三表面20a与第四表面20b的承载板20，形成该承载板20的材质可为金属板或其它导电材质，于一较佳实施例中，形成该承载板20的材质为铁或冷轧钢卷（Steel-Plate-ColdRolled-Coil，SPCC）。
如图2B所示，于该承载板20的第四表面20b上形成具有第一阻层开孔210的第一阻层21。
如图2C所示，于该第一阻层开孔210中形成第一线路22a。
如图2D所示，于该第一阻层21与第一线路22a上形成具有第二阻层开孔230的第二阻层23。
如图2E所示，于该第二阻层开孔230中形成第二线路22b，该第一线路22a与第二线路22b构成层叠线路层22。
如图2F所示，移除该第一阻层21与第二阻层23。
如图2G所示，形成包覆该第一线路22a与第二线路22b的介电层24。
如图2H所示，移除部分厚度的该介电层24，该介电层24具有相对的第一表面24a与第二表面24b，使该第二线路22b外露于该介电层24的第二表面24b，且移除该介电层24的方式可为研磨。
如图2I所示，形成贯穿该承载板20的承载板开孔200，并使剩余该承载板20构成多个金属柱201及用以维持整体刚性的支撑部202，形成该承载板开孔200的方式可为蚀刻，惟此为所属技术领域具有通常知识者依据本说明书所能了解，故不在此赘述。
如图2J所示，于该介电层24的第一表面24a上接置电性连接该层叠线路层22的半导体芯片25。
如图2K所示，于该介电层24的第一表面24a上形成包覆该半导体芯片25、金属柱201与支撑部202的封装胶体26。
如图2L所示，以激光烧灼方式形成多个对应外露该金属柱201的顶端的封装胶体开孔260，并于该介电层24的第二表面24b接置多个焊球27。
如图2M所示，进行切单步骤，并移除该支撑部202，至此即完成一第一封装件2。
如图2N所示，于该封装胶体26上接置第二封装件3，该第二封装件3包括用以对应连接该金属柱201的顶端的导电组件31，该导电组件31例如为焊球，使该第二封装件3电性连接该等金属柱201。
第二实施例
图3A至图3G所示者，为本发明的层叠式封装结构的第一封装件的另一制法的剖视图。
如图3A所示，于一具有相对的第三表面40a与第四表面40b的承载板40中形成多个贯穿的承载板通孔400，形成该承载板40的材质可为金属板或其它导电材质，于较佳实施例中，形成该承载板40的材质为铁或冷轧钢卷（Steel-Plate-ColdRolled-Coil，SPCC）。
如图3B所示，于各该承载板通孔400中形成金属柱41。
如图3C所示，于该承载板40的第四表面40b上形成具有第一阻层开孔210的第一阻层21，于该第一阻层开孔210中形成第一线路22a。
如图3D所示，于该第一阻层21与第一线路22a上形成具有第二阻层开孔230的第二阻层23，于该第二阻层开孔230中形成第二线路22b，该第一线路22a与第二线路22b构成层叠线路层22。
如图3E所示，移除该第一阻层21与第二阻层23。
如图3F所示，形成包覆该第一线路22a与第二线路22b且外露该第二线路22b的介电层24。
如图3G所示，移除该承载板40，并留下该等金属柱41。后续可再进行如图2J至图2N的步骤，在此将不再赘述。
本发明还提供一种层叠式封装结构，其包括：第一封装件2，其包括：介电层24，其具有相对的第一表面24a与第二表面24b；层叠线路层22，其嵌埋于该介电层24中，且外露于该第一表面24a与第二表面24b；多个金属柱201，其设于该介电层24的第一表面24a上，且电性连接该层叠线路层22；半导体芯片25，其接置于该介电层24的第一表面24a上，且电性连接该层叠线路层22；及封装胶体26，其形成于该介电层24的第一表面24a上，并包覆该半导体芯片25与金属柱201，且具有多个对应外露该金属柱201的顶端的封装胶体开孔260；以及第二封装件3，其接置于该封装胶体26上，且电性连接该等金属柱201。
于本实施例的层叠式封装结构中，该第二封装件3还包括用以对应连接该金属柱201的顶端的导电组件31，该导电组件31为焊球。
要补充说明的是，于该层叠线路层22的外露表面上还可形成有表面处理层（例如镍/金）（未图标）或有机保焊剂（Organic Solderability Preservative，OSP）（未图标），惟此为所属技术领域具有通常知识者依据本说明书所能了解，故不在此赘述。
综上所述，相较于现有技术，本发明通过于移除承载板时留下多个金属柱，并于接置芯片与包覆封装胶体后，形成外露该金属柱的顶端的封装胶体开孔，故可有效减少该封装胶体开孔的深度，进而减少制程时间，增进产能；此外，本发明的电性连接第一封装件与第二封装件所需的导电组件较小，可降低桥接的风险，提高良率，且减少整体堆栈厚度；再者，本发明以层叠线路层取代现有的封装基板，故能薄化整体封装件的厚度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种层叠式封装结构的制法，包括：
提供第一封装件，其包括：
介电层，其具有相对的第一表面与第二表面；
层叠线路层，其嵌埋于该介电层中，该层叠线路层的上下两端面外露于该第一表面与第二表面，且该层叠线路层的上下两端面分别与该第一表面与第二表面齐平；
多个金属柱，其设于该介电层的第一表面上，且电性连接该层叠线路层；
半导体芯片，其接置于该介电层的第一表面上，且电性连接该层叠线路层；及
封装胶体，其形成于该介电层的第一表面上，并包覆该半导体芯片与金属柱，且具有多个对应外露该金属柱的顶端的封装胶体开孔；以及
于该封装胶体上接置第二封装件，使该第二封装件电性连接该多个金属柱。
2.根据权利要求1所述的层叠式封装结构的制法，其特征在于，该第一封装件的制作步骤包括：
于一具有相对的第三表面与第四表面的承载板的第四表面上形成具有第一阻层开孔的第一阻层；
于该第一阻层开孔中形成第一线路；
于该第一阻层与第一线路上形成具有第二阻层开孔的第二阻层；
于该第二阻层开孔中形成第二线路，该第一线路与第二线路构成该层叠线路层；
移除该第一阻层与第二阻层；
形成包覆该第一线路与第二线路且外露该第二线路的该介电层；
形成贯穿该承载板的承载板开孔，并使剩余该承载板构成该多个金属柱；
于该介电层的第一表面上接置电性连接该层叠线路层的该半导体芯片；
于该介电层的第一表面上形成包覆该半导体芯片与金属柱的该封装胶体；以及
形成多个对应外露该金属柱的顶端的该封装胶体开孔。
3.根据权利要求1所述的层叠式封装结构的制法，其特征在于，该第一封装件的制作步骤包括：
于一具有相对的第三表面与第四表面的承载板中形成多个贯穿的承载板通孔；
于各该承载板通孔中形成该金属柱；
于该承载板的第四表面上形成具有第一阻层开孔的第一阻层；
于该第一阻层开孔中形成第一线路；
于该第一阻层与第一线路上形成具有第二阻层开孔的第二阻层；
于该第二阻层开孔中形成第二线路，该第一线路与第二线路构成该层叠线路层；
移除该第一阻层与第二阻层；
形成包覆该第一线路与第二线路且外露该第二线路的该介电层；
移除该承载板，并留下该多个金属柱；
于该介电层的第一表面上接置电性连接该层叠线路层的该半导体芯片；
于该介电层的第一表面上形成包覆该半导体芯片与金属柱的该封装胶体；以及
形成多个对应外露该金属柱的顶端的该封装胶体开孔。
4.根据权利要求2或3所述的层叠式封装结构的制法，其特征在于，形成该承载板的材质为金属板或导电材料。
5.根据权利要求2或3所述的层叠式封装结构的制法，其特征在于，形成该封装胶体开孔的方式是以激光烧灼该封装胶体。
6.根据权利要求1所述的层叠式封装结构的制法，其特征在于，该第二封装件还包括用以对应连接该金属柱的顶端的导电组件。
7.根据权利要求6所述的层叠式封装结构的制法，其特征在于，该导电组件为焊球。
8.根据权利要求1所述的层叠式封装结构的制法，其特征在于，于提供该第一封装件之后，还包括对该第一封装件进行切单步骤。
9.一种层叠式封装结构，包括：
第一封装件，其包括：
介电层，其具有相对的第一表面与第二表面；
层叠线路层，其嵌埋于该介电层中，该层叠线路层的上下两端面外露于该第一表面与第二表面，且该层叠线路层的上下两端面分别与该第一表面与第二表面齐平；
多个金属柱，其设于该介电层的第一表面上，且电性连接该层叠线路层；
半导体芯片，其接置于该介电层的第一表面上，且电性连接该层叠线路层；及
封装胶体，其形成于该介电层的第一表面上，并包覆该半导体芯片与金属柱，且具有多个对应外露该金属柱的顶端的封装胶体开孔；以及
第二封装件，其接置于该封装胶体上，且电性连接该多个金属柱。
10.根据权利要求9所述的层叠式封装结构，其特征在于，该第二封装件还包括用以对应连接该金属柱的顶端的导电组件。
11.根据权利要求10所述的层叠式封装结构，其特征在于，该导电组件为焊球。
CN201310478867.3A 2013-09-27 2013-10-14 层叠式封装结构及其制法 Active CN104517922B (zh)

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