CN104795356A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

Info

Publication number
CN104795356A
CN104795356A CN201410039516.7A CN201410039516A CN104795356A CN 104795356 A CN104795356 A CN 104795356A CN 201410039516 A CN201410039516 A CN 201410039516A CN 104795356 A CN104795356 A CN 104795356A
Authority
CN
China
Prior art keywords
substrate
semiconductor package
making
metal column
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410039516.7A
Other languages
English (en)
Inventor
王隆源
江政嘉
徐逐崎
施嘉凯
黄淑惠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN104795356A publication Critical patent/CN104795356A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体封装件及其制法，该制法包括：接置第一基板于第二基板上，该第一基板的一表面上设有多个第一金属柱，该第二基板具有相对的第三表面与第四表面，该第三表面上设有芯片，该第一基板藉由该第一金属柱连接该第二基板的第三表面；于该第一基板与第二基板间形成封装胶体，令该封装胶体具有面向该第一基板的第一表面及与其相对的第二表面；以及移除该第一基板。本发明能有效避免焊料桥接现象。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种用于堆栈式封装件的半导体封装件及其制法。
背景技术
近年来，由于各种电子产品在尺寸上是日益要求轻、薄及小，因此可节省基板平面面积并可同时兼顾处理性能的堆栈式封装件（package on package，PoP）愈来愈受到重视。
图1所示者为现有的堆栈式封装件，如图所示，该堆栈式封装件为使用焊球11来作为底层封装基板12与顶层封装基板13之间的电性连接用途的互连结构(interconnection)，然而，由于封装件的输入/输出(I/O)的电性连接密度增加，在堆栈封装件的尺寸不变的情况下，焊球11间的间距必须减小，使得焊球11容易于回焊时桥接。
因此，如何避免上述现有技术中的种种问题，实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明的主要目的为提供一种半导体封装件及其制法，能有效避免焊料桥接现象。
本发明的半导体封装件的制法包括：接置第一基板于第二基板上，其中，该第一基板的一表面上设有多个第一金属柱，该第二基板具有其上设有芯片的第三表面与相对于该第三表面的第四表面，供该第一基板藉由该第一金属柱连接该第二基板的第三表面；于该第一基板与第二基板间形成封装胶体，令该封装胶体具有面向该第一基板的第一表面及与其相对的第二表面；以及移除该第一基板。
于前述的制法中，该第三表面上还具有多个电性连接垫，供该第一基板藉由该第一金属柱对应电性连接该电性连接垫而接置于该第二基板上，该第一基板包括依序层叠的介电层、第一金属层与第二金属层，且该第一金属柱设于该第二金属层上。
依上所述的半导体封装件的制法，移除该第一基板包括先移除该介电层与第一金属层，再移除该第二金属层，该第一金属柱的顶端上还设有导电组件，各该电性连接垫上还设有第二金属柱，以对应电性连接该第一金属柱。
于本发明的制法中，该第二金属柱的顶端上还设有导电组件，于移除该第一基板后，还包括于该第一金属柱上形成有机保焊剂，于移除该第一基板后，还包括于该第四表面上形成多个导电组件。
所述的制法中，该第二基板包括依序层叠的第一承载板与黏着层，且该第一金属柱连接至该黏着层，且于移除该第一基板后，还包括移除该第二基板，并于该第二表面上形成第二线路重布层，于移除该第一基板后，还包括于该第一表面上形成第一线路重布层。
又依上所述的半导体封装件的制法，于形成该第一线路重布层后，还包括于该第一线路重布层上接置第二承载板，并移除该第二基板，于该第二表面上形成第二线路重布层，移除该第二承载板，于形成该第二线路重布层后，还包括于该第二线路重布层上形成多个导电组件。
本发明还提供一种半导体封装件，其包括：封装胶体，其具有相对的第一表面与第二表面；芯片，其嵌埋于该封装胶体内，且外露于该封装胶体的第二表面；多个金属柱，其设于该封装胶体中，且贯穿该第一表面与第二表面；第一线路重布层，其形成于该第一表面上，且电性连接该金属柱；以及第二线路重布层，其形成于该第二表面上，且电性连接该芯片与金属柱。
前述的半导体封装件中，还包括形成于该第二线路重布层上的多个导电组件。
由上可知，本发明的半导体封装件及其制法以金属柱来电性连接上下基板，该金属柱所占的空间较现有技术的焊球小，因此可适用于细间距的封装需求，并避免焊料桥接。
附图说明
图1为现有堆栈封装结构的剖视图。
图2A至图2I为本发明的半导体封装件的制法的第一实施例及该半导体封装件的应用例的剖视图，其中，图2B’为图2B的另一实施例，图2C’与图2C”为图2C的不同实施例，图2D’为图2D的另一实施例。
图3A至图3K为本发明的半导体封装件的制法的第二实施例及该半导体封装件的应用例的剖视图。
主要组件符号说明
11            焊球
12            底层封装基板
13            顶层封装基板
20            第一基板
201           介电层
202           第一金属层
203           第二金属层
204           第一金属柱
205、213、24  导电组件
21、30        第二基板
21a、30a      第三表面
21b、30b      第四表面
211           电性连接垫
212           第二金属柱
22            芯片
23            封装胶体
23a           第一表面
23b           第二表面
25            电子组件
2、3          半导体封装件
301           第一承载板
302、33       黏着层
31            第一线路重布层
32            第二承载板
34            第二线路重布层。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
第一实施例
请参阅图2A至图2I，其为本发明的半导体封装件的制法的第一实施例及该半导体封装件的应用例的剖视图。
首先，如图2A所示，提供一第一基板20，其可包括依序层叠的介电层201、第一金属层202与第二金属层203，形成该介电层201的材质可为FR4，该第一金属层202可为铜层，该第二金属层203可为铜箔。
如图2B所示，于该第一基板20的第二金属层203上设有多个第一金属柱204，形成该第一金属柱204的材质可为铜，且该第一金属柱204的顶端上还设有导电组件205，例如焊料；或者，如图2B’所示，不设有该导电组件205。
如图2C所示，提供一第二基板21，其材质例如为BT基板、FR-4基板或陶瓷基板，该第二基板21具有相对的第三表面21a与第四表面21b，该第三表面21a上设有芯片22，该第三表面21a上还具有多个电性连接垫211；或者，如图2C’所示，各该电性连接垫211上还设有第二金属柱212；或者，如图2C”所示，各该第二金属柱212上还设有导电组件213，例如焊料。
如图2D所示，于该第二基板21上接置该第一基板20，该第一基板20藉由该第一金属柱204对应电性连接该电性连接垫211；或者，如图2D’所示，该第一基板20藉由该第一金属柱204对应电性连接该第二金属柱212。
如图2E所示，其为延续自图2D，于该第一基板20与第二基板21间形成封装胶体23，令该封装胶体23具有面向该第一基板20的第一表面23a及与其相对的第二表面23b。
如图2F所示，以例如剥除的方式移除该介电层201与第一金属层202。
如图2G所示，以例如蚀刻的方式移除该第二金属层203，以外露该第一金属柱204，并视需要于该第一金属柱204上形成有机保焊剂（Organic Solderability Preservative，OSP）（未图标）。
如图2H所示，于该第四表面21b上形成多个导电组件24，至此即完成本发明的半导体封装件2。
如图2I所示，于该第一金属柱204上接置另一电子组件25，例如封装结构或其它半导体芯片。
第二实施例
请参阅图3A至图3K，其为本发明的半导体封装件的制法的第二实施例及该半导体封装件的应用例的剖视图。
首先，如图3A所示，提供一第二基板30，该第二基板30包括依序层叠的第一承载板301与黏着层302，该第二基板30具有相对的第三表面30a与第四表面30b，该第三表面30a上设有芯片22，该第一承载板301的材质例如为玻璃或硅，其型态可为晶圆型（wafer form）或板型（pannel form）。
如图3B所示，提供一第一基板20，其可包括依序层叠的介电层201、第一金属层202与第二金属层203，形成该介电层201的材质可为FR4，该第一金属层202可为铜层，该第二金属层203可为铜箔，于该第一基板20的第二金属层203上设有多个第一金属柱204，于该第二基板30上接置该第一基板20，该第一基板20藉由该第一金属柱204连接至该黏着层302。
如图3C所示，于该第一基板20与第二基板30间形成封装胶体23，令该封装胶体23具有面向该第一基板20的第一表面23a及与其相对的第二表面23b。
如图3D所示，以例如剥除的方式移除该介电层201与第一金属层202。
如图3E所示，以例如蚀刻的方式移除该第二金属层203，以外露该第一金属柱204，并视需要于该第一金属柱204上形成有机保焊剂（Organic Solderability Preservative，OSP）（未图标）。
如图3F所示，于该第一表面23a上形成第一线路重布层31。
如图3G所示，移除该第二基板30。
如图3H所示，视需要藉由黏着层33于该第一线路重布层31上接置第二承载板32。
如图3I所示，于该第二表面23b上形成第二线路重布层34。
如图3J所示，于该第二线路重布层34上形成多个导电组件24，至此即完成本发明的半导体封装件3。
如图3K所示，于该第一金属柱204上接置另一电子组件25，例如封装结构或其它半导体芯片。
本发明还提供一种半导体封装件，如图3J所示，其包括：封装胶体23，其具有相对的第一表面23a与第二表面23b；芯片22，其嵌埋于该封装胶体23内，且外露于该封装胶体23的第二表面23b；多个第一金属柱204，其设于该封装胶体23中，且贯穿该第一表面23a与第二表面23b；第一线路重布层31，其形成于该第一表面23a上，且电性连接该第一金属柱204；以及第二线路重布层34，其形成于该第二表面23b上，且电性连接该芯片22与第一金属柱204。
前述的半导体封装件中，还包括形成于该第二线路重布层34上的多个导电组件24。
综上所述，相较于现有技术，本发明的半导体封装件及其制法以金属柱来电性连接上下基板，并于形成封装胶体后移除上基板，由于该金属柱所占的空间较焊球小，因此可适用于细间距（fine pitch）的封装需求，并可避免焊料桥接，进而提高产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种半导体封装件的制法，其包括：
接置第一基板于第二基板上，其中，该第一基板的一表面上设有多个第一金属柱，该第二基板具有其上设有芯片的第三表面与相对于该第三表面的第四表面，供该第一基板藉由该第一金属柱连接该第二基板的第三表面；
于该第一基板与第二基板间形成封装胶体，令该封装胶体具有面向该第一基板的第一表面及与其相对的第二表面；以及
移除该第一基板。
2.根据权利要求1所述的半导体封装件的制法，其特征在于，该第三表面上还具有多个电性连接垫，供该第一基板藉由该第一金属柱对应电性连接该电性连接垫而接置于该第二基板上。
3.根据权利要求2所述的半导体封装件的制法，其特征在于，各该电性连接垫上还设有第二金属柱，以对应电性连接该第一金属柱。
4.根据权利要求3所述的半导体封装件的制法，其特征在于，该第二金属柱的顶端上还设有导电组件。
5.根据权利要求1所述的半导体封装件的制法，其特征在于，该第一金属柱的顶端上还设有导电组件。
6.根据权利要求1所述的半导体封装件的制法，其特征在于，该第一基板包括依序层叠的介电层、第一金属层与第二金属层，且该第一金属柱设于该第二金属层上。
7.根据权利要求6所述的半导体封装件的制法，其特征在于，移除该第一基板包括先移除该介电层与第一金属层，再移除该第二金属层。
8.根据权利要求1所述的半导体封装件的制法，其特征在于，于移除该第一基板后，还包括于该第一金属柱上形成有机保焊剂。
9.根据权利要求1所述的半导体封装件的制法，其特征在于，于移除该第一基板后，还包括于该第四表面上形成多个导电组件。
10.根据权利要求1所述的半导体封装件的制法，其特征在于，该第二基板包括依序层叠的第一承载板与黏着层，且该第一金属柱连接至该黏着层，且于移除该第一基板后，还包括移除该第二基板，并于该第二表面上形成第二线路重布层。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，于形成该第二线路重布层后，还包括于该第二线路重布层上形成多个导电组件。
12.根据权利要求1所述的半导体封装件的制法，其特征在于，于移除该第一基板后，还包括于该第一表面上形成第一线路重布层。
13.根据权利要求12所述的半导体封装件的制法，其特征在于，于形成该第一线路重布层后，还包括于该第一线路重布层上接置第二承载板，并移除该第二基板，于该第二表面上形成第二线路重布层，移除该第二承载板。
14.一种半导体封装件，包括：
封装胶体，其具有相对的第一表面与第二表面；
芯片，其嵌埋于该封装胶体内，且外露于该封装胶体的第二表面；
多个金属柱，其设于该封装胶体中，且贯穿该第一表面与第二表面；
第一线路重布层，其形成于该第一表面上，且电性连接该金属柱；以及
第二线路重布层，其形成于该第二表面上，且电性连接该芯片与金属柱。
15.根据权利要求14所述的半导体封装件，其特征在于，该封装件还包括形成于该第二线路重布层上的多个导电组件。
CN201410039516.7A 2014-01-16 2014-01-27 半导体封装件及其制法 Pending CN104795356A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103101561 2014-01-16
TW103101561A TWI550791B (zh) 2014-01-16 2014-01-16 半導體封裝件及其製法

Publications (1)

Publication Number Publication Date
CN104795356A true CN104795356A (zh) 2015-07-22

Family

ID=53521992

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410039516.7A Pending CN104795356A (zh) 2014-01-16 2014-01-27 半导体封装件及其制法

Country Status (3)

Country Link
US (2) US9343421B2 (zh)
CN (1) CN104795356A (zh)
TW (1) TWI550791B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105590904A (zh) * 2015-11-05 2016-05-18 华天科技（西安）有限公司 一种指纹识别多芯片封装结构及其制备方法
CN106601630A (zh) * 2015-10-19 2017-04-26 碁鼎科技秦皇岛有限公司 芯片封装方法及芯片封装结构
US11854877B2 (en) 2016-10-13 2023-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614844B (zh) 2017-03-31 2018-02-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法
US10825773B2 (en) * 2018-09-27 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same
US11373989B1 (en) * 2020-08-28 2022-06-28 Xilinx, Inc. Package integration for laterally mounted IC dies with dissimilar solder interconnects

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239336A1 (en) * 2008-03-21 2009-09-24 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US20100140771A1 (en) * 2008-12-05 2010-06-10 Stats Chippac, Ltd. Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
US20120104607A1 (en) * 2010-10-29 2012-05-03 Cheng-Yi Weng Stacked semiconductor packages and related methods
CN102637678A (zh) * 2011-02-15 2012-08-15 欣兴电子股份有限公司 封装堆栈装置及其制法
US20130105991A1 (en) * 2011-11-02 2013-05-02 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3d and package-on-package applications, and method of manufacture
CN103165555A (zh) * 2011-12-08 2013-06-19 欣兴电子股份有限公司 层叠封装的封装结构及其制法
CN103515362A (zh) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 堆叠式封装器件和封装半导体管芯的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410825B2 (en) * 2005-09-15 2008-08-12 Eastman Kodak Company Metal and electronically conductive polymer transfer
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7741148B1 (en) * 2008-12-10 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support
US20100327465A1 (en) * 2009-06-25 2010-12-30 Advanced Semiconductor Engineering, Inc. Package process and package structure
US20110014746A1 (en) * 2009-07-17 2011-01-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer Singulaton
TWI497668B (zh) * 2011-07-27 2015-08-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9559039B2 (en) * 2012-09-17 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
KR101419601B1 (ko) * 2012-11-20 2014-07-16 앰코 테크놀로지 코리아 주식회사 Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
CN106229270A (zh) * 2013-03-29 2016-12-14 日月光半导体制造股份有限公司 堆迭式封装及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239336A1 (en) * 2008-03-21 2009-09-24 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US20100140771A1 (en) * 2008-12-05 2010-06-10 Stats Chippac, Ltd. Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
US20120104607A1 (en) * 2010-10-29 2012-05-03 Cheng-Yi Weng Stacked semiconductor packages and related methods
CN102637678A (zh) * 2011-02-15 2012-08-15 欣兴电子股份有限公司 封装堆栈装置及其制法
US20130105991A1 (en) * 2011-11-02 2013-05-02 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3d and package-on-package applications, and method of manufacture
CN103165555A (zh) * 2011-12-08 2013-06-19 欣兴电子股份有限公司 层叠封装的封装结构及其制法
CN103515362A (zh) * 2012-06-25 2014-01-15 台湾积体电路制造股份有限公司 堆叠式封装器件和封装半导体管芯的方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601630A (zh) * 2015-10-19 2017-04-26 碁鼎科技秦皇岛有限公司 芯片封装方法及芯片封装结构
CN105590904A (zh) * 2015-11-05 2016-05-18 华天科技（西安）有限公司 一种指纹识别多芯片封装结构及其制备方法
US11854877B2 (en) 2016-10-13 2023-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
US9343421B2 (en) 2016-05-17
US20150200169A1 (en) 2015-07-16
TW201530714A (zh) 2015-08-01
TWI550791B (zh) 2016-09-21
US20160233205A1 (en) 2016-08-11

Similar Documents

Publication Publication Date Title
US12009289B2 (en) Semiconductor package and manufacturing method thereof
US11791256B2 (en) Package substrate and method of fabricating the same
US8502370B2 (en) Stack package structure and fabrication method thereof
KR100833589B1 (ko) 스택 패키지
CN105097750A (zh) 封装结构及其制法
CN104795356A (zh) 半导体封装件及其制法
KR101706444B1 (ko) 가변 칩 간격을 갖는 램프-스택 칩 패키지
KR101394203B1 (ko) 적층형 반도체 패키지 및 그 제조 방법
CN105097759A (zh) 封装堆栈结构及其制法暨无核心层式封装基板及其制法
CN104517922B (zh) 层叠式封装结构及其制法
US20150255360A1 (en) Package on package structure and fabrication method thereof
CN102646663B (zh) 半导体封装件
US20180269142A1 (en) Substrate construction and electronic package including the same
KR101207882B1 (ko) 패키지 모듈
EP2899752B1 (en) Chip package structure
CN104681499B (zh) 封装堆栈结构及其制法
CN103137581B (zh) 具有导电凸块的半导体装置、封装结构及制法
CN101211792A (zh) 半导体封装件及其制法与堆叠结构
CN104425418A (zh) 半导体封装件及其制法
US20210050326A1 (en) Semiconductor package
CN101465341B (zh) 堆叠式芯片封装结构
CN105575942A (zh) 中介基板及其制法
CN103972203A (zh) 嵌埋有电子组件的线路板结构及其制法
CN108074895A (zh) 堆叠封装结构及其制造方法
CN104867901A (zh) 基板结构与半导体封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150722

RJ01 Rejection of invention patent application after publication