TWI614844B - 封裝堆疊結構及其製法 - Google Patents

封裝堆疊結構及其製法 Download PDF

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Publication number
TWI614844B
TWI614844B TW106111065A TW106111065A TWI614844B TW I614844 B TWI614844 B TW I614844B TW 106111065 A TW106111065 A TW 106111065A TW 106111065 A TW106111065 A TW 106111065A TW I614844 B TWI614844 B TW I614844B
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Taiwan
Prior art keywords
insulating layer
layer
component
stack structure
item
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TW106111065A
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English (en)
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TW201838100A (zh
Inventor
陳漢宏
許元鴻
林長甫
林榮政
黃富堂
Original Assignee
矽品精密工業股份有限公司
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Priority to TW106111065A priority Critical patent/TWI614844B/zh
Priority to CN201710244156.8A priority patent/CN108666255A/zh
Priority to US15/865,999 priority patent/US20180288886A1/en
Application granted granted Critical
Publication of TWI614844B publication Critical patent/TWI614844B/zh
Publication of TW201838100A publication Critical patent/TW201838100A/zh
Priority to US16/856,259 priority patent/US11516925B2/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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Abstract

一種封裝堆疊結構及其製法，係於設有電子元件之板體上堆疊無核心層(coreless)之線路部，以降低該封裝堆疊結構的整體厚度。

Description

封裝堆疊結構及其製法
本發明係有關一種封裝結構，尤指一種封裝堆疊結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，業界遂發展出疊加複數封裝結構以形成封裝堆疊結構(Package on Package，簡稱POP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1A及1B圖係為習知封裝堆疊結構1,1’之不同態樣之剖面示意圖。
如第1A圖所示，該封裝堆疊結構1係包含第一封裝基板11及第二封裝基板12，該第一封裝基板11具有複數線路層110，且該第二封裝基板12具有核心層120與複數線路層121，俾供第一半導體元件10以覆晶方式設於該第 一封裝基板11上，再藉由底膠14充填於該第一半導體元件10與第一封裝基板11之間，且第二半導體元件15以打線方式結合於該第二封裝基板12上，再藉由封裝膠體16包覆該第二半導體元件15，並以複數銲球13疊設且電性連接該第一封裝基板11與該第二封裝基板12。
如第1B圖所示，該封裝堆疊結構1’係包含第一封裝基板11及第二封裝基板12，該第一封裝基板11具有複數線路層110，且該第二封裝基板12具有核心層120與複數線路層121，俾供第一半導體元件10以覆晶方式設於該第一封裝基板11上，再藉由底膠14充填於該第一半導體元件10與第一封裝基板11之間，之後以複數銲球13疊設且電性連接該第一封裝基板11與該第二封裝基板12，再藉由封裝膠體16’包覆該些銲球13與第一半導體元件10，後續將第二半導體元件15’以覆晶方式設於該第二封裝基板12上。
惟，習知封裝堆疊結構1,1’中，其第二封裝基板12皆具有核心層120，導致該封裝堆疊結構1,1’不符合薄化之需求。
因此，如何克服習知技術中之問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種封裝堆疊結構，係包括：第一組件，係包含有絕緣層、線路部與複數導電元件，其中，該絕緣層具有相對之第一表面與第二 表面，該線路部係結合該絕緣層，該導電元件係立設於該絕緣層之第一表面上並接觸該線路部，且該第一組件不具有核心層；板體，係透過該複數導電元件而堆疊於該絕緣層之第一表面上；以及第一電子元件，係設於該板體上。
前述之封裝堆疊結構中，復包括結合於該絕緣層之第二表面上的支撐部。例如，該支撐部係包含至少一未圖案化之金屬層，並以該金屬層結合該絕緣層之第二表面；或者，該支撐部係包含複數金屬層與複數隔離層，並以該金屬層結合該絕緣層之第二表面。
本發明亦提供一種封裝堆疊結構之製法，係包括：提供一包含絕緣層、線路部、複數導電元件與支撐部之第一組件，該絕緣層係具有相對之第一表面與第二表面，且該線路部係結合該絕緣層，該導電元件立設於該絕緣層之第一表面上並接觸該線路部，且該絕緣層藉其第二表面結合該支撐部；將該第一組件接置於第二組件上，其中該第二組件包含有一板體及設於該板體上之第一電子元件，以令該絕緣層、線路部與支撐部透過該些導電元件堆疊於該板體上；以及於該第一組件接置至第二組件後，移除該支撐部。
前述之製法中，該支撐部係包含至少一金屬層，並以該金屬層結合該絕緣層之第二表面。
前述之製法中，該支撐部係包含複數金屬層與複數隔離層，並以該金屬層結合該絕緣層之第二表面。
前述之封裝堆疊結構及其製法中，該線路部係包含至 少一線路層。
前述之封裝堆疊結構及其製法中，該線路部之外表面係低於該絕緣層之第二表面。
前述之封裝堆疊結構及其製法中，該導電元件係為銲球、銅核心球或金屬件。
前述之封裝堆疊結構及其製法中，復包括將第二電子元件設於該絕緣層之第二表面上。
前述之封裝堆疊結構及其製法中，復包括將封裝材形成於該絕緣層之第一表面與該板體之間。
前述之封裝堆疊結構及其製法中，該線路部係嵌埋於該絕緣層中。
由上可知，本發明封裝堆疊結構及其製法，主要藉由先將該第一組件堆疊於該板體上，再移除該支撐部，以提供穩固該第一組件之效果，且可降低該封裝堆疊結構的整體厚度。
1,1’,2,3‧‧‧封裝堆疊結構
10‧‧‧第一半導體元件
11‧‧‧第一封裝基板
110,121‧‧‧線路層
12‧‧‧第二封裝基板
120‧‧‧核心層
13‧‧‧銲球
14‧‧‧底膠
15,15’‧‧‧第二半導體元件
16,16’‧‧‧封裝膠體
2a,3a‧‧‧第一組件
2b‧‧‧第二組件
20‧‧‧絕緣層
20a‧‧‧第一表面
20b‧‧‧第二表面
21,31‧‧‧線路部
210‧‧‧導電盲孔
211‧‧‧第一線路層
212‧‧‧第二線路層
22‧‧‧導電元件
23,33,43‧‧‧支撐部
231‧‧‧第一金屬層
232‧‧‧第二金屬層
233‧‧‧第三金屬層
24‧‧‧板體
240‧‧‧電性接觸墊
241‧‧‧銲錫材
25‧‧‧第一電子元件
250,270‧‧‧導電凸塊
26‧‧‧封裝材
27‧‧‧第二電子元件
28‧‧‧銲球
300‧‧‧開孔
330‧‧‧第一隔離層
331‧‧‧第一金屬層
332‧‧‧第二金屬層
333‧‧‧第二隔離層
h‧‧‧高度
S‧‧‧切割路徑
t,d,r,L‧‧‧厚度
第1A及1B圖係為習知封裝堆疊結構之不同態樣之剖視示意圖；第2A至2D圖係為本發明之封裝堆疊結構之第一實施例之製法的剖視示意圖；第3A至3D圖係為本發明之封裝堆疊結構之第二實施例之製法的局部剖視示意圖；以及第4圖係為本發明之封裝堆疊結構之第一組件之支撐部之另一實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之封裝堆疊結構2之第一實施例之製法的剖視示意圖。
如第2A圖所示，提供一第一組件2a，其包含一絕緣層20、一線路部21、複數導電元件22與一支撐部23。
所述之絕緣層20係具有相對之第一表面20a與第二表面20b，並以該第二表面20b結合該支撐部23。
於本實施例中，形成該絕緣層20之材質可為介電材，如預浸材(prepreg)、封裝材(molding compound)或ABF(Ajinomoto Build-up Film)等，且該絕緣層20之厚度t 係例如為15微米。
所述之線路部21係結合該絕緣層20，例如嵌埋於該絕緣層20中。於本實施例中，該線路部21係包含一埋設於該第一表面20a之第一線路層211、一埋設於該第二表面20b之第二線路層212、及複數電性連接該第一與第二線路層211,212之導電盲孔210。應可理解地，該第一與第二線路層211,212亦可設於該絕緣層20之第一表面20a與第二表面20b之上。
再者，形成該第一線路層211、該第二線路層212及該些導電盲孔210之材質係為銅材、鎳/金材或其它合適導電材。
所述之導電元件22立設於該絕緣層20之第一表面20a上並接觸該線路部21之第一線路層211。
於本實施例中，該導電元件22係為銲球(solder ball)、銅核心球、或如銅材或金材之金屬件(如柱狀、塊狀或針狀)等。
再者，該導電元件22之形狀並無限制，如錐柱體(即體積由底端朝頂端漸縮)或其它形狀。
又，該導電元件22突出該第一表面20a之高度h係例如為165微米。
所述之支撐部23係可為已切單的板塊或為整版面結構(即包含多個單元)，例如條形(strip form)或晶圓型(wafer form)。
於本實施例中，該支撐部23包含至少一未圖案化之金 屬層，例如係由第一金屬層231、第二金屬層232與第三金屬層233所構成，並以該第一金屬層231結合該絕緣層20之第二表面20b與該第二線路層212。
再者，該第一與第三金屬層231,233係為銅層，且該第二金屬層232係為鎳層。
又，該第一與第二金屬層231,232之厚度d,r係例如為3微米，且該第三金屬層233之厚度L係例如為70微米。
如第2B圖所示，將該第一組件2a接置於第二組件2b上，其中，該第二組件2b包含有板體24以及設於該板體24上之第一電子元件25，以於該絕緣層20之第一表面20a上堆疊該板體24(或於該板體24上堆疊該第一組件2a)。接著，將封裝材26形成於該絕緣層20之第一表面20a與該板體24之間，以包覆該第一電子元件25與該導電元件22。
所述之板體24係為具有核心層或無核心層(coreless)之線路結構，如封裝基板(substrate)，其具有如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)之線路配置。應可理解地，該板體亦可為其它承載晶片之板材，如導線架(leadframe)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等，並不限於上述。
於本實施例中，該導電元件22係熔融接合至該板體24之電性接觸墊240上之銲錫材241。
所述之第一電子元件25係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該 被動元件係例如電阻、電容及電感。
於本實施例中，該第一電子元件25係藉由複數如銲錫材料之導電凸塊250以覆晶方式設於該板體24上並電性連接該板體24；或者，該第一電子元件25可藉由複數銲線(圖略)以打線方式電性連接該板體24；亦或，該第一電子元件25可直接接觸該板體24之線路。然而，有關該第一電子元件25電性連接該板體24之方式不限於上述。
所述之封裝材26之形成材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或模塑料(molding compound)等，但不限於上述。
如第2C圖所示，移除該支撐部23，使該第二線路層212外露於該絕緣層20之第二表面20b。
於本實施例中，先以蝕刻製程依序移除第三金屬層233與第二金屬層232，以得到一平整表面，再微蝕刻第一金屬層231並延伸至該絕緣層20之第二表面20b下方3至5微米(即移除部分該第二線路層212)，使該線路部21之第二線路層212之外表面低於該絕緣層20之第二表面20b。
應可理解地，若先移除該支撐部23，再將埋設有線路部21之絕緣層20堆疊於該板體24上，則於移除該支撐部23之過程中會因剛性不足而無法穩固該第一組件2a，致使該第一組件2a會產生位移，導致設備無法取放(pick & place)該絕緣層20。因此，本發明之製法係先將該第一組件2a堆疊於該板體24上，再移除該支撐部23，以藉由該板體24(及該封裝材26)提供穩固該第一組件2a之效果， 故於於薄化過程中(即移除該支撐部23)，能避免因剛性不足而無法取放的情況發生。
如第2D圖所示，沿如第2C圖所示之切割路徑S進行切單製程，之後將第二電子元件27設於該絕緣層20之第二表面20b上，且於該板體24下方植設如銲球28之導電件。
於本實施例中，該第二電子元件27係為封裝件、主動元件、被動元件或其三者組合等，其中，該封裝件係例如晶片級封裝(Chip Scale Package，簡稱CSP)，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第二電子元件27係藉由複數如銲錫材料之導電凸塊270堆疊於該第二表面20b上並電性連接該第二線路層212；或者，該第二電子元件27可藉由複數銲線(圖略)以打線方式電性連接該第二線路層212；亦或，該第二電子元件27可直接接觸該第二線路層212。然而，有關該第二電子元件27電性連接該第二線路層212之方式不限於上述。
本發明之製法係藉由先將該第一組件2a堆疊於第二組件2b之板體24上，再移除部分該第一組件2a(即移除該支撐部23)，故相較於習知技術，本發明之製法因該板體24上堆疊無核心層(coreless)之線路部21而能降低該封裝堆疊結構2的整體厚度。
第3A至3D圖係為本發明之封裝堆疊結構3之第二實施例之製法的剖視示意圖。本實施例與第一實施例之差異 在於第一組件之結構不同，其它製程大致相同，故以下僅詳細說明相異處，而不再贅述相同處。
如第3A圖所示，係如第2B圖所示之製程，將一包含絕緣層20、線路部31、複數導電元件22與一支撐部33之第一組件3a堆疊至第二組件2b之板體24上，且將封裝材26形成於該絕緣層20之第一表面20a與該板體24之間。
所述之線路部31係為單一線路層，其埋設於該絕緣層20之第一表面20a。
所述之導電元件22立設於該絕緣層20之第一表面20a上並接觸該線路部31且熔融接合至該板體24上。
所述之支撐部33係包含第一與第二金屬層331,332及第一與第二隔離層330,333，並以該第一金屬層331結合該絕緣層20之第二表面20b。
於本實施例中，形成該絕緣層20與該第二隔離層333之材質係為ABF(Ajinomoto Build-up Film)，且形成該第一與第二金屬層331,332之材質係為銅層，而該第一隔離層330係作為核心層。應可理解地，該第一組件3a係為相對核心層對稱佈設之構造，該絕緣層20與該第二隔離層333之材質可相同或不相同，且該第一組件3a之構造不限於上述。
如第3B圖所示，以研磨方式移除該支撐部33，以外露出該絕緣層20之第二表面20b。
如第3C圖所示，以例如雷射鑽孔方式，形成複數開孔300於該絕緣層20之第二表面20b上，使該線路部31 之部分表面外露於該絕緣層20之第二表面20b。
如第3D圖所示，於該板體24下方植設銲球28，並進行切單製程，且將第二電子元件27設於該絕緣層20之第二表面20b上，並以形成於該些開孔300中之導電凸塊270電性連接該線路部31。
本發明之製法係藉由先將該第一組件3a堆疊於該板體24上，再移除部分該第一組件3a(即移除該支撐部33)，故相較於習知技術，本發明之製法不僅能提供穩固該第一組件3a之效果，以避免於薄化過程中(即移除該支撐部33)因剛性不足而無法取放的情況發生，且因該板體24上堆疊無核心層之線路部31而能降低該封裝堆疊結構3的整體厚度。
再者，如第4圖所示，該第一組件之支撐部43亦可為單一金屬層，如銅、鐵或不鏽鋼，並於製程中以蝕刻或研磨移除。
本發明復提供一種封裝堆疊結構2,3，其包括：一絕緣層20、一線路部21,31、複數導電元件22、一板體24以及至少一第一電子元件25。
所述之絕緣層20係具有相對之第一表面20a與第二表面20b。
所述之線路部21,31係結合該絕緣層20，例如，該線路部21,31嵌埋於該絕緣層20中。
所述之導電元件22係立設於該絕緣層20之第一表面20a上並接觸該線路部21,31。
所述之板體24係接置於該些導電元件22上以堆疊於該絕緣層20之第一表面20a上。
所述之第一電子元件25係設於該板體24上。
於一實施例中，該線路部21,31係包含至少一線路層。
於一實施例中，該線路部31之外表面係低於該絕緣層20之第二表面20b。
於一實施例中，該導電元件22係為銲球、銅核心球或金屬件。
於一實施例中，該封裝堆疊結構2,3復包括第二電子元件27，係設於該絕緣層20之第二表面20b上。
於一實施例中，該封裝堆疊結構2,3復包括封裝材26，係形成於該絕緣層20之第一表面20a與該板體24之間。
於一實施例中，該封裝堆疊結構2,3復包括結合於該絕緣層20之第二表面20b上的支撐部23,33,43。例如，該支撐部23,43係包含至少一金屬層(例如第一至第三金屬層231,232,233)，並以該金屬層結合該絕緣層20之第二表面20b；或者，該支撐部33係包含複數金屬層(例如第一及第二金屬層331,332)與複數隔離層(例如第一及第二隔離層330,333)，並以該金屬層結合該絕緣層20之第二表面20b。
綜上所述，本發明封裝堆疊結構及其製法，係藉由先將該第一組件堆疊於該第二組件之板體上，再移除該支撐部，以提供穩固該第一組件之效果，且能降低該封裝堆疊 結構的整體厚度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝堆疊結構
20‧‧‧絕緣層
20a‧‧‧第一表面
20b‧‧‧第二表面
21‧‧‧線路部
212‧‧‧第二線路層
22‧‧‧導電元件
24‧‧‧板體
25‧‧‧第一電子元件
26‧‧‧封裝材
27‧‧‧第二電子元件
270‧‧‧導電凸塊
28‧‧‧銲球

Claims (16)

  1. 一種封裝堆疊結構，係包括：第一組件，係包含有絕緣層、線路部與複數導電元件，其中，該絕緣層具有相對之第一表面與第二表面，該線路部係結合該絕緣層，該導電元件係立設於該絕緣層之第一表面上並接觸該線路部，且該第一組件不具有核心層；板體，係透過該複數導電元件而堆疊於該絕緣層之第一表面上；第一電子元件，係設於該板體上；以及支撐部，係結合於該絕緣層之第二表面上，且該支撐部包含至少一未圖案化之金屬層，其中，該支撐部更包含隔離層，並以該金屬層結合該絕緣層之第二表面。
  2. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該線路部係包含至少一線路層。
  3. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該線路部之外表面係低於該絕緣層之第二表面。
  4. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該導電元件係為銲球、銅核心球或金屬件。
  5. 如申請專利範圍第1項所述之封裝堆疊結構，復包括形成於該絕緣層之第一表面與該板體之間之封裝材。
  6. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該線路部係嵌埋於該絕緣層中。
  7. 一種封裝堆疊結構之製法，係包括： 提供一包含絕緣層、線路部、支撐部與複數導電元件之第一組件，其中，該絕緣層係具有相對之第一表面與第二表面，該線路部係結合該絕緣層，該導電元件係立設於該絕緣層之第一表面上並接觸該線路部，且該絕緣層以其第二表面結合該支撐部；將該第一組件接置於第二組件上，其中，該第二組件包含有一板體及設於該板體上之第一電子元件，以令該絕緣層、線路部與支撐部透過該複數導電元件堆疊於該板體上；以及於該第一組件接置至該第二組件後，移除該支撐部。
  8. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，該支撐部係包含至少一金屬層，並以該金屬層結合該絕緣層之第二表面。
  9. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，該支撐部係包含複數金屬層與複數隔離層，並以該金屬層結合該絕緣層之第二表面。
  10. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，該線路部係包含至少一線路層。
  11. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，於移除該支撐部後，令該線路部之外表面外露出該絕緣層之第二表面。
  12. 如申請專利範圍第11項所述之封裝堆疊結構之製法，其中，該線路部之外表面係低於該絕緣層之第二表面。
  13. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，該導電元件係為銲球、銅核心球或金屬件。
  14. 如申請專利範圍第7項所述之封裝堆疊結構之製法，復包括於該絕緣層之第二表面上接置第二電子元件。
  15. 如申請專利範圍第7項所述之封裝堆疊結構之製法，復包括於該絕緣層之第一表面與該板體之間形成封裝材。
  16. 如申請專利範圍第7項所述之封裝堆疊結構之製法，其中，該線路部係嵌埋於該絕緣層中。
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