CN103201834B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN103201834B
CN103201834B CN201280003499.0A CN201280003499A CN103201834B CN 103201834 B CN103201834 B CN 103201834B CN 201280003499 A CN201280003499 A CN 201280003499A CN 103201834 B CN103201834 B CN 103201834B
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Prior art keywords
nickel plating
porous nickel
lead frame
solder layer
power semiconductor
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CN103201834A (zh
Inventor
生田敬子
金连姬
广濑贵之
小岛俊之
塚原法人
反田耕一
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H01L23/495—Lead-frames or other flat leads
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/12—Electroplating: Baths therefor from solutions of nickel or cobalt
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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Abstract

提供一种能抑制热阻的增加，并能减小施加到焊料层的热阻的半导体装置。其配置结构具有：半导体元件（5）；焊料层（4），该焊料层（4）配置在半导体元件的至少一个面上；以及引线框（2），该引线框（2）以夹着多孔镀镍部（1）的方式配置在该焊料层上。与直接接合半导体元件与引线框的情况相比，能将焊料接合部的热阻的增加量抑制为仅与多孔镀镍部分相对应的量，能降低施加到焊料层的热阻。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
已知有将功率半导体元件直接与绝缘体上的引线框相接合的功率半导体装置。
图11(a)是示意性地示出以往的具有上述结构的功率半导体装置的功率半导体元件与引线框的接合部的结构的剖视图。
引线框304的一侧的面固定在绝缘体305上，该绝缘体305配置成其下表面与散热板306上方相接触。引线框304的另一侧的面经由焊料层302而与功率半导体元件301相接合。
如上所述，以往将焊料302用于功率半导体元件301与引线框304的接合。然而，由于引线框304的线膨胀系数与功率半导体元件301的线膨胀系数差异较大，因而，驱动功率半导体装置时的动力循环会向焊料接合部的焊料层302反复施加较大的热应力，最终会发生焊料裂缝，从而导致接合不良的问题。
另一方面，在功率半导体装置中，为了减小由构件间的线膨胀系数之差所引起的热应力、热翘曲，提出有以下技术方案，即，在线膨胀系数之差较大的构件间设置导热性多孔金属板，利用焊料对导热性多孔金属板与上述各构件之间进行接合(例如，参照专利文献1)。
本申请的发明者认为：在图11(a)所示的以往结构的功率半导体装置的焊料接合部中，为了降低施加到焊料层302的热应力，可以应用专利文献1所提出的结构。
图11(b)是示意性地示出在图11(a)所示的以往的功率半导体装置中设置导热性多孔金属板而构成的结构中的功率半导体装置与引线框的接合部的结构的剖视图。
线膨胀系数之差较大的功率半导体元件301与引线框304与由两个焊接层302a及302b夹住的导热性的多孔金属板303相接合。
多孔金属板303由铜或铝等导热率及线膨胀系数较大的导热性金属构成。
该多孔金属板303作为应力缓冲板来减小施加到焊料层302a及302b上的应力，从而能够抑制焊料裂缝的发生。
现有技术文献
专利文献
专利文献1：日本国专利特开2002—237556号公报
发明内容
然而，在线膨胀系数之差较大的功率半导体元件与引线框之间设置导热性多孔金属板的结构中，尽管能降低热应力，但是却会导致功率半导体元件与引线框间的接合部的热阻增大。
即，与图11(a)所示的仅简单地以一层焊料层302来接合功率半导体元件301与引线框304的以往结构相比，在图11(b)所示的设置有多孔金属板303的结构中，由于追加了多孔金属板303和焊料层302b，因此，导致接合部的热阻增大。
本发明考虑了上述课题，其目的在于提供一种能够抑制接合部的热阻的增大，并能减小施加到焊料层的热应力，抑制焊料裂缝的发生的半导体装置及其制造方法。
解决技术问题所采用的技术方案
为了解决上述课题，本发明1是一种半导体装置，包括：
半导体元件；
焊料层，该焊料层配置在所述半导体元件的至少一个面上；以及
引线框，该引线框以夹着多孔镀镍部的方式配置在所述焊料层上。
此外，本发明2是本发明1的半导体装置，
所述多孔镀镍部的厚度是10～100μm，孔隙率是20～60％。
本发明3是本发明1或2的半导体装置，
将所述多孔镀镍部施加到所述引线框上。
本发明4是本发明1的半导体装置，
所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
本发明5是本发明1的半导体装置，包括：
另一焊料层，该另一焊料层配置在所述半导体元件的配置有所述焊料层的一侧面的相反侧的面上；以及
另一引线框，该另一引线框以夹着另一多孔镀镍部的方式配置在所述另一焊料层上。
本发明6是本发明1的半导体装置，
所述多孔镀镍部具有多个空孔，
位于所述多孔镀镍部的与所述焊料层相接合的面上的所述空孔中，埋入有导热率高于镍的粒子。
本发明7是本发明6的半导体装置，
埋入有所述粒子的所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
本发明8是本发明6或7的半导体装置，
埋入所述空孔的所述粒子是炭材料的粒子。
本发明9是本发明6的半导体装置，
所述多孔镀镍部的厚度是10～200μm，孔隙率是20～60％。
本发明10是本发明6的半导体装置，
埋入所述空孔的粒子的直径是4～50nm。
本发明11是本发明6的半导体装置，包括：
另一焊料层，该另一焊料层配置在所述半导体元件的配置有所述焊料层的一侧面的相反侧的面上；以及
另一引线框，该另一引线框以夹着具有多个空孔的另一多孔镀镍部的方式配置在所述另一焊料层上，
在位于所述另一多孔镀镍部的与所述另一焊料层相接合的面上的所述空孔中，埋入有导热率高于镍的粒子。
本发明12是一种半导体装置的制造方法，包括：
多孔镀镍工序，该多孔镀镍工序对引线框施加多孔镀镍；以及
焊料接合工序，该焊料接合工序利用焊料将半导体元件与所述引线框的施加了所述多孔镀镍的一侧进行接合。
本发明13是本发明12的半导体装置的制造方法，还包括：
粒子埋入工序，该粒子埋入工序将导热率高于镍的粒子埋入到位于由所述多孔镀镍工序施加到所述引线框的所述多孔镀镍的表面的空孔中。
本发明14是本发明12或13的半导体装置的制造方法，
所述多孔镀镍工序中，选择性地在所述引线框的与所述半导体元件进行接合的一侧的面上施加所述多孔镀镍。
本发明15是一种半导体装置，
该半导体装置是由本发明12的半导体装置的制造方法所制造的半导体装置，
所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
本发明16是一种半导体装置，
该半导体装置是由本发明13的半导体装置的制造方法所制造的半导体装置，
埋入有所述粒子的所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
通过施加多孔镀镍，从而使得在半导体元件和引线框之间存在有线膨胀系数和弹性模量都较低的层。由此，即使功率半导体元件发热，引线框发生较大的膨胀，在镀敷层中产生变形，但是由于镀敷层的弹性模量较小，因而能够缓和在焊料层中引起的热应力。
另外，尽管镀敷层与半导体元件的线膨胀系数之差会在焊料层中引起热翘曲，但是由于其差值较小，因而，施加到焊料层的热应力也较小。
另外，在本发明的半导体装置中，若对引线框施加多孔镀镍，并利用焊料来将其与半导体元件相接合，则能减小接合部的热应力，因此，接合所需的焊料层为一层。由此，与简单的焊料接合部相比，能将本发明的热阻的增加量抑制为对应于多孔镀镍层的量。
发明效果
本发明能提供一种能够抑制接合部的热阻的增大，并能减小施加到焊料层的热应力，抑制焊料裂缝的发生的半导体装置及其制造方法。
附图说明
图1是示意性地示出本发明的实施方式1的功率半导体装置的配置结构的剖视图。
图2(a)是标识本发明的实施方式1的功率半导体装置的制造工序中的镀敷工序的图，图2(b)是表示本发明的实施方式1的功率半导体装置的制造工序中的引线框固定工序的图，图2(c)是表示本发明的实施方式1的功率半导体装置的制造工序中的焊料接合工序的图。
图3是示意性地示出本发明的实施方式1的多孔镀镍的剖视图。
图4是示意性地示出本发明的实施方式1的、另一结构的功率半导体装置的配置结构的剖视图。
图5是示意性地示出本发明的实施方式1相关的实施例1至6、及比较例1至2的功率半导体装置的配置结构的剖视图。
图6(a)是示意性地示出本发明的实施方式2的功率半导体装置的配置结构的剖视图，图6(b)是表示本发明的实施方式2的功率半导体装置的多孔镀镍部分的放大剖视图。
图7(a)是表示本发明的实施方式2的功率半导体装置的制造工序中的镀敷工序的图，图7(b)是表示本发明的实施方式2的功率半导体装置的制造工序中、将纳米粒子埋入多孔镀镍(porousnickelplating)的表面的空孔的粒子埋入工序的图，图7(c)是表示本发明的实施方式2的功率半导体装置的制造工序中的引线框固定工序的图，图7(d)是表示本发明的实施方式2的功率半导体装置的制造工序中的焊料接合工序的图。
图8(a)是示意性地示出本发明的实施方式2的、镀敷工序后的多孔镀镍的的剖视图，图8(b)是示意性地示出本发明的实施方式2的、粒子埋入工序后的多孔镀镍的剖视图。
图9是示意性地示出本发明的实施方式2的、另一结构的功率半导体装置的配置结构的剖视图。
图10是示意性地示出本发明的实施方式2相关的实施例8至13、及比较例1至3的功率半导体装置的配置结构的剖视图。
图11(a)是示意性地示出以往的功率半导体装置中的、功率半导体元件及引线框之间的接合部的剖视图，图11(b)是示意性地示出在以往的功率半导体装置中设置导热性多孔金属板的情况下的、功率半导体元件及引线框间的接合部的剖视图。
附图标记
20多孔镀镍
2引线框
3绝缘体
4焊料层
5功率半导体元件
6镀镍槽
7空孔
8散热板
9绝缘树脂
10焊糊
11第二引线框
12、21第二多孔镀镍
13掩模
14第二焊料层
17纳米粒子
301功率半导体元件
302、302a、302b焊料层
303多孔金属板
304引线框
305绝缘体
306散热板
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
(实施方式1)
图1是示意性地示出本发明的实施方式1的功率半导体装置的配置结构的剖视图。
引线框2的一侧的面固定在绝缘体3上，该绝缘体3配置成其下表面与散热板8上方相接触。引线框1的实施了多孔镀镍1的另一侧的面经由焊料层4而与功率半导体元件5相接合。
另外，功率半导体元件5相当于本发明的半导体元件的一个示例。
该功率半导体装置的配置结构是例如利用图2(a)～图2(c)的工序制造的。
图2(a)～图2(c)是表示本实施方式1的功率半导体装置的制造方法的一个例子的工序图。图2(a)示出了镀敷工序，图2(b)示出了引线框固定工序，图2(c)示出了焊料接合工序。
首先，如图2(a)所示，对引线框2实施多孔镀镍1。
多孔镀镍1可以通过以下方式获得：即，例如通过将引线框2浸入放入了起泡剂的镀镍槽6来进行电镀。图2(a)中，将掩膜13安装到引线框2，从而仅选择性地对将利用焊料与功率半导体元件5进行接合的一侧的面施加多孔镀镍1。此时，通过调节流过引线框2的电流密度及镀敷时间，从而能够控制多孔镀镍1的厚度及孔隙率。
图3是示意性地示出对引线框2的表面施加了多孔镀镍1的剖视图。
此外，引线框2的表面所施加的多孔镀镍1是本发明的多孔镀镍部的一个例子。
多孔镀镍1的空孔7是高度为10～15μm的针状，孔隙率最大，则空孔7的直径越大。
对于多孔镀镍1，并不限于图2(a)所示出那样的、仅选择性地施加在引线框2的利用焊料与功率半导体元件5进行接合的部分，也可以施加到引线框2的整个表面。但是，为了抑制未与功率半导体元件5相接合的部分的热阻的增加，优选为仅选择性地将多孔镀镍1施加在利用焊料进行接合的部分。
此外，对于多孔镀镍1，在其线膨胀系数小于引线框2的线膨胀系数并大于功率半导体元件5的线膨胀系数的情况下，能有效地减小施加到焊料层4的热应力。可认为多孔镀镍1的线膨胀系数相当于将镍的线膨胀系数(12．8ppm)乘上(100-孔隙率)％而获得的值。功率半导体元件5的线膨胀系数大致是4-5ppm，因此，多孔镀镍1的孔隙率必须是60％以下。
另外，若多孔镀镍1的孔隙率小于20％，则单位体积的空孔数存在偏差，因而，无法获得具有均匀的孔隙率的多孔镀镍层。
由此，优选多孔镀镍1的孔隙率为20％～60％。
此外，由于多孔镀镍1的空孔7的形状是高度为10～15μm的针状，因此，若多孔镀镍1的厚度小于10μm，则镀敷厚度会存在偏差，会导致无法获得均匀的多孔镀镍层。在本实施方式1中，若多孔镀镍1的厚度大于100μm，则多孔镀镍层的热阻会增大，而且镀敷时间会变长，因此，会导致生产性降低。
由此，在本实施方式1中，尽管优选多孔镀镍1的厚度为10～100μm，但是通过使多孔镀镍1具有一定的厚度，从而能够减少焊料层4中发生的变形，并能缓和热应力，因此，对于多孔镀镍1的厚度，更优选的是能更有效地减小施加到焊料层4的应力的20～100μm。
此外，引线框2的材质可以是铜或铝，但是更优选导电率和导热率都较高的铜。
另外，上文记载了对引线框2直接施加多孔镀镍1，但是，也可以对预先实施了其他表面处理的引线框2施加多孔镀镍1。
接着，如图2(b)所示，将施加了多孔镀镍1后的引线框2固定到绝缘树脂9上。此处，使用绝缘树脂9作为绝缘体3。
对于施加了多孔镀镍1后的引线框2，以引线框2不与散热板8相接触且引线框2的一侧的面会在绝缘树脂9上露出的方式，将其放置在展开在散热板8上的绝缘树脂9上，使绝缘树脂9固化，以将引线框2固定到绝缘树脂9上。
接着，如图2(c)所示，在引线框2的露出面上对焊糊10进行丝网印刷，并在其上放置功率半导体元件5，从而构成本发明的配置结构。能根据使用具有本发明的配置结构的半导体装置的环境，来适当地选择焊糊10。
此外，在向功率半导体元件5印刷焊糊10时，为了抑制热阻的增加，提供厚度为50～100μm的焊糊。
接着，使上述结构体通过回流炉(未图示)，从而获得图1所示的引线框2和功率半导体元件5间的布线结构。
根据本实施方式1的功率半导体装置的结构，在功率半导体元件5与引线框2之间，存在有线膨胀系数和弹性模量都较小的层。因而，即使功率半导体元件5发热，引线框2发生较大的膨胀，在多孔镀镍1中产生变形，但是由于多孔镀镍1的弹性模量较小，因而能够缓和在焊料层4中引起的热应力。
另外，尽管多孔镀镍1与功率半导体元件5的线膨胀系数之差会在焊料层4中引起热翘曲，但是由于其差值较小，因此，相比不存在多孔镀镍1的情况，施加到焊料层4的热应力会减小。
另外，若仅利用焊料来接合施加了多孔镀镍1的引线框2和功率半导体元件5，则能减小接合部的热应力，因此，接合所需的焊料层4为一层。由此，与简单的焊料接合部相比，能将本实施方式1的焊料接合部的热阻的增加量抑制为多孔镀镍1相对应的量。
图4是示意性地示出本实施方式1的另一结构的功率半导体装置的配置结构的剖视图。与图1相同的结构部分使用相同的标号。
图4所示的功率半导体装置中，利用焊料将功率半导体元件5的两个面都分别与引线框进行接合。功率半导体元件5的一个面经由焊料层4与施加了多孔镀镍1的引线框2相接合，在功率半导体元件5的相反侧的面经由第二焊料层14与施加了第二多孔镀镍12的第二引线框11相接合。
利用焊料将施加了将第二多孔镀镍12的第二引线框11的一端与功率半导体元件5进行接合，使其另一端与第二功率半导体元件或第三引线框(未图示)相连接。
即使在图4所示的利用焊料将多个引线框2、11与功率半导体元件5进行接合的配置结构中，也能与图1所示的配置结构获得同样的降低施加到焊料层4及第二焊料层14的热应力的效果。
此外，图4中的第二焊料层14是本发明的另一焊料层的一个例子，第二多孔镀镍12是本发明的另一多孔镀镍部的一个例子，第二引线框11是本发明的另一引线框的一个例子。
由此，通过采用本实施方式1的功率半导体装置的配置结构，从而能够抑制接合部的热阻的增加，并能减小施加到焊料层4的热应力，从而能抑制焊料裂缝的发生。
此外，上文举例说明了具备功率半导体元件的功率半导体装置的例子，但是，即使在功率半导体元件以外的半导体元件直接与引线框相接合的结构的半导体装置中，也能应用本实施方式1的结构，能获得相同的效果。
接着，通过比较本实施方式1的实施例与比较例，来说明本发明的效果。
以下，将使用模拟来说明本实施方式1的实施例，但是本发明并不限于该实施例。
在进行模拟时，将实施例1～实施例7、比较例1及比较例2共用的多孔镀镍层以外的结构构件的尺寸、材料物性值都设为相同的值。
图5是示意性地示出本实施方式1的实施例1～实施例7、比较例1及比较例2中所使用的功率半导体装置的配置结构的剖视图。
此外，实施例1～实施例6、比较例1及比较例2中，在对引线框2进行镀敷时，如图2(a)那样，使用掩膜13以使得仅对接合功率半导体元件5的一侧的面进行镀敷。在实施例7中，不使用掩膜而对引线框2的整个表面进行镀敷。
(实施例1)
如图5所示，实施例1的功率半导体装置中，利用纵4mm×横6mm×厚100mm的焊料层4(Sn—Ag—Cu、弹性模量41．6GPa、线膨胀系数21．7ppm、导热率55W／(m·K))，来接合纵4mm×横6mm×厚0．4mm的功率半导体元件5(弹性模量450GPa、线膨胀系数4．2ppm)、与纵10mm×横10mm×厚1．5mm的引线框2(铜、弹性模量120GPa、线膨胀系数16．6ppm)，上述引线框2被施加了厚度为10μm、孔隙率为20％的多孔镀镍1(弹性模量168GPa、线膨胀系数10．2ppm、导热率72．8W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的施加到焊料层4的热应力进行计算，从而将其求出。
此外，多孔镀镍1的弹性模量、线膨胀系数、及导热率是通过对镍的弹性模量(210GPa)、线膨胀系数(12．8ppm)、及导热率(91W／(m·K))分别乘上(100-孔隙率)％而获得的。对实施例2～实施例7的多孔镀镍的弹性模量和线膨胀系数进行相同的定义。
另外，计算多孔镀镍1的热阻和焊料层4的热阻的总和作为接合部的热阻值。对实施例2～实施例7的接合部的热阻值也进行相同的计算。
(实施例2)
实施例2的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为10μm、孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率36．4W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
(实施例3)
实施例3的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为20μm、孔隙率设为20％(弹性模量168GPa、线膨胀系数10．2ppm、导热率72．8W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
(实施例4)
实施例4的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为20μm、孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率36．4W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
(实施例5)
实施例5的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为100μm、孔隙率设为20％(弹性模量168GPa、线膨胀系数10．2ppm、导热率72．8W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
(实施例6)
实施例6的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为100μm、孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率36．4W／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
(实施例7)
实施例7的功率半导体装置不仅将实施例1的结构中的厚度为100μm、孔隙率为20％的多孔镀镍1施加在引线框2的与功率半导体元件5相接合的一侧的面上，还将其施加在引线框2的整个面上。因而，在图5中，不仅对引线框2的上表面施加多孔镀镍1，还对其下表面实施多孔镀镍1。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
此外，由于引线框2的下表面未固定，因此，对于热应力，具有与仅对上表面施加了多孔镀镍1的实施例1相同的值。
另外，对于热阻，分别计算引线框2的上表面侧的热阻值(多孔镀镍1的热阻和焊料层4的热阻的总和)和下表面侧的热阻值(下表面侧的多孔镀镍1的热阻)，计算上表面侧的热阻值作为接合部的热阻值。
(比较例1)
比较例1的功率半导体装置与实施例1的结构的区别在于，不对引线框2施加多孔镀镍，而施加4μm的镀镍，再利用焊料将功率半导体元件5与引线框2进行接合。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
另外，计算焊料层4的热阻作为接合部的热阻值。
(比较例2)
比较例2的功率半导体装置是将实施例1的结构中的多孔镀镍1的厚度设为200μm，孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率36．4w／(m·K))。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例1相同。
另外，计算多孔镀镍1的热阻和焊料层4的热阻的总和作为接合部的热阻值。
(评价)
表1中示出了实施例1～实施例7、比较例1及比较例2的各焊料层4上所施加的最大热应力和接合部的热阻值。
[表1]
根据表1，在实施例1～实施例7中，施加到焊料层4上的热应力相比比较例1降低了大约4～50％。另外，实施例1～实施例7的热阻值被抑制为比较例1的1．1～2．5倍。
对于功率半导体的接合部，适当的热阻值的范围会根据功率半导体元件5的接合面的面积而变化，但是，就在本模拟中所使用的功率半导体元件5(纵4mm×横6mm)与引线框2间的功率半导体的接合部的热阻值而言，对于一个接合面，0．2K／W以下即为合适的热阻值，但是更优选0．15K／W以下的热阻值。
在比较例2中，尽管具有极小的420MPa的热应力，但是热阻值却是较大的0．306K／W，因而，并不是合适的功率半导体的接合部。
此外，如实施例7所示，功率半导体元件5的接合面上的热阻值，与仅对引线框2的上表面施加多孔镀镍1(实施例1)的情况下的热阻值是相同的。因而，在对引线框2的整个面施加与实施例2～实施例6具有相同厚度的多孔镀镍1的情况下，也能分别获得与实施例2～实施例6的热阻值相同的值。
另外，在多孔镀镍1的厚度是10μm的实施例1、2、7中，与比较例1相比，热应力只下降了5％以下，在多孔镀镍1的厚度是20μm的实施例3～6中，与比较例1相比，焊料层4的热应力下降了10％以上，因此，能更有效地降低应力。
(实施方式2)
图6(a)是示意性地示出本发明的实施方式2的功率半导体装置的配置结构的剖视图。
此外，实施方式2中所使用的图6～图10与实施方式1中所使用的图1～图5的相同的构成部分使用相同标号进行表示。
引线框2的一侧的面固定在绝缘体3上，该绝缘体3配置成其下表面与散热板8上方相接触。引线框2的施加了多孔镀镍20的另一侧的面经由焊料层4而与功率半导体元件5相接合。
图6(b)是对图6(a)中以虚线的圆形围住的多孔镀镍20部分进行扩大表示的剖视图。
如图6(b)所示，多孔镀镍20中，在位于与焊料层4相接合的一侧的表面的空孔7内，埋入有导热率高的纳米粒子17。
在本实施方式2中，在多孔镀镍20的空孔7内埋入纳米粒子17，这一点不同于实施方式1的多孔镀镍1的空孔7内未埋入纳米粒子17。
此外，纳米粒子17是本发明的埋入在位于与焊料层相接合的面上的空孔中、比镍的导热率要高的粒子的一个例子。
该功率半导体装置的配置结构是例如利用图7(a)～(d)的工序制造的。
图7(a)～(d)是表示本实施方式2的功率半导体装置的制造方法的一个例子的工序图。图7(a)示出了镀敷工序，图7(b)示出了将纳米粒子17埋入多孔镀镍20的表面的空孔7的粒子埋入工序，图7(c)示出了引线框固定工序，图7(d)示出了焊料接合工序。
首先，如图7(a)所示，对引线框2施加多孔镀镍20。
多孔镀镍20可以通过以下方式获得：即，例如通过将引线框2浸入放入了起泡剂的镀镍槽6来进行电镀。图7(a)中，将掩膜13安装到引线框2，从而仅选择性地对将利用焊料与功率半导体元件5进行结合的一侧的面施加多孔镀镍20。此时，通过调节流过引线框2的电流密度及镀敷时间，从而能够控制多孔镀镍20的厚度及孔隙率。
图8(a)是示意性地示出在实施了图7(a)的镀敷工序之后的、对引线框2的表面施加了多孔镀镍20的剖视图。
多孔镀镍20的空孔7是高度为10～15μm的针状，孔隙率最大，则空孔7的直径越大。
对于多孔镀镍20，并不限于图7(a)所示出那样的、仅选择性地施加在引线框2的与功率半导体元件5进行焊料结合的部分，也可以施加到引线框2的整个表面。但是，为了抑制未与功率半导体元件5相接合的部分的热阻的增加，优选为仅选择性地将多孔镀镍20施加在利用焊料进行结合的部分。
此外，对于多孔镀镍20，在其线膨胀系数小于引线框2的线膨胀系数并大于功率半导体元件5的线膨胀系数的情况下，能有效地减小施加到焊料层4的热应力。可认为多孔镀镍20的线膨胀系数相当于将镍的线膨胀系数(12．8ppm)乘上(100-孔隙率)％而获得的值。功率半导体元件5的线膨胀系数大致是4-5ppm，因此，多孔镀镍20的孔隙率必须是60％以下。
另外，若多孔镀镍20的孔隙率小于20％，则单位体积的空孔数存在偏差，因而，无法获得具有均匀孔隙率的多孔镀镍层。
由此，优选多孔镀镍20的孔隙率为20％～60％。
此外，由于多孔镀镍20的空孔7的形状是高度为10～15μm的针状，因此，若多孔镀镍1的厚度小于10μm，则镀敷厚度会存在偏差，会导致无法获得均匀的多孔镀镍层。在本实施方式2中，若多孔镀镍1的厚度大于200μm，则多孔镀镍层的热阻会增大，而且镀敷时间会变长，因此，会导致生产性降低。
由此，在本实施方式2中，尽管优选多孔镀镍20的厚度为10～200μm，但是通过使多孔镀镍20具有一定的厚度，从而能够减少焊料层4中发生的变形，并能缓和热应力，因此，对于多孔镀镍1的厚度，更优选的是能更有效地减小施加到焊料层4的应力的20～200μm。
此外，引线框2的材质可以是铜或铝，但是更优选导电率和导热率都较高的铜。
另外，上文记载了对引线框2直接施加多孔镀镍20，但是，也可以对预先实施了其他表面处理的引线框2施加多孔镀镍20。
接着，如图7(b)所示，向施加于引线框2的多孔镀镍20的表面的空孔7埋入纳米粒子17。
作为向多孔镀镍20的表面埋入纳米粒子17的方法，例如有将引线框2浸入超声波洗净槽15，并实施超声波振动的方法，上述超声波洗净槽15中放入有能使纳米粒子17均匀分散的溶液16。作为使纳米粒子17均匀分散的溶液16，使用表面张力较小的例如乙醇的水溶液等。通过调整使纳米粒子17分散的混合溶液16的浓度和实施超声波振动的时间，从而能够以均匀的密度将纳米粒子17导入多孔镀镍20的表面的空孔7。
然后，对于在多孔镀镍20的表面导入了纳米粒子17的引线框2，例如通过减压或微加热等方式来使溶剂蒸发。
图8(b)是示意性地示出在实施了图7(b)的粒子埋入工序之后的、对引线框2的表面施加了多孔镀镍20的剖视图。
由此，引线框2的表面所施加的多孔镀镍20是本发明的多孔镀镍部的一个例子。
若纳米粒子17的导热率高于镍的导热率(大约90．5w／(m·K))，则能有效地减小接合部的热阻。由此，优选纳米粒子17的材质是91W／(m·K)以上的导热率。优选纳米粒子17的材质是炭材料(金刚石、碳纳米管、石墨等)，其中，优选导热率较高的金刚石(大约2000W／(m·K))。
此外，通过将尺寸较小的纳米粒子17埋入多孔镀镍20的表面的空孔7中，粒子与粒子之间的接触面积会增大，粒子与多孔镀镍20之间的接触面积也会增大，能进一步减小热阻。由此，优选纳米粒子17的尺寸为50nm以下。若大于50nm，则与多孔镀镍20的接触面积减小，不能有效地传导热。
然而，若纳米粒子17小于4nm，由于扩散后的纳米粒子非常轻，因此，难以利用超声波振动进行控制，且纳米粒子不易浸入多孔镀镍20的空孔7，因此，优选纳米粒子17大于4nm。
纳米粒子17会在保持粒子的状态下以一定密度进入多孔镀镍20的表面的空孔7，因此，不会影响多孔镀镍20的应力缓和效果。因而，对于将纳米粒子17埋入表面的空孔7的多孔镀镍20，其弹性模量、线膨胀系数与未向表面空孔7埋入纳米粒子17的多孔镀镍的弹性模量、线膨胀系数相同。
此外，对于导热率较高的纳米粒子17，由于其以一定密度填充到多孔镀镍20的表面的空孔7，因此，其与多孔镀镍20具有足够的接触面积，因此，多孔镀镍20散发出的热能迅速地被释放。
接着，如图7(c)所示，施加多孔镀镍20，并将在多孔镀镍20的表面埋入了纳米粒子17的引线框2固定到绝缘树脂9上。此处，使用绝缘树脂9作为绝缘体3。
对于施加了在表面埋入有纳米粒子17的多孔镀镍17后的引线框2，以引线框2不与散热板8相接触且引线框2的一侧的面会在绝缘树脂9上露出的方式，将引线框2放置在展开在散热板8上的绝缘树脂9上，使绝缘树脂9固化，以将引线框2固定到绝缘树脂9上。
接着，如图7(d)所示，在引线框2的露出面上对焊糊10进行丝网印刷，并在其上放置功率半导体元件5，从而构成本发明的配置结构。能根据使用具有本发明的配置结构的半导体装置的环境，来适当地选择焊糊10。
此外，在向功率半导体元件5印刷焊糊10时，提供厚度为50～100μm的焊糊。在焊料层的厚度为50μm以下的情况下，功率半导体元件5与多孔镀镍20的接合强度会下降，而在焊料层的厚度为100μm以上的情况下，热阻会增加，因此，提供焊糊10，以使得焊料层的厚度为50～100μm。
接着，使上述结构体通过回流炉(未图示)，从而获得图6(a)所示的引线框2和功率半导体元件5间的布线结构。
根据本实施方式2的半导体装置的结构，在功率半导体元件5与引线框2之间，存在有线膨胀系数和弹性模量都较小的层。因而，即使功率半导体元件5发热，引线框2发生较大的膨胀，在埋入有纳米粒子17的多孔镀镍20中产生变形，但是由于多孔镀镍1的弹性模量较小，因而能够缓和在焊料层4中引起的热应力。
另外，尽管埋入有纳米粒子17的多孔镀镍20与功率半导体元件5的线膨胀系数之差会在焊料层4中引起热翘曲，但是由于其差值较小，因此，相比不存在埋入有纳米粒子17的多孔镀镍20的情况，施加到焊料层4的热应力会减小。
另外，若仅利用焊料来对引线框2与功率半导体元件5进行接合，则能减小接合部的热应力，因此，接合所需的焊料层4为一层，上述引线框上施加了其表面的空孔7中埋入有纳米粒子17的多孔镀镍20。由此，与简单的焊料接合部相比，能将本实施方式2的焊料接合部的热阻的增加量抑制为多孔镀镍20相对应的量。而且，由于将导热率高的纳米粒子17埋入多孔镀镍20的表面的空孔7中，因此，能进一步抑制由多孔镀镍20引起的热阻的增加量。
图9是示意性地示出本实施方式2的另一结构的功率半导体装置的配置结构的剖视图。与图6相同的结构部分使用相同的标号。
图9所示的功率半导体装置中，功率半导体元件5的两个面都分别利用焊料与引线框进行接合。功率半导体元件5的一个面经由焊料层4与实施了多孔镀镍20的引线框2相接合，在功率半导体元件5的相反侧的面经由第二焊料层14与实施了第二多孔镀镍21的第二引线框11相接合。
位于多孔镀镍20的与焊料层4相接合的一侧的表面的空孔7中，埋入有图6(b)所示的纳米粒子17。同样的，对位于第二多孔镀镍21的与第二焊料层14相接合的一侧的表面的空孔中，也埋入纳米粒子。
利用焊料将施加了将第二引线框11的一端与功率半导体元件5进行接合，使其另一端与第二功率半导体元件或第三引线框(未图示)相连接，上述第二引线框11上施加有第二多孔镀镍21，该第二多孔镀镍21的表面埋入有纳米粒子。
即使在图9所示的利用焊料将多个引线框2、11与功率半导体元件5进行接合的配置结构中，也能与图6(a)所示的配置结构获得同样的降低施加到焊料层4及第二焊料层14的热应力的效果。
此外，图9的第二焊料层14是本发明的另一焊料层的一个例子，在其表面的空孔中埋入有纳米粒子的第二多孔镀镍21是本发明的具有多个空孔的另一多孔镀镍部的一个例子，第二引线框11是本发明的另一引线框的一个例子。
由此，通过采用本实施方式2的功率半导体装置的配置结构，从而能够抑制接合部的热阻的增加，并能减小施加到焊料层4的热应力，从而能抑制焊料裂缝的发生。
此外，上文举例说明了具备功率半导体元件的功率半导体装置的例子，但是，即使是采用功率半导体元件以外的半导体元件直接与引线框相接合的结构的半导体装置中，也能应用本实施方式2的结构，能获得相同的效果。
接着，通过比较本实施方式2的实施例与比较例，来说明本发明的效果。
以下，将使用模拟来说明本实施方式2的实施例，但是本发明并不限于该实施例。
在进行模拟时，将实施例8～实施例13、比较例1及比较例3共用的多孔镀镍层以外的结构构件的尺寸、材料物性值都设为相同的值。
图10是示意性地示出本实施方式2的实施例8～实施例13、比较例1及比较例3中所使用的功率半导体装置的配置结构的剖视图。
此外，实施例8～实施例13、比较例1及比较例3中，在对引线框2进行镀敷时，如图7(a)那样，使用掩膜13以使得仅对接合功率半导体元件5的一侧的面进行镀敷。
(实施例8)
如图10所示，实施例8的功率半导体装置中，利用纵4mm×横6mm×厚100mm的焊料层4(Sn—Ag—Cu、弹性模量41．6GPa、线膨胀系数21．7ppm、导热率55W／(m·K))，来接合纵4mm×横6mm×厚0．4mm的功率半导体元件5(弹性模量450GPa、线膨胀系数4．2ppm)、与纵10mm×横10mm×厚1．5mm的引线框2(铜、弹性模量120GPa、线膨胀系数16．6ppm)，上述引线框2被施加了厚度为20μm、孔隙率为20％的多孔镀镍20(弹性模量168GPa、线膨胀系数10．2ppm、导热率172．8W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000W／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。
此外，对于在表面的空孔7中埋入有纳米粒子17的多孔镀镍20的弹性模量、线膨胀系数，是通过分别对镍的弹性模量(210GPa)、线膨胀系数(12．8ppm)乘上(100-孔隙率)％而获得的。对实施例9～实施例13的多孔镀镍的弹性模量和线膨胀系数进行相同的定义。
另外，对于在表面的空孔7中埋入有纳米粒子17的多孔镀镍20的导热率，是通过将对镍的导热率(91W／(m·K)乘上(100-孔隙率)％而获得的值、与对纳米金刚石(导热率2000w／(m·K))的导热率乘上((纳米粒子的厚度／多孔镀镍的厚度)×孔隙率)％而获得的值进行相加而得到的。对实施例9～实施例13的多孔镀镍的导热率进行相同的定义。
另外，计算在表面的空孔中埋入有纳米金刚石的多孔镀镍20的热阻与焊料层4的热阻的总和，将其作为接合部的热阻值。对实施例9～实施例13的接合部的热阻值也进行相同的计算。
(实施例9)
实施例9的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为20μm、孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率336．4W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000W／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
(实施例10)
实施例10的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为100μm，孔隙率设为20％(弹性模量168GPa、线膨胀系数10．2ppm、导热率92．8W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000W／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
(实施例11)
实施例11的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为100μm，孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率96．4W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000W／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
(实施例12)
实施例12的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为200μm、孔隙率设为20％(弹性模量168GPa、线膨胀系数10．2ppm、导热率82．8W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000w／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
(实施例13)
实施例13的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为200μm、孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率66．4W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000W／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
(比较例1)
比较例1的功率半导体装置与实施例8的结构的区别在于，不对引线框2施加在其表面的空孔中埋入有纳米金刚石的多孔镀镍20，而施加4μm的镀镍，再利用焊料将功率半导体元件5与引线框2进行接合。该比较例1的结构与实施方式1中作为比较例使用的比较例1具有相同的结构。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
另外，计算焊料层4的热阻作为接合部的热阻值。
(比较例3)
比较例3的功率半导体装置是将实施例8的结构中的多孔镀镍20的厚度设为300μm，孔隙率设为60％(弹性模量84GPa、线膨胀系数5．1ppm、导热率56．4W／(m·K))。在多孔镀镍20的表面的空孔7中埋入有纳米粒子17(纳米金刚石：导热率2000w／(m·K))，并将多孔镀镍20的厚度设为5μm。
在该功率半导体装置的功率半导体元件5与引线框2间的布线结构中，利用线性结构解析(FEM)来对结构构件的温度从200℃变化到-40℃时的、施加到焊料层4的热应力进行计算，从而将其求出。其它结构与实施例8相同。
另外，计算在表面的空孔中埋入有纳米金刚石的多孔镀镍20的热阻与焊料层4的热阻的总和，将其作为接合部的热阻值。
(评价)
表2中示出了实施例8～实施例13、比较例1及比较例3的各焊料层4上所施加的最大热应力和接合部的热阻值。
此外，作为参考，表2中还示出了在实施例8～实施例11、及实施例13的各结构中、采用未埋入有纳米金刚石的多孔镀镍20的情况下的热阻值。
[表2]
根据表2，在实施例8～实施例13中，施加到焊料层4上的热应力相比比较例1降低了大约9～60％。另外，实施例8～实施例13的热阻值被抑制为比较例1的0．1～2．6倍。
对于功率半导体的接合部，适当的热阻值的范围会根据功率半导体元件5的接合面的面积而变化，但是，就在本模拟中所使用的功率半导体元件5(纵4mm×横6mm)与引线框2间的功率半导体的接合部的热阻值而言，对于一个接合面，0．2K／W以下即为合适的热阻值，但是更优选0．15K／W以下的热阻值。
在比较例3中，尽管具有极小的403MPa的热应力，但是热阻值却是较大的0．298K／W，因而，并不是合适的功率半导体的接合部。
另外，在表面的空孔中埋入有纳米金刚石的多孔镀镍20的厚度为20μm的实施例8、9中，其热应力相比比较例1降低了10％以下，而在表面的空孔中埋入有纳米金刚石的多孔镀镍20的厚度为100μm以上的实施例10～13中，施加到焊料层4的热应力相比比较例1降低了大约45％以下，能更有效地降低应力。
另外，根据表2可知，在实施例8～实施例13所示的结构中，与采用未埋入纳米金刚石的多孔镀镍的情况相比，通过在多孔镀镍20的表面埋入纳米金刚石，从而能进一步降低接合部的热阻值。
因而，通过在多孔镀镍中埋入纳米金刚石，从而能以更薄的多孔镀镍获得合适的热阻值。另外，即使增大多孔镀镍的厚度，也仍能维持较低的热阻值，而且增大多孔镀镍的厚度还能进一步减小热应力。
如上所述，本实施方式2的功率半导体装置中，对引线框2施加多孔镀镍20，并在多孔镀镍20的焊料层4侧的表面的空孔7中埋入导热率高的纳米粒子17，从而在功率半导体元件5与引线框2之间存在有线膨胀系数和弹性模量都较低、且局部的热阻也较小的层。由此，即使功率半导体元件5发热，引线框2发生较大的膨胀，在多孔镀镍20这层中产生变形，但是由于多孔镀镍20的弹性模量较小，因而能够缓和在焊料层4中引起的热应力。
另外，尽管多孔镀镍20这层与功率半导体元件5的线膨胀系数之差会在焊料层4中引起热翘曲，但是由于其差值较小，因而，施加到焊料层4的热应力也较小。而且，由于多孔镀镍20与焊料层4的接合面的热阻较小，因此，能提高该接合面上的热扩散性能，且能缓和热循环中的多孔镀镍20这层与焊料层4的接合界面上的热应力集中。
工业中的实用性
本发明的半导体装置及其制造方法具有能抑制接合部的热阻的增加、降低施加到焊料层的热应力、抑制焊料裂缝的发生的效果，能用于电动汽车的电动机用逆变器基板、在室内外使用的发电系统的功率调节器等汽车、环境、住宅、基础设施领域。

Claims (15)

1.一种半导体装置，其特征在于，包括：
半导体元件；
焊料层，该焊料层配置在所述半导体元件的至少一个面上；以及引线框，该引线框以夹着多孔镀镍部的方式配置在所述焊料层上，所述多孔镀镍部的厚度是10～100μm，孔隙率是20～60％。
2.如权利要求1所述的半导体装置，其特征在于，
将所述多孔镀镍部施加到所述引线框上。
3.如权利要求1所述的半导体装置，其特征在于，
所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
4.如权利要求1所述的半导体装置，其特征在于，包括：
另一焊料层，该另一焊料层配置在所述半导体元件的配置有所述焊料层的一侧面的相反侧的面上；以及
另一引线框，该另一引线框以夹着另一多孔镀镍部的方式配置在所述另一焊料层上。
5.如权利要求1所述的半导体装置，其特征在于，
所述多孔镀镍部具有多个空孔，
在位于所述多孔镀镍部的与所述焊料层相接合的面上的所述空孔中，埋入有导热率高于镍的粒子。
6.如权利要求5所述的半导体装置，其特征在于，
埋入有所述粒子的所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
7.如权利要求5或6所述的半导体装置，其特征在于，
埋入所述空孔的所述粒子是炭材料的粒子。
8.如权利要求5所述的半导体装置，其特征在于，
所述多孔镀镍部的厚度是10～200μm，孔隙率是20～60％。
9.如权利要求5所述的半导体装置，其特征在于，
埋入所述空孔的粒子的直径是4～50nm。
10.如权利要求5所述的半导体装置，其特征在于，包括：
另一焊料层，该另一焊料层配置在所述半导体元件的配置有所述焊料层的一侧面的相反侧的面上；以及
另一引线框，该另一引线框以夹着具有多个空孔的另一多孔镀镍部的方式配置在所述另一焊料层上，
在位于所述另一多孔镀镍部的与所述另一焊料层相接合的面上的所述空孔中，埋入有导热率高于镍的粒子。
11.一种半导体装置的制造方法，其特征在于，包括：
多孔镀镍工序，该多孔镀镍工序对引线框施加厚度为10～100μm、空隙率为20～60％的多孔镀镍部；以及
焊料接合工序，该焊料接合工序利用焊料将半导体元件、与所述引线框的施加了所述多孔镀镍部的一侧进行接合。
12.如权利要求11所述的半导体装置的制造方法，其特征在于，
还包括粒子埋入工序，该粒子埋入工序将导热率高于镍的粒子埋入到位于由所述多孔镀镍工序施加到所述引线框的所述多孔镀镍部的表面的空孔中。
13.如权利要求11或12所述的半导体装置的制造方法，其特征在于，
在所述多孔镀镍工序中，选择性地在所述引线框的与所述半导体元件进行接合的一侧的面上施加所述多孔镀镍部。
14.一种半导体装置，
该半导体装置是利用权利要求11记载的的半导体装置的制造方法所制造的半导体装置，其特征在于，
所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
15.一种半导体装置，
该半导体装置是利用权利要求12记载的的半导体装置的制造方法所制造的半导体装置，其特征在于，
埋入有所述粒子的所述多孔镀镍部的线膨胀系数大于所述半导体元件的线膨胀系数且小于所述引线框的线膨胀系数。
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