TWI433243B - 無載具之半導體封裝件及其製法 - Google Patents

無載具之半導體封裝件及其製法 Download PDF

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Publication number
TWI433243B
TWI433243B TW099122791A TW99122791A TWI433243B TW I433243 B TWI433243 B TW I433243B TW 099122791 A TW099122791 A TW 099122791A TW 99122791 A TW99122791 A TW 99122791A TW I433243 B TWI433243 B TW I433243B
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Taiwan
Prior art keywords
layer
metal
carrier
semiconductor package
connection pad
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TW099122791A
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English (en)
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TW201203397A (en
Inventor
蔡岳穎
湯富地
黃建屏
柯俊吉
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矽品精密工業股份有限公司
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Priority to TW099122791A priority Critical patent/TWI433243B/zh
Priority to US12/967,839 priority patent/US8975734B2/en
Publication of TW201203397A publication Critical patent/TW201203397A/zh
Application granted granted Critical
Publication of TWI433243B publication Critical patent/TWI433243B/zh
Priority to US14/319,321 priority patent/US9190296B2/en

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Description

無載具之半導體封裝件及其製法
本發明係有關一種半導體封裝件及其製法，尤係關於一無載具之半導體封裝件，以及製造該半導體封裝件之方法。
傳統以導線架作為晶片承載件之半導體封件之型態及種類繁多，就四邊扁平無導腳(Quad Flat Non-leaded,QFN)半導體封裝件而言，其特徵在於未設置有外導腳，即未形成有如習知四邊形平面(Quad Flat package,QFP)半導體封裝件中用以與外界電性連接之外導腳，如此，將得以縮小半導體封裝件之尺寸。然而伴隨半導體產品輕薄短小之發展趨勢，傳統導線架之QFN封裝件往往因其封裝膠體厚度之限制，而無法進一步縮小封裝件之整體高度，因此，業界便發展出一種無載具(carrier)之半導體封裝件，冀藉由減低習用之導線架厚度，以令其整體厚度得以較傳統導線架式封裝件更為輕薄。
請參閱第1圖，係為美國專利第5,830,800號案所揭示之無載具之半導體封裝件，該半導體封裝件主要先於一銅板(未圖示)上形成多數銲墊(Pad)12，接著，再於該銅板上設置晶片13並透過銲線14電性連接晶片13及銲墊12，復進行封裝模壓製程以形成封裝膠體15，然後再蝕刻移除該銅板以使銲墊12顯露於外界，接著以拒銲層11定義出該銲墊12位置，以供植設銲球46於該銲墊12上，藉以完成一無需晶片承載件之封裝件。相關之技術內容亦可參閱美國專利第6,770,959、6,989,294、6,933,594及6,872,661等。
然而，該銲墊12厚度僅約1至5μm薄，且與封裝膠體15的附著力差，故易發生脫層問題，甚或導致銲線14之斷裂；再者形成銲墊12係使用昂貴之金(Au)、鈀(Pd)等貴重金屬作為移除銅板之蝕刻阻層，增加製程成本。
為改善前述問題，美國專利第6,498,099號案提出一種製程方式，主要係如第2A至2D’圖所示，先提供一銅板20，並在銅板20上表面進行半蝕刻，以形成作為電性終端(terminal)之銲墊22及供接置晶片之晶片墊21，並於該銅板20上表面全面鍍上鎳(Ni)或銀(Ag)等鍍層27；再將半導體晶片23接置於該晶片墊21上，並透過銲線24連接該半導體晶片23與銲墊22，以藉由該鍍層27使該銲線24與該銲墊22有效接合，及形成覆蓋該半導體晶片23、銲線24及銅板20上表面之封裝膠體25；接著對銅板20下表面進行蝕刻以外露出封裝膠體25，且保留銲墊22及晶片墊21；之後於銲墊22下表面形成無電解電鍍金並植設銲球26，以供半導體封裝件得以透過該銲球26回銲形成銲錫接(solder joint)而銲結至電路板(PCB)28上。
該製程透過全面鍍覆鎳或銀之鍍層，而不必如美國專利第5,830,800號案使用金/鈀作為蝕刻阻層，從而降低成本，但因該鎳或銀等鍍層與封裝膠體之結合性不佳，容易因熱應力而導致脫層(delamination)而造成水氣滲入(如第2C’圖所示)。再者，當該封裝件銲接於電路板28後，於需重工(rework)該封裝件時，亦因封裝膠體25與銀層之附著力不佳，而發生如第2D’圖所示之銲墊22脫落之情事，從而造成該封裝件之報廢。且於製程中，須在已經半蝕刻的銅板上進行置晶、打線及封裝模壓製程，因該銅板已減少一半厚度而過軟，不利於製程過程中運送，且易受熱影響造成銅板彎曲。更甚者，當電性終端的輸入/輸出端增加時，此種成陣列排列之銲墊22設計，更容易發生銲線重疊(wire cross)導致短路(wire short)問題。相關如美國專利第6,700,188號案亦有相同問題。
因此，如何解決上述問題而能提供一種得降低製程成本、避免發生脫層問題及易於生產運送之無載具之半導體封裝件，實刻不容緩。
本發明之一目的在於提供一種無載具之半導體封裝件及其製法，不須使用昂貴之金、鈀作為蝕刻阻層，以降低製程成本。
本發明之又一目的在於提供一種無載具之半導體封裝件及其製法，避免鍍層與封裝膠體脫層問題。
本發明之再一目的在於提供一種無載具之半導體封裝件及其製法，於重工時避免電性終端脫落問題。
本發明之另一目的在於提供一種無載具之半導體封裝件及其製法，避免銅板結構彎曲問題，有利於量產。
為達成上揭及其他目的，本發明揭露一種無載具之半導體封裝件，包括：複數金屬塊，係彼此間隔設置；具有相對之上表面及下表面之第一膠體，係包覆該複數金屬塊之側面，且令各該金屬塊之上下端面分別外露出該第一膠體之上表面及下表面；連接墊，係設於該金屬塊上，且與該金屬塊電性耦合；半導體晶片，電性連接至該金屬塊上之連接墊；以及第二膠體，設於該第一膠體上表面上且包覆該半導體晶片及連接墊。
該半導體晶片可透過銲線或覆晶方式電性連接至該金屬塊上之連接墊，該連接墊包括金屬層(例如銅層)及覆蓋於該金屬層上之抗氧化層，例如銀層或有機可銲保護膜(OSP)，且該連接墊之平面尺寸大於金屬塊之截面積，以使該連接墊及金屬塊構成T型結構，增加金屬塊與第一膠體之結合性，避免脫層問題。
於另一態樣中，本發明復提供一種無載具之半導體封裝件，係包括：複數金屬塊，係彼此間隔設置；具有相對之上表面及下表面之第一膠體，係包覆該複數金屬塊之側面，且令各該金屬塊之上下端面分別外露出該第一膠體之上表面及下表面；連接墊，係設於該金屬塊上，且與該金屬塊電性耦合；第二膠體，形成於該第一膠體及連接墊上，且外露各該連接墊之部分；增層跡線，形成於該第二膠體及外露之部分連接墊上；鍍層，覆蓋於該增層跡線終端；半導體晶片，電性連接至該增層跡線上之鍍層；以及第三膠體，設於該第二膠體上表面上且包覆該半導體晶片及該增層跡線。
於該無載具之半導體封裝件中，該鍍層為銀層或有機可銲保護膜。
該無載具之半導體封裝件之製法包括下列步驟：製備一具有相對第一及第二表面之金屬載板(Carrier)，使該金屬載板第一表面具有相對之凹槽及金屬塊；於該凹槽中填充第一膠體，並外露出該金屬塊上表面；對應該金屬塊上形成一連接墊，該連接墊係與該金屬塊電性耦合；將半導體晶片電性連接至該金屬塊上之連接墊；於該金屬載板第一表面上形成包覆該半導體晶片及連接墊之第二膠體；以及移除該金屬載板第二表面，以外露出該金屬塊及第一膠體下表面。後續復可於該金屬塊下表面植設銲球及進行切單作業。
該半導體晶片可透過銲線或覆晶方式電性連接至該金屬塊上之連接墊，該連接墊包括金屬層(例如銅層)及覆蓋於該金屬層上之抗氧化層，例如銀層或有機可銲保護膜，且該連接墊之平面尺寸大於金屬塊之截面積，以使該連接墊及金屬塊構成T型結構，以增加金屬塊與第一膠體之結合性，避免脫層問題。
本發明復提供一種無載具之半導體封裝件之製法，係包括：製備一具有相對第一及第二表面之金屬載板，使該金屬載板第一表面具有相對之凹槽及金屬塊；於該凹槽中填充第一膠體，並外露出該金屬塊上表面；於該金屬塊上形成一連接墊，並使該連接墊與該金屬塊電性耦合；於該第一膠體及連接墊上形成第二膠體，且該第二膠體外露各該連接墊之部分；於該第二膠體及外露之部分連接墊上形成增層跡線；於該增層跡線終端覆蓋鍍層；將半導體晶片電性連接至該增層跡線上之鍍層；於該第二膠體上形成包覆該半導體晶片及該增層跡線之第三膠體；以及移除該金屬載板第二表面之部分金屬載板，以外露出該金屬塊及第一膠體下表面。
因此本發明之無載具之半導體封裝件及製法，係於金屬載板上利用半蝕刻方式形成複數凹槽及相對應之金屬塊，該金屬塊即對應為電性終端或晶片墊位置，而後於該凹槽中填充第一膠體，使該第一膠體直接與例如銅材質之金屬載板(金屬塊)接著，而未間隔其它材質之鍍層，藉以增加附著力，接著再於該金屬塊上形成一連接墊，該連接墊包括一例如銅層之金屬層及覆蓋於該金屬層上之一例如銀層或有機可銲保護膜之抗氧化層，以透過該連接墊與金屬塊形成T型鎖固結構而與第一膠體鎖合，避免脫層甚或水氣侵入問題，同時當有重工需求時亦毋須擔心鍍層與封裝膠體之結合性不佳，電性終端會與銲錫接自半導體封裝件脫落而殘留在電路板上，導致半導體封裝件報廢無用問題；而後進行置晶、打線、封裝模壓作業，形成覆蓋半導體晶片之第二膠體，而在前述置晶、打線、封裝模壓作業中，由於先前半蝕刻之凹槽已經被第一膠體填滿，故整個金屬載板具一定結構強度，避免習知銅板半蝕刻後軟弱彎曲，影響生產運送及量產問題；再者，製程中亦毋須使用昂貴之金、鈀等金屬作為蝕刻阻層，得以降低製程成本。
以下即配合所附圖式詳細說明本發明所揭露之無載具之半導體封裝件及其製法。
第一實施例
請參閱第3A至3I圖，係為本發明之無載具之半導體封裝件及其製法第一實施例之示意圖。
如第3A圖所示，準備一如銅板之金屬載板30，該金屬載板30具有相對之第一表面30a及第二表面30b。
如第3B圖所示，接著於該金屬載板30第一表面上形成圖案化之第一阻層31a，使該圖案化第一阻層31a定義出電性終端及晶片墊位置，並於該金屬載板30第二表面上覆蓋第二阻層31b，該第一及第二阻層例如為乾膜(Dry film)。
如第3C圖所示，利用半蝕刻製程移除未為該第一阻層31a覆蓋之部分金屬載板，藉以在該金屬載板30第一表面形成複數凹槽301及相對之金屬塊302，接著移除該第一阻層31a及第二阻層31b。該金屬塊302即對應構成電性終端302a及晶片墊302b。
如第3D圖所示，於該凹槽301中填充如封裝化合物(molding compound)或銲料阻層(solder mask)之第一膠體35a，該封裝化合物可為環氧樹脂或其他高分子材枓，並使該金屬塊302外露出該第一膠體35a。
如第3E圖所示，在該第一膠體35a、金屬塊302上表面以無電解電鍍或濺鍍等方式形成一如薄銅層之導電層37。
並於該導電層37上覆蓋如乾膜之第三阻層31c，並令該第三阻層31c形成有複數開口310c，其中，該開口310c位置係對應該金屬塊302位置，且該開口面積係大於對應之金屬塊之截面積。
接著利用如電鍍之方式於該第三阻層開口310c中形成一例如銅之金屬層38a，再於該金屬層38a上形成一抗氧化層38b，例如，電鍍銀之鍍層或以浸泡方式於該金屬層38a上覆蓋有機可銲保護膜，以構成一連接墊38。該金屬層之厚度約為10至50μm，該連接墊38之平面尺寸係大於金屬塊302之截面積，以形成T型鎖合結構，藉以增加金屬塊302與第一膠體35a之結合性，避免脫層問題。
此外，如第3D’及3E’圖所示，該連接墊38之製法復可包括在形成導電層37之前，於該第一膠體35a及金屬塊302上表面形成外露該金屬塊302之緩衝層39，其中，該緩衝層39之材質為苯並環丁烯(BCB)或聚醯亞胺(PI)，如此可使第一膠體35a及金屬塊302之表面平坦化，並釋放導電層37、連接墊38與第一膠體35a之間的應力。
如第3F圖所示，之後移除該第三阻層31c及為該第三阻層31c所覆蓋之導電層37。
另外，該抗氧化層38b亦可在形成該金屬層38a，並移除該第三阻層31c及其所覆蓋之導電層37後，再以噴鍍(spotting plating)方式於外露之金屬層38a上形成如銀之鍍層。
如第3G圖所示，接著進行置晶(Die Bonding;D/B)、打線(Wire Bonding;W/B)及封裝模壓製程(Molding)；對應晶片墊302b位置將半導體晶片33接置於該連接墊38上，並利用銲線34電性連接該半導體晶片33及對應電性終端302a位置之連接墊38，再於該第一膠體35a及連接墊38上形成包覆該半導體晶片33及銲線34之第二膠體35b。
如第3H圖所示，以蝕刻方式移除該金屬載板30第二表30b面，以外露出該金屬塊302及第一膠體35a下表面。據此，即如同在第一膠體35a中形成複數貫穿其上、下表面之貫孔350a，並於該貫孔中350a填充有金屬塊302。
如第3I圖所示，後續復可於該金屬塊302下表面植設銲球36及進行切單作業(Singulation)。該銲球36得以作為半導體封裝件之輸入/輸出端以與外部裝置電性連接。
透過前述製法，本發明之無載具之半導體封裝件係包括：複數金屬塊302，係彼此間隔設置；具有相對之上表面及下表面之第一膠體35a，係包覆該複數金屬塊302之側面，且令各該金屬塊302之上下端面分別外露出該第一膠體35a之上表面及下表面；連接墊38，係設於該金屬塊302上，且與該金屬塊302電性耦合；半導體晶片33，電性連接至該金屬塊302上之連接墊38；以及第二膠體35b，設於該第一膠體35a上表面上且包覆該半導體晶片33及連接墊38，其中，該連接墊38包括有一如銅之金屬層38a及覆蓋於該金屬層38a上如銀層或有機可銲保護膜之抗氧化層38b，以供該半導體晶片33透過銲線34電性連接至該金屬塊302上之連接墊38，該金屬塊302下表面復可設置銲球36，以供該無載具之半導體封裝件電性連接至外部裝置。
在如第3D’及3E’圖所示之形成有緩衝層之製法中，所得之半導體封裝件復可包括緩衝層39，係形成並夾置於該第一膠體35a與該連接墊38及第二膠體35b之間，並露出該金屬塊302之部分，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
因此本發明之無載具之半導體封裝件及製法，係於金屬載板上利用半蝕刻方式形成複數凹槽及相對應之金屬塊，該金屬塊即對應為電性終端或晶片墊位置，而後於該凹槽中填充第一膠體，使該第一膠體直接與例如銅材質之金屬載板(金屬塊)接著，而未間隔其它材質之鍍層，藉以增加附著力，接著再於該金屬塊上形成一連接墊，該連接墊包括一例如銅層之金屬層及覆蓋於該金屬層上之一例如銀層或有機可銲保護膜之抗氧化層，以透過該連接墊與金屬塊形成T型鎖固結構而與第一膠體鎖合，避免脫層甚或水氣侵入問題，同時當有重工需求時亦毋須擔心鍍層與封裝膠體之結合性不佳，電性終端會與銲錫接自半導體封裝件脫落而殘留在電路板上，導致半導體封裝件報廢無用問題；而後進行置晶、打線、封裝模壓作業，形成覆蓋半導體晶片之第二膠體，而在前述置晶、打線、封裝模壓作業中，由於先前半蝕刻之凹槽已經被第一膠體填滿，故整個金屬載板具一定結構強度，避免習知銅板半蝕刻後軟弱彎曲，影響生產運送及量產問題；再者，製程中亦毋須使用昂貴之金、鈀等金屬作為蝕刻阻層，得以降低製程成本。
第二實施例
請參閱第4圖，係為本發明之無載具之半導體封裝件及其製法第二實施例之示意圖。
本實施例與前述實施例大致相同，主要差異在於半導體晶片復可利用覆晶方式透過金屬凸塊(bump)電性耦合至金屬塊上之連接墊。
此實施例之半導體晶片43係以覆晶(Flip-Chip)方式接設於連接墊48上；詳言之，於進行置晶作業時，半導體晶片43之作用面係朝向連接墊48並藉多數凸塊(Solder Bump)49電性耦合至金屬塊上之連接墊48。
相較於以銲線導接半導體晶片與連接墊之結構，利用凸塊之覆晶技術得進一步縮短半導體晶片與連接墊間之電性連接路徑，更能確保半導體晶片與連接墊間之電性連接品質。再者，半導體晶片之非作用面得選擇性地外露出用以包覆半導體晶片之第二膠體，以使半導體晶片運作產生之熱量得藉該外露之非作用面有效散逸至外界，進而改善半導體封裝件之散熱效率。
第三實施例
請參閱第5A至5C圖，係為本發明之無載具之半導體封裝件及其製法第三實施例之示意圖。
本實施例與第一實施例大致相同，主要差異在於復包括增層跡線之製備。
首先，根據第3A至3F圖之步驟，在金屬載板30第一表面形成複數凹槽301及相對之金屬塊302，於該凹槽301中填充第一膠體35a，並使該金屬塊302外露出該第一膠體35a後，全面於該第一膠體35a及金屬塊302上表面以無電解電鍍或濺鍍等方式形成如薄銅之導電層37。接著，於該導電層37上形成一圖案化第三阻層31c，使該圖案化第三阻層31c形成有複數開口310c以定義出導電跡線及晶片墊位置，接著利用電鍍方式於該第三阻層開口310c中形成一例如銅之金屬層38a，再於該金屬層38a上形成一抗氧化層38b，例如，電鍍銀之鍍層或以浸泡方式於該金屬層38a上覆蓋有機可銲保護膜，以構成一連接墊38。接著，移除第三阻層31c，並蝕刻移除先前為該第三阻層所覆蓋之導電層37。
復參閱第5A圖，於該第一膠體35a及連接墊38上形成第二膠體35b，且該第二膠體35b外露各該連接墊38之部分。
如第5B圖所示，再參照第3A至3F圖之製法步驟，於該第二膠體35b及外露之部分連接墊38上形成增層跡線51，並於該增層跡線51終端覆蓋如銀層或有機可銲保護膜之鍍層53。
如第5C圖所示，將半導體晶片55透過銲線57電性連接至該增層跡線51上之鍍層53；於該第二膠體35b上形成包覆該半導體晶片55及該增層跡線51之第三膠體59；以及移除該金屬載板30第二表面30b之部分金屬載板30，以外露出該金屬塊302及第一膠體35a下表面。其後步驟即如前述實施例所述，接著進行植球、切單等作業，以形成一具導電跡線之低成本的無載具之半導體封裝件。
此外，本實施例中，如第5A’至5C’圖所示，復可包括在形成連接墊38之前，於該第一膠體35a上表面形成外露該金屬塊302之緩衝層39，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。如此可使第一膠體35a及金屬塊302之表面平坦化，並釋放導電層37、連接墊38與第一膠體35a之間的應力。該緩衝層39之形成係如第3D’及3E’圖所示者，故不再贅述。根據前述製法所得之無載具之半導體封裝件，包括：複數金屬塊302，係彼此間隔設置；具有相對之上表面及下表面之第一膠體35a，係包覆該複數金屬塊302之側面，且令各該金屬塊302之上下端面分別外露出該第一膠體35a之上表面及下表面；連接墊38，係設於該金屬塊302上，且與該金屬塊302電性耦合；第二膠體35b，形成於該第一膠體35a及連接墊38上，且外露各該連接墊38之部分；增層跡線51，形成於外露之部分連接墊38及其周圍之第二膠體35b上及；鍍層53，覆蓋於該增層跡線51終端；半導體晶片55，電性連接至該增層跡線51上之鍍層53；以及第三膠體59，設於該第二膠體35b上表面上且包覆該半導體晶片55及該增層跡線51。
在如第5A’至5C’圖所示之形成有緩衝層之製法中，所得之半導體封裝件復可包括緩衝層39，係形成並夾置於該第一膠體35a與該連接墊38及第二膠體35b之間，並露出該金屬塊302，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
惟以上所述者，僅係用以說明本發明之具體實施例而已，並非用以限定本發明之可實施範圍，舉凡熟習該項技藝者在未脫離本發明所指示之精神與原理下所完成之一切等效改變或修飾，仍應皆由後述之專利範圍所涵蓋。
11．．．拒銲層
12．．．銲墊
13．．．晶片
14．．．銲線
15．．．封裝膠體
16．．．銲球
20．．．銅板
21．．．晶片墊
22．．．銲墊
23．．．半導體晶片
24．．．銲線
25．．．封裝膠體
26．．．銲球
27．．．鍍層
28．．．電路板
30．．．金屬載板
30a．．．第一表面
30b．．．第二表面
31a．．．第一阻層
31b．．．第二阻層
31c．．．第三阻層
310c．．．開口
301．．．凹槽
302‧‧‧金屬塊
302a‧‧‧電性終端
302b‧‧‧晶片墊
35a‧‧‧第一膠體
303‧‧‧鍍層
33‧‧‧半導體晶片
34‧‧‧銲線
35b‧‧‧第二膠體
350a‧‧‧貫孔
36‧‧‧銲球
37‧‧‧導電層
38‧‧‧連接墊
38a‧‧‧金屬層
38b‧‧‧抗氧化層
39‧‧‧緩衝層
43‧‧‧半導體晶片
48‧‧‧連接墊
49‧‧‧凸塊
51‧‧‧增層跡線
53‧‧‧鍍層
55‧‧‧半導體晶片
57‧‧‧銲線
59‧‧‧第三膠體
第1圖為美國專利第5,830,800號案所揭示之無載具之半導體封裝件之示意圖；
第2A至2D圖為美國專利第6,498,099號案所揭示之無載具之半導體封裝件製法之示意圖；
第2C’圖為美國專利第6,498,099號案所揭示之無載具之半導體封裝件發生脫層問題之示意圖；
第2D’圖為美國專利第6,498,099號案所揭示之無載具之半導體封裝件發生重工時電性終端與銲錫脫落問題之示意圖；
第3A至3I圖為本發明之無載具之半導體封裝件第一實施例之示意圖，其中，第3D’及3E’圖係顯示形成緩衝層之示意圖；
第4圖為本發明之無載具之半導體封裝件第二實施例之示意圖；以及
第5A至5C圖為本發明之無載具之半導體封裝件第三實施例之示意圖，其中，第5A’至5C’圖係顯示形成緩衝層之示意圖。
302．．．金屬塊
302a．．．電性終端
302b．．．晶片墊
33．．．半導體晶片
34．．．銲線
35a．．．第一膠體
350a．．．貫孔
35b．．．第二膠體
38．．．連接墊
38a．．．金屬層
38b．．．抗氧化層

Claims (46)

  1. 一種無載具之半導體封裝件之製法，係包括：製備一具有相對第一及第二表面之金屬載板，使該金屬載板第一表面具有相對之凹槽及金屬塊；於該凹槽中填充第一膠體，並外露出該金屬塊上表面；於該第一膠體及金屬塊上表面形成外露該金屬塊之緩衝層；於該金屬塊上形成一連接墊，並使該連接墊與該金屬塊電性耦合；將半導體晶片電性連接至該金屬塊上之連接墊；於該金屬載板第一表面上形成包覆該半導體晶片及連接墊之第二膠體；以及移除該金屬載板第二表面之金屬載板部分，以外露出該金屬塊及第一膠體下表面。
  2. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，復包括於該金屬塊下表面植設銲球及進行切單作業。
  3. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該具有凹槽及金屬塊之金屬載板之製法係包括：提供一金屬載板，該金屬載板具有相對之第一表面及第二表面，以在該金屬載板第一表面上形成圖案化之第一阻層，並於該金屬載板第二表面上覆蓋第二阻層； 以及利用半蝕刻製程移除未為該第一阻層覆蓋之部分金屬載板，藉以在該金屬載板第一表面形成複數凹槽及相對之金屬塊。
  4. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該第一膠體係選自封裝化合物(molding compound)或銲料阻層(solder mask)。
  5. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該連接墊包括金屬層及覆蓋於該金屬層上之抗氧化層。
  6. 如申請專利範圍第5項所述之無載具之半導體封裝件之製法，其中，該金屬層為銅層。
  7. 如申請專利範圍第5項所述之無載具之半導體封裝件之製法，其中，該抗氧化層為銀層或有機可銲保護膜。
  8. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該連接墊之製法係包括：在該緩衝層及金屬塊上表面形成導電層；於該導電層上覆蓋第三阻層，並令該第三阻層形成有複數開口，其中，該開口位置係對應該金屬塊位置，且該開口面積大於對應之金屬塊之截面積；於該第三阻層開口中形成金屬層，再於該金屬層上覆蓋抗氧化層，以構成連接墊；以及移除該第三阻層及為該第三阻層所覆蓋之導電層。
  9. 如申請專利範圍第1項所述之無載具之半導體封裝件 之製法，其中，該連接墊之製法係包括：在該緩衝層及金屬塊上表面形成導電層；於該導電層上覆蓋第三阻層，並令該第三阻層形成有複數開口，其中，該開口位置係對應該金屬塊位置，且該開口面積大於對應之金屬塊之截面積；於該第三阻層開口中形成一金屬層；移除該第三阻層及為該第三阻層所覆蓋之導電層；以及於該金屬層上覆蓋抗氧化層，以構成連接墊。
  10. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
  11. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該連接墊之平面尺寸大於金屬塊之截面積，使該連接墊及金屬塊構成T型結構。
  12. 如申請專利範圍第1項所述之無載具之半導體封裝件之製法，其中，該半導體晶片透過銲線或覆晶方式電性連接至該金屬塊上之連接墊。
  13. 一種無載具之半導體封裝件之製法，係包括：製備一具有相對第一及第二表面之金屬載板，使該金屬載板第一表面具有相對之凹槽及金屬塊；於該凹槽中填充第一膠體，並外露出該金屬塊上表面；於該金屬塊上形成一連接墊，並使該連接墊與該金 屬塊電性耦合；於該第一膠體及連接墊上形成第二膠體，且該第二膠體外露各該連接墊之部分；於該第二膠體及外露之部分連接墊上形成增層跡線；於該增層跡線終端覆蓋鍍層；將半導體晶片電性連接至該增層跡線上之鍍層；於該第二膠體上形成包覆該半導體晶片及該增層跡線之第三膠體；以及移除該金屬載板第二表面之部分金屬載板，以外露出該金屬塊及第一膠體下表面。
  14. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，復包括於該金屬塊下表面植設銲球及進行切單作業。
  15. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該具有凹槽及金屬塊之金屬載板之製法係包括：提供一金屬載板，該金屬載板具有相對之第一表面及第二表面，以在該金屬載板第一表面上形成圖案化之第一阻層，並於該金屬載板第二表面上覆蓋第二阻層；以及利用半蝕刻製程移除未為該第一阻層覆蓋之部分金屬載板，藉以在該金屬載板第一表面形成複數凹槽及相對之金屬塊。
  16. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該第一膠體係選自封裝化合物(molding compound)或銲料阻層(solder mask)。
  17. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該連接墊包括金屬層及覆蓋於該金屬層上之抗氧化層。
  18. 如申請專利範圍第17項所述之無載具之半導體封裝件之製法，其中，該金屬層為銅層。
  19. 如申請專利範圍第17項所述之無載具之半導體封裝件之製法，其中，該抗氧化層為銀層或有機可銲保護膜。
  20. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，復包括在形成該連接墊之前，於該第一膠體上表面形成外露該金屬塊之緩衝層。
  21. 如申請專利範圍第20項所述之無載具之半導體封裝件之製法，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
  22. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該連接墊之製法係包括：在該第一膠體及金屬塊上表面形成導電層；於該導電層上覆蓋第三阻層，並令該第三阻層形成有複數開口，其中，該開口位置係對應該金屬塊位置，且該開口面積大於對應之金屬塊之截面積；於該第三阻層開口中形成金屬層，再於該金屬層上覆蓋抗氧化層，以構成連接墊；以及 移除該第三阻層及為該第三阻層所覆蓋之導電層。
  23. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該連接墊之製法係包括：在該第一膠體及金屬塊上表面形成導電層；於該導電層上覆蓋第三阻層，並令該第三阻層形成有複數開口，其中，該開口位置係對應該金屬塊位置，且該開口面積大於對應之金屬塊之截面積；於該第三阻層開口中形成一金屬層；移除該第三阻層及為該第三阻層所覆蓋之導電層；以及於該金屬層上覆蓋抗氧化層，以構成連接墊。
  24. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該連接墊之平面尺寸大於金屬塊之截面積，使該連接墊及金屬塊構成T型結構。
  25. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該半導體晶片透過銲線或覆晶方式電性連接至該增層跡線上之鍍層。
  26. 如申請專利範圍第13項所述之無載具之半導體封裝件之製法，其中，該鍍層為銀層或有機可銲保護膜。
  27. 一種無載具之半導體封裝件，係包括：複數金屬塊，係彼此間隔設置；具有相對之上表面及下表面之第一膠體，係包覆該複數金屬塊之側面，且令各該金屬塊之上、下端面分別外露出該第一膠體之上表面及下表面； 緩衝層，係形成並夾置於該第一膠體與該連接墊及第二膠體之間，並露出該金屬塊之部分；連接墊，係設於該金屬塊上，且與該金屬塊電性耦合；半導體晶片，電性連接至該金屬塊上之連接墊；以及第二膠體，設於該第一膠體上且包覆該半導體晶片及連接墊。
  28. 如申請專利範圍第27項所述之無載具之半導體封裝件，復包括有形成於該金屬塊下表面之銲球。
  29. 如申請專利範圍第27項所述之無載具之半導體封裝件，其中，該第一膠體係選自封裝化合物(molding compound)或銲料阻層(solder mask)。
  30. 如申請專利範圍第27項所述之無載具之半導體封裝件，其中，該半導體晶片係以銲線或覆晶方式電性連接至該金屬塊上之連接墊。
  31. 如申請專利範圍第27項所述之無載具之半導體封裝件，其中，該連接墊包括金屬層及覆蓋於該金屬層上之抗氧化層。
  32. 如申請專利範圍第31項所述之無載具之半導體封裝件，其中，該金屬層為銅層。
  33. 如申請專利範圍第31項所述之無載具之半導體封裝件，其中，該抗氧化層為銀層或有機可銲保護膜。
  34. 如申請專利範圍第27項所述之無載具之半導體封裝 件，其中，該連接墊之平面尺寸大於該金屬塊之截面積，使該連接墊及金屬塊構成T型結構。
  35. 如申請專利範圍第27項所述之無載具之半導體封裝件，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
  36. 一種無載具之半導體封裝件，係包括：複數金屬塊，係彼此間隔設置；具有相對之上表面及下表面之第一膠體，係包覆該複數金屬塊之側面，且令各該金屬塊之上下端面分別外露出該第一膠體之上表面及下表面；連接墊，係設於該金屬塊上，且與該金屬塊電性耦合；第二膠體，形成於該第一膠體及連接墊上，且外露各該連接墊之部分；增層跡線，形成於該第二膠體及外露之部分連接墊上；鍍層，覆蓋於該增層跡線終端；半導體晶片，電性連接至該增層跡線上之鍍層；以及第三膠體，設於該第二膠體上表面上且包覆該半導體晶片及該增層跡線。
  37. 如申請專利範圍第36項所述之無載具之半導體封裝件，復包括有形成於該金屬塊下表面之銲球。
  38. 如申請專利範圍第36項所述之無載具之半導體封裝件，其中，該第一膠體係選自封裝化合物(molding compound)或銲料阻層(solder mask)。
  39. 如申請專利範圍第36項所述之無載具之半導體封裝件，其中，該半導體晶片係以銲線或覆晶方式電性連接至該增層跡線上之鍍層。
  40. 如申請專利範圍第36項所述之無載具之半導體封裝件，其中，該連接墊包括金屬層及覆蓋於該金屬層上之抗氧化層。
  41. 如申請專利範圍第40項所述之無載具之半導體封裝件，其中，該金屬層為銅層。
  42. 如申請專利範圍第40項所述之無載具之半導體封裝件，其中，該抗氧化層為銀層或有機可銲保護膜。
  43. 如申請專利範圍第36項所述之無載具之半導體封裝件，其中，該連接墊之平面尺寸大於該金屬塊之截面積，使該連接墊及金屬塊構成T型結構。
  44. 如申請專利範圍第36項所述之無載具之半導體封裝件，復包括緩衝層，係形成並夾置於該第一膠體與該連接墊及第二膠體之間，並露出該金屬塊。
  45. 如申請專利範圍第44項所述之無載具之半導體封裝件，其中，該緩衝層之材質為苯並環丁烯或聚醯亞胺。
  46. 如申請專利範圍第36項所述之無載具之半導體封裝件，其中，該鍍層為銀層或有機可銲保護膜。
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