WO2013065230A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2013065230A1
WO2013065230A1 PCT/JP2012/006277 JP2012006277W WO2013065230A1 WO 2013065230 A1 WO2013065230 A1 WO 2013065230A1 JP 2012006277 W JP2012006277 W JP 2012006277W WO 2013065230 A1 WO2013065230 A1 WO 2013065230A1
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WIPO (PCT)
Prior art keywords
nickel plating
porous nickel
semiconductor device
lead frame
power semiconductor
Prior art date
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PCT/JP2012/006277
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English (en)
French (fr)
Inventor
敬子 生田
連姫 金
貴之 広瀬
小島　俊之
塚原　法人
耕一 反田
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パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to EP12837653.0A priority Critical patent/EP2775515A4/en
Priority to JP2013511448A priority patent/JP5579928B2/ja
Priority to US13/822,838 priority patent/US8816481B2/en
Priority to CN201280003499.0A priority patent/CN103201834B/zh
Publication of WO2013065230A1 publication Critical patent/WO2013065230A1/ja

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    • H01L23/495—Lead-frames or other flat leads
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/12—Electroplating: Baths therefor from solutions of nickel or cobalt
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • a power semiconductor device in which a power semiconductor element is directly bonded to a lead frame on an insulator is known.
  • FIG. 11A is a schematic cross-sectional view showing the structure of the joint between the power semiconductor element and the lead frame of the conventional power semiconductor device having such a configuration.
  • One surface of the lead frame 304 is fixed on an insulator 305 whose lower surface is placed in contact with the heat sink 306.
  • the other surface of the lead frame 304 is joined to the power semiconductor element 301 via the solder layer 302.
  • the solder 302 has been used for joining the power semiconductor element 301 and the lead frame 304.
  • the linear expansion coefficient of the lead frame 304 and the linear expansion coefficient of the power semiconductor element 301 are greatly different from each other, the power cycle when the power semiconductor device is driven increases the solder layer 302 in the solder joint portion. There was a problem that thermal stress was repeatedly applied and eventually a solder crack was generated, resulting in poor bonding.
  • Patent Document 1 the inventor of the present application has been proposed in Patent Document 1 in order to reduce the thermal stress applied to the solder layer 302 in the solder joint portion of the conventional power semiconductor device having the structure shown in FIG. We thought about applying the structure.
  • FIG. 11A is a schematic cross-sectional view showing the structure at the junction between the power semiconductor element and the lead frame when the conventional power semiconductor device shown in FIG. 11A is provided with a thermally conductive porous metal plate. Shown in b).
  • a power semiconductor element 301 and a lead frame 304 having a large difference in linear expansion coefficient are joined to a thermally conductive porous metal plate 303 sandwiched between two solder layers 302a and 302b.
  • the porous metal plate 303 is made of a heat conductive metal having a large thermal conductivity and a linear expansion coefficient such as copper or aluminum.
  • the porous metal plate 303 serves as a stress buffer plate, reduces the thermal stress applied to the solder layers 302a and 302b, and can suppress the occurrence of solder cracks.
  • the thermally conductive porous metal plate is provided between the power semiconductor element having a large difference in linear expansion coefficient and the lead frame, although the thermal stress can be reduced, the thermal resistance of the joint between the power semiconductor element and the lead frame is large. It will increase.
  • the present invention provides a semiconductor device and a method for manufacturing the same that can reduce the thermal stress on the solder layer and suppress the occurrence of solder cracks while suppressing an increase in the thermal resistance of the joint. With the goal.
  • the first aspect of the present invention provides: A semiconductor element; A solder layer disposed on at least one surface of the semiconductor element;
  • the semiconductor device includes a lead frame disposed on the solder layer with a porous nickel plating portion interposed therebetween.
  • the second aspect of the present invention is the semiconductor device according to the first aspect of the present invention having a thickness of 10 to 100 ⁇ m and a porosity of 20 to 60%.
  • the third aspect of the present invention is the semiconductor device according to the first or second aspect of the present invention, which is applied to the lead frame.
  • the fourth aspect of the present invention is In the semiconductor device according to the first aspect of the present invention, a linear expansion coefficient of the porous nickel plating portion is larger than a linear expansion coefficient of the semiconductor element and smaller than a linear expansion coefficient of the lead frame.
  • the fifth aspect of the present invention provides Another solder layer disposed on the surface opposite to the one surface of the semiconductor element on which the solder layer is disposed;
  • the semiconductor device according to the first aspect of the present invention includes the other solder layer and another lead frame disposed with another porous nickel plating portion interposed therebetween.
  • the sixth aspect of the present invention provides The porous nickel plating portion has a large number of holes,
  • particles having a thermal conductivity higher than that of nickel are embedded in the holes located on a surface of the porous nickel plating portion that is bonded to the solder layer.
  • a linear expansion coefficient of the porous nickel plating portion in which the particles are embedded is larger than a linear expansion coefficient of the semiconductor element and smaller than a linear expansion coefficient of the lead frame.
  • the particles embedded in the holes are particles of a carbon-based material.
  • the ninth aspect of the present invention provides The porous nickel plating part is the semiconductor device according to the sixth aspect of the present invention, having a thickness of 10 to 200 ⁇ m and a porosity of 20 to 60%.
  • the tenth aspect of the present invention is In the semiconductor device according to the sixth aspect of the present invention, the diameter of the particles embedded in the holes is 4 to 50 nm.
  • the eleventh aspect of the present invention is Another solder layer disposed on a surface opposite to one surface of the semiconductor element on which the solder layer is disposed;
  • the twelfth aspect of the present invention is Porous nickel plating process for applying porous nickel plating to the lead frame;
  • a method of manufacturing a semiconductor device comprising: a solder bonding step of bonding the porous nickel plated side of the lead frame to a semiconductor element by solder.
  • the thirteenth aspect of the present invention is A particle embedding step further comprising embedding particles having a higher thermal conductivity than nickel in the pores located on the surface of the porous nickel plating applied to the lead frame by the porous nickel plating step; It is a manufacturing method of a semiconductor device of the present invention.
  • the fourteenth aspect of the present invention is In the porous nickel plating process, the porous nickel plating is selectively performed on the surface of the lead frame that is to be joined to the semiconductor element.
  • the fifteenth aspect of the present invention provides The semiconductor device manufactured by the semiconductor device manufacturing method of the twelfth aspect of the present invention is In the semiconductor device, a linear expansion coefficient of the porous nickel plating portion is larger than a linear expansion coefficient of the semiconductor element and smaller than a linear expansion coefficient of the lead frame.
  • the 16th aspect of the present invention is A semiconductor device manufactured by the method for manufacturing a semiconductor device of the thirteenth aspect of the present invention, In the semiconductor device, a coefficient of linear expansion of the porous nickel plating portion in which the particles are embedded is larger than a coefficient of linear expansion of the semiconductor element and smaller than a coefficient of linear expansion of the lead frame.
  • the thermal strain is induced in the solder layer due to the difference in coefficient of linear expansion between the plating layer and the semiconductor element, the difference is small, so the thermal stress applied to the solder layer is reduced.
  • the thermal stress at the joint can be reduced simply by performing porous nickel plating on the lead frame and soldering to the semiconductor element, so that only one solder layer is required for joining.
  • the increase in the thermal resistance of the present invention is limited to the porous nickel plating layer.
  • the present invention it is possible to provide a semiconductor device and a method for manufacturing the same that can reduce the thermal stress on the solder layer and suppress the occurrence of solder cracks while suppressing an increase in the thermal resistance of the joint.
  • FIG. 1 Schematic sectional view showing an arrangement structure of the power semiconductor device according to the first embodiment of the present invention.
  • A The figure which shows the plating process in the manufacturing process of the power semiconductor device of Embodiment 1 of this invention
  • (b) The figure which shows the lead frame fixing process in the manufacturing process of the power semiconductor device of Embodiment 1 of this invention
  • (C) The figure which shows the solder joining process in the manufacturing process of the power semiconductor device of Embodiment 1 of this invention.
  • Schematic sectional view of porous nickel plating according to Embodiment 1 of the present invention Schematic sectional view showing an arrangement structure of a power semiconductor device having another configuration according to the first embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view showing an arrangement structure of a power semiconductor device according to Embodiment 1 of the present invention.
  • One surface of the lead frame 2 is fixed on an insulator 3 whose lower surface is in contact with the heat sink 8.
  • the other surface of the lead frame 2 to which the porous nickel plating 1 has been applied is bonded to the power semiconductor element 5 via the solder layer 4.
  • the power semiconductor element 5 is an example of the semiconductor element of the present invention.
  • the arrangement structure of the power semiconductor device is manufactured by, for example, the steps shown in FIGS. 2 (a) to 2 (c).
  • FIG. 2A to FIG. 2C are process diagrams showing an example of the method for manufacturing the power semiconductor device of the first embodiment.
  • 2A shows the plating process
  • FIG. 2B shows the lead frame fixing process
  • FIG. 2C shows the solder joining process.
  • porous nickel plating 1 is applied to the lead frame 2 as shown in FIG.
  • Porous nickel plating 1 is obtained, for example, by immersing the lead frame 2 in a nickel plating tank 6 containing a foaming agent and performing electroplating.
  • a mask 13 is attached to the lead frame 2 so that the porous nickel plating 1 is selectively applied only to the surface to be soldered to the power semiconductor element 5.
  • the thickness and porosity of the porous nickel plating 1 can be controlled by adjusting the current density flowing through the lead frame 2 and the plating time.
  • FIG. 3 is a schematic cross-sectional view of the porous nickel plating 1 applied to the surface of the lead frame 2.
  • porous nickel plating 1 applied to the surface of the lead frame 2 corresponds to an example of the porous nickel plating portion of the present invention.
  • the pores 7 of the porous nickel plating 1 are needle-shaped with a height of 10 to 15 ⁇ m, and the diameter of the pores 7 increases as the porosity increases.
  • the porous nickel plating 1 is not limited to being selectively applied only to the portion of the lead frame 2 that is solder-bonded to the power semiconductor element 5, but may be applied to the entire surface of the lead frame 2. Also good. However, in order to suppress an increase in the thermal resistance of the portion not joined to the power semiconductor element 5, it is preferable that the porous nickel plating 1 is selectively applied only to the portion to be soldered.
  • the porous nickel plating 1 is effective in applying thermal stress applied to the solder layer 4 when the linear expansion coefficient is smaller than the linear expansion coefficient of the lead frame 2 and larger than the linear expansion coefficient of the power semiconductor element 5. Can be reduced.
  • the linear expansion coefficient of the porous nickel plating 1 is considered to be equivalent to a value obtained by multiplying the linear expansion coefficient (12.8 ppm) of nickel by (100 ⁇ porosity)%. Since the linear expansion coefficient of the power semiconductor element 5 is about 4 to 5 ppm, the porosity of the porous nickel plating 1 needs to be 60% or less.
  • the porosity of the porous nickel plating 1 is less than 20%, the number of pores per unit volume is biased, and a porous nickel plating layer with a uniform porosity cannot be obtained.
  • the porosity of the porous nickel plating 1 is preferably 20% to 60%.
  • the shape of the pores 7 of the porous nickel plating 1 is a needle shape having a height of 10 to 15 ⁇ m, if the thickness is made smaller than 10 ⁇ m, the plating thickness varies and a uniform porous nickel plating layer can be obtained. I can't. In the first embodiment, if the thickness is made larger than 100 ⁇ m, the thermal resistance of the porous nickel plating layer increases, and the plating time becomes longer, resulting in poor productivity.
  • the thickness of the porous nickel plating 1 is preferably 10 to 100 ⁇ m, but is induced in the solder layer 4 by giving the porous nickel plating 1 a certain thickness. Since strain is reduced and thermal stress is relieved, it is more preferable to set the thickness to 20 to 100 ⁇ m, which is more effective in reducing stress on the solder layer 4.
  • the lead frame 2 is preferably made of copper or aluminum, but copper having higher conductivity and thermal conductivity is more preferable.
  • the porous nickel plating 1 is applied directly to the lead frame 2.
  • the porous nickel plating 1 may be applied to the lead frame 2 that has been subjected to another surface treatment in advance.
  • the lead frame 2 to which the porous nickel plating 1 is applied is fixed on the insulating resin 9.
  • an insulating resin 9 is used as the insulator 3.
  • Porous nickel plating 1 so that the lead frame 2 does not contact the heat radiating plate 8 and the one surface of the lead frame 2 is exposed on the insulating resin 9 on the insulating resin 9 developed on the heat radiating plate 8.
  • the lead frame 2 subjected to the above is placed, the insulating resin 9 is cured, and the lead frame 2 is fixed on the insulating resin 9.
  • cream solder 10 is screen-printed on the exposed surface of the lead frame 2, and the power semiconductor element 5 is placed thereon to constitute the arrangement structure of the present invention.
  • a suitable solder paste 10 is selected according to the environment in which the semiconductor device having the arrangement structure of the present invention is used.
  • cream solder 10 when printed on the power semiconductor element 5, it is supplied so as to have a thickness of 50 to 100 ⁇ m in order to suppress an increase in thermal resistance.
  • a layer having a low coefficient of linear expansion and a low elastic modulus is interposed between the power semiconductor element 5 and the lead frame 2. Therefore, even if the power semiconductor element 5 generates heat and the lead frame 2 expands greatly and the porous nickel plating 1 is distorted, the heat induced in the solder layer 4 because the elastic modulus of the porous nickel plating 1 is low. Stress is relieved.
  • the thermal strain is induced in the solder layer 4 due to the difference in the linear expansion coefficient between the porous nickel plating 1 and the power semiconductor element 5, but since the difference is small, the thermal stress applied to the solder layer 4 is the porous nickel plating. It is reduced compared with the case where 1 does not intervene.
  • FIG. 4 is a schematic cross-sectional view showing the arrangement structure of the power semiconductor device having another configuration according to the first embodiment.
  • the same reference numerals are used for the same components as in FIG.
  • lead frames are soldered to both surfaces of the power semiconductor element 5.
  • a lead frame 2 to which a porous nickel plating 1 is applied is bonded to one surface of the power semiconductor element 5 via a solder layer 4, and a second porous nickel plating 12 is applied to the opposite surface of the power semiconductor element 5.
  • the second lead frame 11 is joined via the second solder layer 14.
  • the other end of the second lead frame 11 whose one end subjected to the second porous nickel plating 12 is soldered to the power semiconductor element 5 is the second power semiconductor element or the third lead frame (not shown). It is connected to the.
  • the second solder layer 14 in FIG. 4 corresponds to an example of another solder layer of the present invention
  • the second porous nickel plating 12 corresponds to an example of another porous nickel plated portion of the present invention
  • the frame 11 is an example of another lead frame of the present invention.
  • the power semiconductor device including the power semiconductor element has been described as an example.
  • the configuration of the first embodiment is also applied to a semiconductor device in which a semiconductor element other than the power semiconductor element is directly bonded to the lead frame. The same effect can be obtained.
  • FIG. 5 is a schematic cross-sectional view showing an arrangement structure of power semiconductor devices used in Examples 1 to 7, Comparative Example 1 and Comparative Example 2 of the first embodiment.
  • Example 1 As shown in FIG. 5, the power semiconductor device of Example 1 has a power semiconductor element 5 (4 mm long ⁇ 6 mm wide ⁇ 0.4 mm thick) (elastic modulus 450 GPa, linear expansion coefficient 4.2 ppm), thickness 10 ⁇ m, pores Lead of 10 mm length ⁇ 10 mm width ⁇ 1.5 mm thickness coated with 20% porous nickel plating 1 (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 72.8 W / (m ⁇ K))
  • Frame 2 (copper, elastic modulus 120 GPa, linear expansion coefficient 16.6 ppm) is solder layer 4 (Sn—Ag—Cu, elastic modulus 41.6 GPa, linear expansion coefficient 21.7 ppm, 4 mm long ⁇ 6 mm wide ⁇ 100 ⁇ m thick), Bonding is performed at a thermal conductivity of 55 W / (m ⁇ K).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • the elastic modulus, linear expansion coefficient and thermal conductivity of the porous nickel plating 1 are as follows: nickel elastic modulus (210 GPa), linear expansion coefficient (12.8 ppm) and thermal conductivity (91 W / (m ⁇ K)) Each was multiplied by (100-porosity)%.
  • the elastic modulus and linear expansion coefficient of the porous nickel plating of Examples 2 to 7 were defined similarly.
  • the sum of the thermal resistance of the porous nickel plating 1 and the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • the thermal resistance values of the joints in Examples 2 to 6 were similarly calculated.
  • Example 2 In the power semiconductor device of Example 2, the thickness of the porous nickel plating 1 in the configuration of Example 1 is 10 ⁇ m, the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 36.4 W). / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 3 In the power semiconductor device of Example 3, the thickness of the porous nickel plating 1 in the configuration of Example 1 is 20 ⁇ m, the porosity is 20% (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 72.8 W). / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 4 In the power semiconductor device of Example 4, the thickness of the porous nickel plating 1 in the configuration of Example 1 is 20 ⁇ m, the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 36.4 W). / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 5 In the power semiconductor device of Example 5, the thickness of the porous nickel plating 1 is 100 ⁇ m and the porosity is 20% (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 72.8 W in the configuration of Example 1). / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 6 In the power semiconductor device of Example 6, the thickness of the porous nickel plating 1 in the configuration of Example 1 is 100 ⁇ m, the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 36.4 W). / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 7 The power semiconductor device of Example 7 is a lead in which the porous nickel plating 1 having a thickness of 10 ⁇ m and a porosity of 20% in the configuration of Example 1 is applied not only to the surface to be joined to the power semiconductor element 5 but also to the entire surface. Frame 2 was designated. Therefore, in FIG. 5, the porous nickel plating 1 is applied not only to the upper surface of the lead frame 2 but also to the lower surface.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • the thermal stress has the same value as in Example 1 in which the porous nickel plating 1 is applied only to the upper surface.
  • thermal resistance value on the upper surface side of the lead frame 2 (the sum of the thermal resistance of the porous nickel plating 1 and the thermal resistance of the solder layer 4) and the thermal resistance value on the lower surface side (the solder layer on the lower surface side).
  • the thermal resistance value on the upper surface side was calculated as the thermal resistance value of the joint.
  • Comparative Example 1 In the power semiconductor device of Comparative Example 1, in the configuration of Example 1, the lead frame 2 was subjected to nickel plating of 4 ⁇ m instead of porous nickel plating, and the power semiconductor element 5 and the lead frame 2 were soldered.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • Comparative Example 2 In the power semiconductor device of Comparative Example 2, the porous nickel plating 1 has a thickness of 200 ⁇ m and a porosity of 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 36.4 W) in the configuration of Example 1. / (M ⁇ K)).
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • the sum of the thermal resistance of the porous nickel plating 1 and the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • Table 1 shows the maximum thermal stress applied to each solder layer 4 of Examples 1 to 7, Comparative Example 1 and Comparative Example 2 and the thermal resistance value of the joint.
  • the range of the thermal resistance value suitable as a power semiconductor junction varies depending on the area of the joint surface of the power semiconductor element 5, but the power semiconductor element 5 (4 mm ⁇ 6 mm) used in this simulation and the lead frame 2
  • the thermal resistance value as the joint portion of the power semiconductor is suitably 0.2 K / W or less, more preferably 0.15 K / W or less per one joint surface.
  • the thermal resistance value at the joint surface with the power semiconductor element 5 is the same as when the porous nickel plating 1 is applied only to the upper surface of the lead frame 4 (Example 1). Therefore, when the porous nickel plating 1 having the same thickness as in the second to sixth embodiments is applied to the entire surface of the lead frame 2, the same values as the thermal resistance values in the second to sixth embodiments can be obtained.
  • Example 1 in which the thickness of the porous nickel plating 1 is 10 ⁇ m, the thermal stress reduction is 5% or less as compared with the comparative example 1, but the thickness of the porous nickel plating 1 is 20 ⁇ m or more.
  • the thermal stress of the solder layer 4 was reduced by about 10% or more compared to Comparative Example 1, and more effective stress reduction was observed.
  • FIG. 6A is a schematic cross-sectional view showing an arrangement structure of the power semiconductor device according to the second embodiment of the present invention.
  • One surface of the lead frame 2 is fixed on an insulator 3 whose lower surface is in contact with the heat sink 8.
  • the other surface of the lead frame 2 to which the porous nickel plating 20 has been applied is bonded to the power semiconductor element 5 via the solder layer 4.
  • FIG. 6 (b) shows an enlarged cross-sectional view of the porous nickel plating 20 portion surrounded by a broken-line circle in FIG. 6 (a).
  • nanoparticles 17 having high thermal conductivity are embedded in the holes 7 located on the surface on the side to be joined to the solder layer 4.
  • the point that the nanoparticles 17 are embedded in the pores 7 of the porous nickel plating 20 is that the porous nickel plating 1 of the first embodiment in which the nanoparticles 17 are not embedded in the pores 7. Is different.
  • the nanoparticle 17 corresponds to an example of a particle having a higher thermal conductivity than nickel, which is embedded in a hole located in a surface to be bonded to the solder layer of the present invention.
  • the arrangement structure of the power semiconductor device is manufactured, for example, by the steps shown in FIGS.
  • FIGS. 7A to 7D are process diagrams showing an example of the method for manufacturing the power semiconductor device of the second embodiment.
  • 7A shows a plating process
  • FIG. 7B shows a particle embedding process for embedding the nanoparticles 17 in the pores 7 on the surface of the porous nickel plating 20
  • FIG. 7C shows a lead frame fixing process
  • 7 (d) shows a soldering step.
  • porous nickel plating 20 is applied to the lead frame 2 as shown in FIG.
  • the porous nickel plating 20 is obtained, for example, by immersing the lead frame 2 in a nickel plating tank 6 containing a foaming agent and performing electroplating.
  • a mask 13 is attached to the lead frame 2, and porous nickel plating 20 is selectively applied only to the surface that is solder-bonded to the power semiconductor element 5.
  • the thickness and the porosity of the porous nickel plating 20 can be controlled by adjusting the current density flowing through the lead frame 2 and the plating time.
  • FIG. 8A shows a schematic cross-sectional view of the porous nickel plating 20 applied to the surface of the lead frame 2 after performing the plating step of FIG. 7A.
  • the pores 7 of the porous nickel plating 20 are needle-shaped with a height of 10 to 15 ⁇ m, and the diameter of the pores 7 increases as the porosity increases.
  • the porous nickel plating 20 is not limited to being selectively applied only to the portion of the lead frame 2 that is solder-bonded to the power semiconductor element 5, but may be applied to the entire surface of the lead frame 2. Also good. However, in order to suppress an increase in the thermal resistance of the portion not joined to the power semiconductor element 5, it is preferable that the porous nickel plating 20 is selectively applied only to the portion to be soldered.
  • the porous nickel plating 20 has an effect of applying thermal stress applied to the solder layer 4 when the linear expansion coefficient is smaller than the linear expansion coefficient of the lead frame 2 and larger than the linear expansion coefficient of the power semiconductor element 5. Can be reduced.
  • the linear expansion coefficient of the porous nickel plating 20 is considered to be equivalent to a value obtained by multiplying the linear expansion coefficient (12.8 ppm) of nickel by (100 ⁇ porosity)%. Since the linear expansion coefficient of the power semiconductor element 5 is about 4 to 5 ppm, the porosity of the porous nickel plating 20 needs to be 60% or less.
  • the porosity of the porous nickel plating 20 is smaller than 20%, the number of pores per unit volume is biased, and a porous nickel plating layer having a uniform porosity cannot be obtained.
  • the porosity of the porous nickel plating 20 is preferably 20% to 60%.
  • the shape of the pores 7 of the porous nickel plating 20 is a needle shape having a height of 10 to 15 ⁇ m, if the thickness is made smaller than 10 ⁇ m, the plating thickness varies and a uniform porous nickel plating layer can be obtained. Can not. In the second embodiment, if the thickness is made larger than 200 ⁇ m, the thermal resistance of the porous nickel plating layer is increased, and the plating time is further increased, resulting in poor productivity.
  • the thickness of the porous nickel plating 20 is preferably 10 to 200 ⁇ m, but is induced in the solder layer 4 by giving the porous nickel plating 20 a certain thickness. Since the strain is reduced and the thermal stress is relieved, it is more preferable to set the thickness to 20 to 200 ⁇ m, which is more effective in reducing the stress on the solder layer 4.
  • the lead frame 2 is preferably made of copper or aluminum, but copper having higher conductivity and thermal conductivity is more preferable.
  • the porous nickel plating 20 is directly applied to the lead frame 2.
  • the porous nickel plating 20 may be applied to the lead frame 2 that has been subjected to another surface treatment in advance.
  • the nanoparticles 17 are embedded in the holes 7 on the surface of the porous nickel plating 20 applied to the lead frame 2.
  • the lead frame 2 is immersed in an ultrasonic cleaning tank 15 containing a solution 16 in which the nanoparticles 17 are uniformly dispersed, and ultrasonic vibration is applied.
  • a solution 16 in which the nanoparticles 17 are uniformly dispersed an aqueous solution of ethanol having a low surface tension, for example, is used.
  • the nanoparticles 17 can be introduced into the pores 7 on the surface of the porous nickel plating 20 with a uniform density. .
  • the lead frame 2 in which the nanoparticles 17 are put on the surface of the porous nickel plating 20 evaporates the solvent by, for example, reducing pressure or slightly heating.
  • FIG. 8B shows a schematic cross-sectional view of the porous nickel plating 20 applied to the surface of the lead frame 2 after performing the particle embedding step of FIG. 7B.
  • the porous nickel plating 20 applied to the surface of the lead frame 2 in this way corresponds to an example of the porous nickel plating portion of the present invention.
  • the material of the nanoparticles 17 is preferably a thermal conductivity of 91 W / (m ⁇ K) or more.
  • the material of the nanoparticle 17 is preferably a carbon-based material (diamond, carbon nanotube, graphite, etc.), among which diamond having a high thermal conductivity (about 2000 W / (m ⁇ K)) is more preferable.
  • the size of the nanoparticles 17 is preferably 50 nm or less. If it is larger than 50 nm, the contact area with the porous nickel plating 20 becomes small, and heat cannot be efficiently conducted.
  • the nanoparticles 17 are smaller than 4 nm, the diffused nanoparticles are very light and difficult to control by ultrasonic vibration, and are difficult to enter the pores 7 of the porous nickel plating 20, so the nanoparticles 17 are larger than 4 nm. Is preferred.
  • the nanoparticles 17 do not affect the stress relaxation effect of the porous nickel plating 20 because the nanoparticles 17 are contained in the pores 7 on the surface of the porous nickel plating 20 at a constant density in the state of particles. Therefore, the porous nickel plating 20 in which the nanoparticles 17 are embedded in the surface vacancies 7 is equivalent to the elastic modulus and the linear expansion coefficient of the porous nickel plating in which the nanoparticles 17 are not added to the surface vacancies 7.
  • the nanoparticles 17 having a high thermal conductivity are packed in the pores 7 on the surface of the porous nickel plating 20 at a constant density. Therefore, the porous nickel plating 20 has a sufficient contact area with the porous nickel plating 20. Heat from the plating 20 can be quickly released.
  • the porous nickel plating 20 is applied, and the lead frame 2 in which the nanoparticles 17 are embedded in the surface of the porous nickel plating 20 is fixed on the insulating resin 9.
  • an insulating resin 9 is used as the insulator 3.
  • the nanoparticles are formed on the surface so that the lead frame 2 does not contact the heat sink 8 and one surface of the lead frame 2 is exposed on the insulating resin 9.
  • the lead frame 2 with the porous nickel plating 20 embedded with 17 is placed, the insulating resin 9 is cured, and the lead frame 2 is fixed on the insulating resin 9.
  • cream solder 10 is screen-printed on the exposed surface of the lead frame 2, and the power semiconductor element 5 is placed thereon to constitute the arrangement structure of the present invention.
  • the cream solder 10 is selected appropriately according to the environment in which the power semiconductor device having the arrangement structure of the present invention is used.
  • the cream solder 10 when the cream solder 10 is printed on the power semiconductor element 5, it is supplied so that the thickness is 50 to 100 ⁇ m.
  • the thickness of the solder layer is 50 ⁇ m or less, the bonding strength between the power semiconductor element 5 and the porous nickel plating 20 is reduced, and when it is thicker than 100 ⁇ m, the thermal resistance increases, so the thickness of the solder layer is 50 to 100 ⁇ m.
  • the cream solder 10 is supplied so that
  • a layer having a low coefficient of linear expansion and a low elastic modulus is interposed between the power semiconductor element 5 and the lead frame 2. Therefore, even if the power semiconductor element 5 generates heat, the lead frame 2 expands greatly, and the porous nickel plating 20 embedded with the nanoparticles 17 is distorted, it is induced in the solder layer 4 because of its low elastic modulus. Thermal stress is relaxed.
  • thermal strain is induced in the solder layer 4 due to the difference in linear expansion coefficient between the porous nickel plating 20 in which the nanoparticles 17 are embedded and the power semiconductor element 5, but since the difference is small, the heat applied to the solder layer 4 The stress is reduced as compared with the case where the porous nickel plating 20 embedded with the nanoparticles 17 is not interposed.
  • the thermal stress at the joint can be reduced by simply soldering the lead frame 2 with the porous nickel plating 20 in which the nanoparticles 17 are embedded in the pores 7 on the surface to the power semiconductor element 5.
  • One solder layer 4 is sufficient. From this, compared with a simple solder joint part, the increase in the thermal resistance of the solder joint part of this Embodiment 2 can be suppressed only to the part of the porous nickel plating 20. FIG. Furthermore, since the nano particles 17 having high thermal conductivity are embedded in the pores 7 on the surface of the porous nickel plating 20, the increase in thermal resistance due to the porous nickel plating 20 can be suppressed to a smaller level.
  • FIG. 9 is a schematic cross-sectional view showing an arrangement structure of a power semiconductor device having another configuration according to the second embodiment.
  • the same reference numerals are used for the same components as in FIG.
  • lead frames are soldered to both surfaces of the power semiconductor element 5.
  • a lead frame 2 on which a porous nickel plating 20 is applied is bonded to one surface of the power semiconductor element 5 via a solder layer 4, and a second porous nickel plating 21 is applied to the opposite surface of the power semiconductor element 5.
  • the second lead frame 11 is joined via the second solder layer 14.
  • nanoparticles 17 are embedded in the holes 7 located on the surface of the porous nickel plating 20 on which the solder layer 4 is bonded. Similarly, nanoparticles are embedded in the holes located on the surface of the second porous nickel plating 21 on the side to which the second solder layer 14 is bonded.
  • the other end of the second lead frame 11 soldered to the power semiconductor element 5 at one end with the second porous nickel plating 21 embedded with nanoparticles on the surface is connected to the second power semiconductor element or the third power semiconductor element. Connected to a lead frame (not shown).
  • the second solder layer 14 in FIG. 9 is an example of another solder layer according to the present invention, and the second porous nickel plating 21 in which nanoparticles are embedded in the surface holes is a large number of holes according to the present invention.
  • the second lead frame 11 corresponds to an example of another lead frame of the present invention.
  • the arrangement structure of the power semiconductor device according to the second embodiment reduces the thermal stress on the solder layer 4 and suppresses the occurrence of solder cracks while suppressing an increase in the thermal resistance of the joint. Is possible.
  • the power semiconductor device including the power semiconductor element has been described as an example.
  • the configuration of the second embodiment is also applied to a semiconductor device in which a semiconductor element other than the power semiconductor element is directly bonded to the lead frame. The same effect can be obtained.
  • FIG. 10 is a schematic cross-sectional view showing the arrangement structure of the power semiconductor devices used in Examples 8 to 13, Comparative Example 1 and Comparative Example 3 of Embodiment 2.
  • the power semiconductor device of Example 8 has a power semiconductor element 5 (elasticity 450 GPa, linear expansion coefficient 4.2 ppm) having a length of 4 mm ⁇ width of 6 mm ⁇ thickness of 0.4 mm, a thickness of 20 ⁇ m, and a hole Lead 10 mm long ⁇ 10 mm wide ⁇ 1.5 mm thick coated with 20% porous nickel plating 20 (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 172.8 W / (m ⁇ K))
  • Frame 2 (copper, elastic modulus 120 GPa, linear expansion coefficient 16.6 ppm) is solder layer 4 (Sn—Ag—Cu, elastic modulus 41.6 GPa, linear expansion coefficient 21.7 ppm, 4 mm long ⁇ 6 mm wide ⁇ 100 ⁇ m thick), Bonding is performed at a thermal conductivity of 55 W / (m ⁇ K).
  • Nanoparticles 17 nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m m
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • the elastic modulus and linear expansion coefficient of the porous nickel plating 20 in which the nanoparticles 17 are embedded in the surface voids 7 are (100 ⁇ vacancy) respectively for the elastic modulus of nickel (210 GPa) and the linear expansion coefficient (12.8 ppm). It was multiplied by% porosity.
  • the elastic modulus and linear expansion coefficient of the porous nickel plating of Examples 9 to 13 were defined similarly.
  • the thermal conductivity of the porous nickel plating 20 in which the nanoparticles 17 are embedded in the pores 7 on the surface is obtained by multiplying the thermal conductivity of nickel (91 W / (m ⁇ K)) by (100 ⁇ porosity)%.
  • the product was obtained by adding the product obtained by multiplying the thermal conductivity of nanodiameter (thermal conductivity 2000 W / (m ⁇ K)) by (nanoparticle thickness / porous nickel plating thickness) ⁇ porosity)%.
  • the thermal conductivity of the porous nickel plating in Examples 9 to 13 was defined in the same manner.
  • the sum of the thermal resistance of the porous nickel plating 20 in which nano-diamonds are embedded in the surface holes and the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • the thermal resistance values of the joints in Examples 9 to 13 were similarly calculated.
  • Example 9 In the power semiconductor device of Example 9, the thickness of the porous nickel plating 20 in the configuration of Example 8 is 20 ⁇ m, the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 336.4 W). / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the pores 7 on the surface of the porous nickel plating 20, and the thickness thereof is 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 10 The power semiconductor device of Example 10 has a porous nickel plating 20 thickness of 100 ⁇ m and a porosity of 20% (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 92.8 W) in the configuration of Example 8. / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the holes 7 on the surface of the porous nickel plating 20, and the thickness thereof is set to 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 11 In the power semiconductor device of Example 11, the thickness of the porous nickel plating 20 in the configuration of Example 8 is 100 ⁇ m, and the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 96.4 W). / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the pores 7 on the surface of the porous nickel plating 20, and the thickness thereof is 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 12 In the power semiconductor device of Example 12, the thickness of the porous nickel plating 20 in the configuration of Example 8 is 200 ⁇ m, the porosity is 20% (elastic modulus 168 GPa, linear expansion coefficient 10.2 ppm, thermal conductivity 82.8 W). / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the pores 7 on the surface of the porous nickel plating 20, and the thickness thereof is 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Example 13 In the power semiconductor device of Example 13, the thickness of the porous nickel plating 20 in the configuration of Example 8 is 200 ⁇ m, the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 66.4 W). / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the pores 7 on the surface of the porous nickel plating 20, and the thickness thereof is 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • Comparative Example 1 In the power semiconductor device of Comparative Example 1, in the configuration of Example 8, the lead frame 2 was subjected to nickel plating of 4 ⁇ m instead of the porous nickel plating 20 in which nano-diamonds were embedded in the surface holes, and the power semiconductor element 5 and the lead The frame 2 was soldered.
  • the configuration of Comparative Example 1 is the same as that of Comparative Example 1 used as the comparative example in Embodiment 1.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • Comparative Example 3 In the power semiconductor device of Comparative Example 3, in the configuration of Example 8, the thickness of the porous nickel plating 20 is 300 ⁇ m, and the porosity is 60% (elasticity 84 GPa, linear expansion coefficient 5.1 ppm, thermal conductivity 56.4 W). / (M ⁇ K)). Nanoparticles 17 (nanodia: thermal conductivity 2000 W / (m ⁇ K)) are embedded in the pores 7 on the surface of the porous nickel plating 20, and the thickness thereof is 5 ⁇ m.
  • the thermal stress applied to the solder layer 4 when the temperature of the constituent member changes from 200 ° C. to ⁇ 40 ° C. is expressed as a linear structure. It calculated
  • FEM required by calculation by analysis
  • the sum of the thermal resistance of the porous nickel plating 20 in which nano-diamonds are embedded in the surface holes and the thermal resistance of the solder layer 4 was calculated as the thermal resistance value of the joint.
  • Table 2 shows the maximum thermal stress applied to each solder layer 4 of Examples 8 to 13, Comparative Example 1 and Comparative Example 3 and the thermal resistance value of the joint.
  • Example 8 to Example 11 and Example 13 the thermal resistance values in the case of the porous nickel plating 20 in which the nano diamond is not embedded in each configuration are also shown in Table 2.
  • the range of the thermal resistance value suitable as a power semiconductor junction varies depending on the area of the joint surface of the power semiconductor element 5, but the power semiconductor element 5 (4 mm ⁇ 6 mm) used in this simulation and the lead frame 2
  • the thermal resistance value as the joint portion of the power semiconductor is suitably 0.2 K / W or less, more preferably 0.15 K / W or less per one joint surface.
  • Example 8 and 9 in which the thickness of the porous nickel plating 20 in which nanodiamonds are embedded in the surface vacancies is 20 ⁇ m, the thermal stress is reduced by 10% or less as compared with Comparative Example 1, but the surface vacancies are reduced.
  • Examples 10 to 13 in which the thickness of the porous nickel plating 20 embedded with nanodiamonds is 100 ⁇ m or more the thermal stress of the solder layer 4 is reduced by about 45% or more as compared with Comparative Example 1, which is more effective. Stress reduction was observed.
  • the thermal resistance of the joint portion is compared with the case where the surface of the porous nickel plating 20 is filled with nanodiamonds and the porous nickel plating does not embed nanodiamonds. It can be seen that the value can be further reduced.
  • an appropriate thermal resistance value can be obtained with the porous nickel plating having a smaller thickness. Further, the thermal stress can be further reduced by increasing the thickness of the porous nickel plating while maintaining a low thermal resistance value.
  • the lead frame 2 is subjected to the porous nickel plating 20, and the thermal conductivity is applied to the holes 7 on the surface of the porous nickel plating 20 on the solder layer 4 side.
  • the thermal conductivity is applied to the holes 7 on the surface of the porous nickel plating 20 on the solder layer 4 side.
  • the thermal strain is induced in the solder layer 4 due to the difference in the coefficient of linear expansion between the layer of the porous nickel plating 20 and the power semiconductor element 5, but since the difference is small, the thermal stress applied to the solder layer 4 is small. Become. Further, since the thermal resistance of the joint surface between the porous nickel plating 20 and the solder layer 4 is small, the thermal diffusibility at the joint surface is improved, and the joint interface between the layer of the porous nickel plating 20 and the solder layer 4 in the thermal cycle. The thermal stress concentration is relaxed.
  • the semiconductor device and the manufacturing method thereof according to the present invention have the effect of reducing the thermal stress on the solder layer and suppressing the occurrence of solder cracks while suppressing an increase in the thermal resistance of the joint, and for an electric vehicle motor. It can be used in the automobile, environment, housing, and infrastructure fields, such as inverter boards and power conditioners for power generation systems used indoors and outdoors.

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Abstract

　熱抵抗の増加を抑えつつ、はんだ層に印加される熱抵抗を低減できる、半導体装置を提供する。　半導体素子（５）と、半導体素子の少なくとも一面に配置されたはんだ層（４）と、そのはんだ層に、ポーラスニッケルめっき部（１）を挟んで配置されたリードフレーム（２）とを備える配置構造とする。半導体素子とリードフレームを直接はんだ接合する場合と比べて、はんだ接合部の熱抵抗の増加分を、ポーラスニッケルめっき部の分のみに抑えられ、はんだ層に印加される熱抵抗を低減できる。

Description

半導体装置およびその製造方法
　本発明は、半導体装置およびその製造方法に関するものである。
　パワー半導体素子を絶縁体上のリードフレームに直接接合した、パワー半導体装置が知られている。
　このような構成の従来のパワー半導体装置の、パワー半導体素子とリードフレームの接合部の構造を示した模式断面図を図１１（ａ）に示す。
　リードフレーム３０４の一方の面が、下面が放熱板３０６上に接触配置された絶縁体３０５上に固定されている。リードフレーム３０４の他方の面は、はんだ層３０２を介して、パワー半導体素子３０１に接合されている。
　このように、従来、パワー半導体素子３０１とリードフレーム３０４の接合には、はんだ３０２が使用されていた。しかし、リードフレーム３０４の線膨張係数と、パワー半導体素子３０１の線膨張係数が大きく相違していることから、パワー半導体装置を駆動させたときのパワーサイクルにより、はんだ接合部のはんだ層３０２に大きな熱応力が繰り返し印加され、最終的に、はんだクラックが発生して、接合不良となってしまう問題があった。
　一方、パワー半導体装置において、部材間の線膨張係数の差による熱応力、熱歪みを低減するために、線膨張係数の差が大きい部材間に熱伝導性ポーラス金属板を設け、熱伝導性ポーラス金属板とそれらの各部材との間をはんだ接合する構造が提案されている（例えば、特許文献１参照）。
　そこで本願の発明者は、図１１（ａ）に示す構造の従来のパワー半導体装置のはんだ接合部において、はんだ層３０２に印加される熱応力を低減するために、特許文献１で提案されている構造を適用することを考えた。
　図１１（ａ）に示した従来のパワー半導体装置に熱伝導性ポーラス金属板を設けた構成とした場合の、パワー半導体素子とリードフレームの接合部における構造を示した模式断面図を図１１（ｂ）に示す。
　線膨張係数の差が大きいパワー半導体素子３０１とリードフレーム３０４が、二つのはんだ層３０２ａおよび３０２ｂに挟まれた熱伝導性のポーラス金属板３０３に接合されている。
　ポーラス金属板３０３は、銅やアルミニウムなどの熱伝導率及び線膨張係数の大きな熱伝導性金属で構成される。
　このポーラス金属板３０３が、応力緩衝板となって、はんだ層３０２ａおよび３０２ｂに印加される熱応力を低減し、はんだクラックの発生を抑制できる。
特開２００２－２３７５５６号公報
　しかしながら、線膨張係数の差が大きいパワー半導体素子とリードフレーム間に熱伝導性ポーラス金属板を設ける構成では、熱応力を低減できるものの、パワー半導体素子とリードフレーム間の接合部の熱抵抗が大きく増加してしまう。
　すなわち、パワー半導体素子３０１とリードフレーム３０４を単純に一層のはんだ層３０２で接合する図１１（ａ）に示す従来の構成に比べて、図１１（ｂ）に示すポーラス金属板３０３を設けた構成では、ポーラス金属板３０３とはんだ層３０２ｂが加わる構造となるために、接合部の熱抵抗が大きく増加してしまう。
　本発明は、上記課題を考慮して、接合部の熱抵抗の増加を抑えつつ、はんだ層への熱応力を低減し、はんだクラックの発生を抑制できる、半導体装置およびその製造方法を提供することを目的とする。
　上述した課題を解決するために、第１の本発明は、
　半導体素子と、
　前記半導体素子の少なくとも一面に配置されたはんだ層と、
　前記はんだ層に、ポーラスニッケルめっき部を挟んで配置されたリードフレームとを備えた半導体装置である。
　また、第２の本発明は、
　前記ポーラスニッケルめっき部は、厚さが１０～１００μｍで、空孔率が２０～６０％である、第１の本発明の半導体装置である。
　また、第３の本発明は、
　前記ポーラスニッケルめっき部は、前記リードフレームに施されているものである、第１または第２の本発明の半導体装置である。
　また、第４の本発明は、
　前記ポーラスニッケルめっき部の線膨張係数は、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、第１の本発明の半導体装置である。
　また、第５の本発明は、
　前記はんだ層が配置された前記半導体素子の一面の反対側の面に配置された他のはんだ層と、
　前記他のはんだ層に、他のポーラスニッケルめっき部を挟んで配置された他のリードフレームとを備えた、第１の本発明の半導体装置である。
　また、第６の本発明は、
　前記ポーラスニッケルめっき部は、多数の空孔を有し、
　前記ポーラスニッケルめっき部の前記はんだ層と接合する面に位置する前記空孔には、ニッケルよりも高い熱伝導率を有する粒子が埋め込まれている、第１の本発明の半導体装置である。
　また、第７の本発明は、
　前記粒子が埋め込まれた前記ポーラスニッケルめっき部の線膨張係数は、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、第６の本発明の半導体装置である。
　また、第８の本発明は、
　前記空孔に埋め込まれた前記粒子は、炭素系材料の粒子である、第６または第７の本発明の半導体装置である。
　また、第９の本発明は、
　前記ポーラスニッケルめっき部は、厚さが１０～２００μｍで、空孔率が２０～６０％である、第６の本発明の半導体装置である。
　また、第１０の本発明は、
　前記空孔に埋め込まれた粒子の直径は、４～５０ｎｍである、第６の本発明の半導体装置である。
　また、第１１の本発明は、
　前記はんだ層が配置された前記半導体素子の一面の反対側の面に配置された別のはんだ層と、
　前記別のはんだ層に、多数の空孔を有する別のポーラスニッケルめっき部を挟んで配置された別のリードフレームとを備え、
　前記別のポーラスニッケルめっき部の前記別のはんだ層と接合する面に位置する前記空孔には、ニッケルよりも高い熱伝導率を有する粒子が埋め込まれている、第６の本発明の半導体装置である。
　また、第１２の本発明は、
　リードフレームにポーラスニッケルめっきを施すポーラスニッケルめっき工程と、
　前記リードフレームの前記ポーラスニッケルめっきが施された側を、はんだによって半導体素子と接合するはんだ接合工程と、を備えた半導体装置の製造方法である。
　また、第１３の本発明は、
　前記ポーラスニッケルめっき工程により前記リードフレームに施された前記ポーラスニッケルめっきの表面に位置する空孔に、ニッケルよりも高い熱伝導率を有する粒子を埋め込む、粒子埋め込み工程をさらに備えた、第１２の本発明の半導体装置の製造方法である。
　また、第１４の本発明は、
　前記ポーラスニッケルめっき工程では、前記リードフレームの前記半導体素子と接合される側の面に選択的に前記ポーラスニッケルめっきを施す、第１２または第１３の本発明の半導体装置の製造方法である。
　また、第１５の本発明は、
　第１２の本発明の半導体装置の製造方法によって製造した半導体装置は、
　前記ポーラスニッケルめっき部の線膨張係数が、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、半導体装置である。
　また、第１６の本発明は、
　第１３の本発明の半導体装置の製造方法によって製造した半導体装置は、
　前記粒子が埋め込まれた前記ポーラスニッケルめっき部の線膨張係数が、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、半導体装置である。
　ポーラスニッケルめっきを施すことにより、半導体素子とリードフレームの間に、線膨張係数と弾性率の低い層が介在することになる。これより、半導体素子が発熱して、リードフレームが大きく膨張し、めっき層に歪みが生じても、めっき層の弾性率が低いために、はんだ層に誘起される熱応力は緩和される。
　また、めっき層と、半導体素子との線膨張係数の差によって、はんだ層に熱歪みが誘起されるが、その差が小さいため、はんだ層にかかる熱応力は小さくなる。
　また、本発明の半導体装置においては、リードフレームにポーラスニッケルめっきを施して、半導体素子とはんだ接合するだけで、接合部の熱応力が低減できるため、接合に必要なはんだ層は一層で済む。これより、単純なはんだ接合部と比べて、本発明の熱抵抗の増加分は、ポーラスニッケルめっき層の分だけに抑えられる。
　本発明により、接合部の熱抵抗の増加を抑えつつ、はんだ層への熱応力を低減し、はんだクラックの発生を抑制できる、半導体装置およびその製造方法を提供できる。
本発明の実施の形態１のパワー半導体装置の配置構造を示す模式断面図 （ａ）本発明の実施の形態１のパワー半導体装置の製造工程におけるめっき工程を示す図、（ｂ）本発明の実施の形態１のパワー半導体装置の製造工程におけるリードフレーム固定工程を示す図、（ｃ）本発明の実施の形態１のパワー半導体装置の製造工程におけるはんだ接合工程を示す図 本発明の実施の形態１のポーラスニッケルめっきの模式断面図 本発明の実施の形態１の、他の構成のパワー半導体装置の配置構造を示す模式断面図 本発明の実施の形態１についての、実施例１～６、比較例１および２における、パワー半導体装置の配置構造を示す模式断面図 （ａ）本発明の実施の形態２のパワー半導体装置の配置構造を示す模式断面図、（ｂ）本発明の実施の形態２のパワー半導体装置のポーラスニッケルめっき部分の拡大断面図 （ａ）本発明の実施の形態２のパワー半導体装置の製造工程におけるめっき工程を示す図、（ｂ）本発明の実施の形態２のパワー半導体装置の製造工程におけるナノ粒子をポーラスニッケルめっきの表面の空孔に埋めこむ粒子埋め込み工程を示す図、（ｃ）本発明の実施の形態２のパワー半導体装置の製造工程におけるリードフレーム固定工程を示す図、（ｄ）本発明の実施の形態２のパワー半導体装置の製造工程におけるはんだ接合工程を示す図 （ａ）本発明の実施の形態２の、めっき工程後のポーラスニッケルめっきの模式断面図、（ｂ）本発明の実施の形態２の、粒子埋め込み工程後のポーラスニッケルめっきの模式断面図 本発明の実施の形態２の、他の構成のパワー半導体装置の配置構造を示す模式断面図 本発明の実施の形態２についての、実施例８～１３、比較例１および３における、パワー半導体装置の配置構造を示す模式断面図 （ａ）従来のパワー半導体装置における、パワー半導体素子およびリードフレーム間の接合部の模式断面図、（ｂ）従来のパワー半導体装置に熱伝導性ポーラス金属板を設けた場合の、パワー半導体素子およびリードフレーム間の接合部の模式断面図
　以下、本発明の実施の形態について図面を参照しながら説明する。
　（実施の形態１）
　図１は、本発明の実施の形態１におけるパワー半導体装置の配置構造を示す模式断面図である。
　リードフレーム２の一方の面が、下面が放熱板８上に接触配置された絶縁体３上に固定されている。ポーラスニッケルめっき１が施されたリードフレーム２の他方の面は、はんだ層４を介して、パワー半導体素子５に接合されている。
　なお、パワー半導体素子５が、本発明の半導体素子の一例にあたる。
　このパワー半導体装置の配置構造は、例えば、図２（ａ）～図２（ｃ）の工程で製造される。
　図２（ａ）～図２（ｃ）は、本実施の形態１のパワー半導体装置の製造方法の一例を示す工程図である。図２（ａ）はめっき工程を、図２（ｂ）はリードフレーム固定工程を、図２（ｃ）ははんだ接合工程を、それぞれ示している。
　まず、図２（ａ）のように、リードフレーム２にポーラスニッケルめっき１を施す。
　ポーラスニッケルめっき１は、例えば、発泡剤を入れたニッケルめっき槽６に、リードフレーム２を浸けて、電気めっきを施すことで得られる。図２（ａ）では、リードフレーム２にマスク１３を付して、パワー半導体素子５とはんだ接合される側の面のみに選択的にポーラスニッケルめっき１を施すようにしている。このとき、リードフレーム２に流す電流密度とめっき時間を調節することで、ポーラスニッケルめっき１の厚みと空孔率を制御することが出来る。
　図３は、リードフレーム２の表面に施されたポーラスニッケルめっき１の模式断面図を示している。
　なお、リードフレーム２の表面に施されたポーラスニッケルめっき１が、本発明のポーラスニッケルめっき部の一例にあたる。
　ポーラスニッケルめっき１の空孔７は高さ１０～１５μｍの針状であり、空孔率が大きくなればなるほど、空孔７の直径が大きくなる。
　ポーラスニッケルめっき１は、図２（ａ）に示すようにリードフレーム２のパワー半導体素子５とはんだ接合する部分のみに選択的に施すのに限らず、リードフレーム２の表面全体に施すようにしても良い。ただし、パワー半導体素子５と接合しない部分の熱抵抗増加を抑制するために、ポーラスニッケルめっき１は、はんだ接合する部分のみに選択的に施した方が好ましい。
　なお、ポーラスニッケルめっき１は、その線膨張係数が、リードフレーム２の線膨張係数よりも小さく、パワー半導体素子５の線膨張係数よりも大きい場合に、はんだ層４へ印加される熱応力を効果的に低減することが可能となる。ポーラスニッケルめっき１の線膨張係数は、ニッケルの線膨張係数（１２．８ｐｐｍ）に（１００－空孔率）％を乗じた値と同等と考えられる。パワー半導体素子５の線膨張係数は、４～５ｐｐｍ程度なので、ポーラスニッケルめっき１の空孔率は、６０％以下である必要がある。
　また、ポーラスニッケルめっき１の空孔率が２０％よりも小さいと、単位体積あたりの空孔数に偏りが発生し、均一な空孔率のポーラスニッケルめっき層を得ることが出来ない。
　これらより、ポーラスニッケルめっき１の空孔率は２０％～６０％であることが好ましい。
　さらに、ポーラスニッケルめっき１の空孔７の形状は、高さ１０～１５μｍの針状であることから、厚みを１０μｍよりも小さくすると、めっき厚みがバラつき、均一なポーラスニッケルめっき層を得ることが出来ない。また本実施の形態１では、厚みを１００μｍよりも厚くしようとすると、ポーラスニッケルめっき層の熱抵抗が大きくなり、また、めっき時間が長くなるため生産性が悪くなる。
　これより、本実施の形態１では、ポーラスニッケルめっき１の厚みは、１０～１００μｍであることが好ましいが、ポーラスニッケルめっき１に、ある程度の厚みを持たせることで、はんだ層４に誘起される歪みが減少し、熱応力が緩和されることから、はんだ層４への応力低減がより効果的な、２０～１００μｍとするのがより好ましい。
　なお、リードフレーム２の材質は、銅もしくはアルミが良いが、導電率と熱伝導率の高い銅の方が、より好ましい。
　また、上記では、リードフレーム２に直接ポーラスニッケルめっき１を施すこととしたが、予め別の表面処理を施したリードフレーム２に対してポーラスニッケルめっき１を施すようにしてもよい。
　次に、図２（ｂ）に示すように、ポーラスニッケルめっき１を施したリードフレーム２を絶縁樹脂９上に固定する。ここでは、絶縁体３として絶縁樹脂９を用いている。
　放熱板８の上に展開した絶縁樹脂９の上に、リードフレーム２が放熱板８に接触せず、またリードフレーム２の一方の面が絶縁樹脂９上に露出するように、ポーラスニッケルめっき１を施したリードフレーム２を置き、絶縁樹脂９を硬化して、リードフレーム２を絶縁樹脂９上に固定する。
　次に、図２（ｃ）に示すように、リードフレーム２の露出面に、クリームはんだ１０をスクリーン印刷し、その上にパワー半導体素子５を置き、本発明の配置構造を構成する。クリームはんだ１０は、本発明の配置構造を有する半導体装置を使用する環境に合わせて、適切なものを選択する。
　なお、パワー半導体素子５に、クリームはんだ１０を印刷するときは、熱抵抗の増加を抑制するために、厚みが５０～１００μｍになるように供給する。
　次に、この構造体を、リフロー炉（図示しない）に通すことで、図１に示すようなリードフレーム２とパワー半導体素子５の間の配線構造が得られる。
　本実施の形態１のパワー半導体装置の構成によれば、パワー半導体素子５とリードフレーム２の間に、線膨張係数と弾性率の低い層が介在することになる。したがって、パワー半導体素子５が発熱して、リードフレーム２が大きく膨張し、ポーラスニッケルめっき１に歪みが生じても、ポーラスニッケルめっき１の弾性率が低いために、はんだ層４に誘起される熱応力は緩和される。
　また、ポーラスニッケルめっき１とパワー半導体素子５との線膨張係数の差によって、はんだ層４に熱歪みが誘起されるが、その差が小さいため、はんだ層４にかかる熱応力は、ポーラスニッケルめっき１が介在しない場合よりも低減される。
　また、ポーラスニッケルめっき１を施したリードフレーム２を、パワー半導体素子５とはんだ接合するだけで接合部の熱応力を低減できるため、接合に必要なはんだ層４は一層で済む。これより、単純なはんだ接合部と比べて、本実施の形態１のはんだ接合部の熱抵抗の増加分は、ポーラスニッケルめっき１の分だけに抑えることが出来る。
　図４に、本実施の形態１における他の構成のパワー半導体装置の配置構造を示す模式断面図を示す。図１と同じ構成部分には、同じ符号を用いている。
　図４に示すパワー半導体装置は、パワー半導体素子５の両面にそれぞれリードフレームがはんだ接合されている。パワー半導体素子５の一面には、ポーラスニッケルめっき１を施したリードフレーム２がはんだ層４を介して接合され、パワー半導体素子５の反対側の面には、第二のポーラスニッケルめっき１２を施した第二のリードフレーム１１が第二のはんだ層１４を介して接合されている。
　第二のポーラスニッケルめっき１２を施した一端がパワー半導体素子５にはんだ接合されている第二のリードフレーム１１の他の一端は、第二のパワー半導体素子や第三のリードフレーム（図示しない）に接続されている。
　図４に示すような複数のリードフレーム２、１１が、パワー半導体素子５にはんだ接合されている配置構造においても、図１に示す配置構造と同様のはんだ層４および第二のはんだ層１４の熱応力低減効果を得ることができる。
　なお、図４における第二のはんだ層１４が、本発明の他のはんだ層の一例にあたり、第二のポーラスニッケルめっき１２が、本発明の他のポーラスニッケルめっき部の一例にあたり、第二のリードフレーム１１が、本発明の他のリードフレームの一例にあたる。
　以上より、本実施の形態１のパワー半導体装置の配置構造とすることにより、接合部の熱抵抗の増加を抑えつつ、はんだ層４への熱応力を低減し、はんだクラックの発生を抑制することが可能となる。
　なお、上記では、パワー半導体素子を備えたパワー半導体装置を例として説明したが、パワー半導体素子以外の半導体素子がリードフレームに直接接合される構成の半導体装置においても、本実施の形態１の構成を適用でき、同様の効果が得られる。
　次に、本実施の形態１についての実施例を比較例と比較することにより、本発明の効果について説明する。
　以下に、本実施の形態１の実施例をシミュレーションを用いて説明するが、本発明は、この実施例に限定されるものではない。
　シミュレーションを行うにあたり、実施例１～実施例７、比較例１および比較例２に共通する、ポーラスニッケルめっき層以外の構成部材の寸法や材料物性値は、全て同じものとした。
　図５に、本実施の形態１の実施例１～実施例７、比較例１および比較例２で使用したパワー半導体装置の配置構造を示す模式断面図を示す。
　なお、実施例１～実施例６、比較例１および比較例２では、リードフレーム２にめっきを施す際、図２（ａ）のようにマスク１３を用いてパワー半導体素子５が接合される側の面にのみめっきを施した。実施例７では、マスクを用いずにリードフレーム２の表面全体にめっきを施した。
　（実施例１）
　実施例１のパワー半導体装置は、図５に示すように、縦４ｍｍ×横６ｍｍ×厚み０．４ｍｍのパワー半導体素子５（弾性率４５０ＧＰａ、線膨張係数４．２ｐｐｍ）と、厚み１０μｍ、空孔率２０％のポーラスニッケルめっき１（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率７２．８Ｗ／（ｍ・Ｋ））が施された、縦１０ｍｍ×横１０ｍｍ×厚み１．５ｍｍのリードフレーム２（銅、弾性率１２０ＧＰａ、線膨張係数１６．６ｐｐｍ）が、縦４ｍｍ×横６ｍｍ×厚み１００μｍのはんだ層４（Ｓｎ－Ａｇ－Ｃｕ、弾性率４１．６ＧＰａ、線膨張係数２１．７ｐｐｍ、熱伝導率５５Ｗ／（ｍ・Ｋ））で接合されている。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。
　なお、ポーラスニッケルめっき１の弾性率、線膨張係数および熱伝導率は、ニッケルの弾性率（２１０ＧＰａ）、線膨張係数（１２．８ｐｐｍ）および熱伝導率（９１Ｗ／（ｍ・Ｋ））に、それぞれ（１００－空孔率）％を乗じたものとした。実施例２～実施例７のポーラスニッケルめっきの弾性率と線膨張係数も同様に定義した。
　また、ポーラスニッケルめっき１の熱抵抗とはんだ層４の熱抵抗を合計したものを、接合部の熱抵抗値として算出した。実施例２～実施例６の接合部の熱抵抗値についても同様に算出した。
　（実施例２）
　実施例２のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを１０μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率３６．４Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　（実施例３）
　実施例３のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを２０μｍ、空孔率を２０％（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率７２．８Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　（実施例４）
　実施例４のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを２０μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率３６．４Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　（実施例５）
　実施例５のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを１００μｍ、空孔率を２０％（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率７２．８Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　（実施例６）
　実施例６のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを１００μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率３６．４Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　（実施例７）
　実施例７のパワー半導体装置は、実施例１の構成のうち、厚み１０μｍ、空孔率２０％のポーラスニッケルめっき１を、パワー半導体素子５に接合する側の面だけではなく全面に施したリードフレーム２とした。したがって、図５において、リードフレーム２の上面だけではなく、下面にもポーラスニッケルめっき１が施されている。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　なお、リードフレーム２の下面は固定していないので、熱応力に関しては、上面のみにポーラスニッケルめっき１を施した実施例１と同様の値となる。
　また、熱抵抗については、リードフレーム２の上面側の熱抵抗値（ポーラスニッケルめっき１の熱抵抗とはんだ層４の熱抵抗を合計したもの）と下面側の熱抵抗値（下面側のはんだ層の熱抵抗）とを個別に算出し、上面側の熱抵抗値を接合部の熱抵抗値として算出した。
　（比較例１）
　比較例１のパワー半導体装置は、実施例１の構成において、リードフレーム２に、ポーラスニッケルめっきではなく４μｍのニッケルめっきを施して、パワー半導体素子５とリードフレーム２をはんだ接合した。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　また、はんだ層４の熱抵抗を、接合部の熱抵抗値として算出した。
　（比較例２）
　比較例２のパワー半導体装置は、実施例１の構成のうち、ポーラスニッケルめっき１の厚みを２００μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率３６．４Ｗ／（ｍ・Ｋ））とした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例１と同一である。
　また、ポーラスニッケルめっき１の熱抵抗とはんだ層４の熱抵抗を合計したものを、接合部の熱抵抗値として算出した。
　（評価）
　表１に、実施例１～実施例７、比較例１および比較例２の各はんだ層４に印加される最大熱応力と接合部の熱抵抗値を示す。
Figure JPOXMLDOC01-appb-T000001
　表１より、実施例１～実施例７において、はんだ層４に印加される熱応力は、比較例１と比べて約４～５０％低減している。また熱抵抗値は、比較例１と比べて１．１～２．５倍に抑えられている。
　パワー半導体の接合部として適切な熱抵抗値の範囲は、パワー半導体素子５の接合面の面積により変化するが、本シミュレーションで用いたパワー半導体素子５（縦４ｍｍ×横６ｍｍ）とリードフレーム２の場合におけるパワー半導体の接合部としての熱抵抗値としては、一つの接合面につき、０．２Ｋ／Ｗ以下が適切であり、０．１５Ｋ／Ｗ以下であれば、より好ましい。
　比較例２では、熱応力については４２０Ｍｐａと十分に小さいものの、熱抵抗値が０．３０６Ｋ／Ｗと大きい値になっており、パワー半導体の接合部としては適切ではない。
　なお、実施例７に示すように、パワー半導体素子５との接合面における熱抵抗値は、リードフレーム４の上面のみにポーラスニッケルめっき１を施した場合（実施例１）と同じである。したがって、実施例２～実施例６と同一の厚みのポーラスニッケルめっき１をリードフレーム２の全面に施した場合、それぞれ実施例２～実施例６における熱抵抗値と同一の値が得られる。
　また、ポーラスニッケルめっき１の厚みが１０μｍである実施例１、２および７では、熱応力の低減は比較例１と比べて５％以下であるが、ポーラスニッケルめっき１の厚みが２０μｍ以上である実施例３～実施例６では、はんだ層４の熱応力は、比較例１と比べて約１０％以上低減しており、より効果的な応力低減が見られた。
　（実施の形態２）
　図６（ａ）は、本発明の実施の形態２におけるパワー半導体装置の配置構造を示す模式断面図である。
　なお、実施の形態２で用いる図６～図１０では、実施の形態１で用いた図１～図５と同じ構成部分については、同じ符号を用いている。
　リードフレーム２の一方の面が、下面が放熱板８上に接触配置された絶縁体３上に固定されている。ポーラスニッケルめっき２０が施されたリードフレーム２の他方の面は、はんだ層４を介して、パワー半導体素子５に接合されている。
　図６（ｂ）は、図６（ａ）の破線の円形で囲んだ、ポーラスニッケルめっき２０部分の拡大断面図を示している。
　図６（ｂ）に示すように、ポーラスニッケルめっき２０は、はんだ層４と接合する側の表面に位置している空孔７内に、熱伝導率の高いナノ粒子１７が埋め込まれている。
　本実施の形態２では、ポーラスニッケルめっき２０の空孔７内にナノ粒子１７が埋め込まれている点が、空孔７内にナノ粒子１７が埋め込まれていない実施の形態１のポーラスニッケルめっき１と異なっている。
　なお、ナノ粒子１７が、本発明の、はんだ層と接合する面に位置する空孔に埋め込まれている、ニッケルよりも高い熱伝導率を有する粒子の一例にあたる。
　このパワー半導体装置の配置構造は、例えば、図７（ａ）～（ｄ）の工程で製造される。
　図７（ａ）～（ｄ）は、本実施の形態２のパワー半導体装置の製造方法の一例を示す工程図である。図７（ａ）はめっき工程を、図７（ｂ）はナノ粒子１７をポーラスニッケルめっき２０の表面の空孔７に埋め込む粒子埋め込み工程を、図７（ｃ）はリードフレーム固定工程を、図７（ｄ）ははんだ接合工程を、それぞれ示している。
　まず、図７（ａ）のように、リードフレーム２にポーラスニッケルめっき２０を施す。
　ポーラスニッケルめっき２０は、例えば、発泡剤を入れたニッケルめっき槽６に、リードフレーム２を浸けて、電気めっきを施すことで得られる。図７（ａ）では、リードフレーム２にマスク１３を付して、パワー半導体素子５とはんだ接合される側の面のみに選択的にポーラスニッケルめっき２０を施すようにしている。このとき、リードフレーム２に流す電流密度とめっき時間を調節することで、ポーラスニッケルめっき２０の厚みと空孔率を制御することができる。
　図８（ａ）は、図７（ａ）のめっき工程を実施した後の、リードフレーム２の表面に施されたポーラスニッケルめっき２０の模式断面図を示している。
　ポーラスニッケルめっき２０の空孔７は高さ１０～１５μｍの針状であり、空孔率が大きくなればなるほど、空孔７の直径が大きくなる。
　ポーラスニッケルめっき２０は、図７（ａ）に示すようにリードフレーム２のパワー半導体素子５とはんだ接合する部分のみに選択的に施すのに限らず、リードフレーム２の表面全体に施すようにしても良い。ただし、パワー半導体素子５と接合しない部分の熱抵抗増加を抑制するために、ポーラスニッケルめっき２０は、はんだ接合する部分のみに選択的に施した方が好ましい。
　なお、ポーラスニッケルめっき２０は、その線膨張係数が、リードフレーム２の線膨張係数よりも小さく、パワー半導体素子５の線膨張係数よりも大きい場合に、はんだ層４へ印加される熱応力を効果的に低減することが可能となる。ポーラスニッケルめっき２０の線膨張係数は、ニッケルの線膨張係数（１２．８ｐｐｍ）に（１００－空孔率）％を乗じた値と同等と考えられる。パワー半導体素子５の線膨張係数は、４～５ｐｐｍ程度なので、ポーラスニッケルめっき２０の空孔率は、６０％以下である必要がある。
　また、ポーラスニッケルめっき２０の空孔率が２０％よりも小さいと、単位体積あたりの空孔数に偏りが発生し、均一な空孔率のポーラスニッケルめっき層を得ることができない。
　これらより、ポーラスニッケルめっき２０の空孔率は２０％～６０％であることが好ましい。
　さらに、ポーラスニッケルめっき２０の空孔７の形状は、高さ１０～１５μｍの針状であることから、厚みを１０μｍよりも小さくすると、めっき厚みがバラつき、均一なポーラスニッケルめっき層を得ることができない。また本実施の形態２では、厚みを２００μｍよりも厚くしようとすると、ポーラスニッケルめっき層の熱抵抗が大きくなり、また、めっき時間がより一層長くなるため生産性が悪くなる。
　これより、本実施の形態２では、ポーラスニッケルめっき２０の厚みは、１０～２００μｍであることが好ましいが、ポーラスニッケルめっき２０に、ある程度の厚みを持たせることで、はんだ層４に誘起される歪みが減少し、熱応力が緩和されることから、はんだ層４への応力低減がより効果的な、２０～２００μｍとするのがより好ましい。
　なお、リードフレーム２の材質は、銅もしくはアルミが良いが、導電率と熱伝導率の高い銅の方が、より好ましい。
　また、上記では、リードフレーム２に直接ポーラスニッケルめっき２０を施すこととしたが、予め別の表面処理を施したリードフレーム２に対してポーラスニッケルめっき２０を施すようにしてもよい。
　次に、図７（ｂ）に示すように、リードフレーム２に施したポーラスニッケルめっき２０の表面の空孔７にナノ粒子１７を埋め込む。
　ポーラスニッケルめっき２０の表面にナノ粒子１７を埋めこむ方法としては、例えば、ナノ粒子１７を一定分散させた溶液１６が入った超音波洗浄槽１５に、リードフレーム２を浸けて、超音波振動を施す方法がある。ナノ粒子１７を一定分散させる溶液１６として、表面張力の小さい、例えばエタノールの水溶液などを用いる。ナノ粒子１７を分散させた混合溶液１６の濃度と超音波振動を施す時間を調整することによって、ポーラスニッケルめっき２０の表面の空孔７に均一な密度で、ナノ粒子１７を導入することができる。
　そして、ポーラスニッケルめっき２０の表面にナノ粒子１７を入れたリードフレーム２は、例えば、減圧または微加熱することにより、溶剤を蒸発させる。
　図８（ｂ）は、図７（ｂ）の粒子埋め込み工程を実施した後の、リードフレーム２の表面に施されたポーラスニッケルめっき２０の模式断面図を示している。
　このようにしてリードフレーム２の表面に施されたポーラスニッケルめっき２０が、本発明のポーラスニッケルめっき部の一例にあたる。
　ナノ粒子１７の熱伝導率は、ニッケルの熱伝導率（約９０．５Ｗ／（ｍ・Ｋ））よりも高くなければ、接合部の熱抵抗を効果的に低減できない。これより、ナノ粒子１７の材質は、９１Ｗ／（ｍ・Ｋ）以上の熱伝導率であることが好ましい。ナノ粒子１７の材質は炭素系材料（ダイヤモンド、カーボンナノチューブ、グラファイトなど）が好ましいが、その中でも熱伝導率の高いダイヤモンド（約２０００Ｗ／（ｍ・Ｋ））がより好ましい。
　なお、ポーラスニッケルめっき２０の表面の空孔７には、小さいサイズのナノ粒子１７を埋め込んだ方が、粒子と粒子、粒子とポーラスニッケルめっき２０の間の接触面積が大きくなり、熱抵抗をより低減させることができる。これにより、ナノ粒子１７のサイズは、５０ｎｍ以下が好ましい。５０ｎｍより大きいと、ポーラスニッケルめっき２０との接触面積が小さくなり、効率的に熱を伝導することができなくなる。
　しかし、ナノ粒子１７が４ｎｍより小さいと、拡散されたナノ粒子は非常に軽いため超音波振動による制御が難しく、ポーラスニッケルめっき２０の空孔７に入りにくいので、ナノ粒子１７は４ｎｍより大きいのが好ましい。
　ナノ粒子１７は、ポーラスニッケルめっき２０の表面の空孔７に粒子のままの状態で一定の密度で入っているので、ポーラスニッケルめっき２０の応力緩和効果には影響しない。したがって、表面の空孔７にナノ粒子１７を埋め込んだポーラスニッケルめっき２０は、表面の空孔７にナノ粒子１７を加えてないポーラスニッケルめっきの弾性率、線膨張係数と同等である。
　なお、熱伝導率の高いナノ粒子１７は、ポーラスニッケルめっき２０の表面の空孔７に一定の密度で詰まって入っているので、ポーラスニッケルめっき２０と十分な接触面積を持つことにより、ポーラスニッケルめっき２０からの熱を迅速に逃がすことができる。
　次に、図７（ｃ）に示すように、ポーラスニッケルめっき２０を施し、ポーラスニッケルめっき２０表面にナノ粒子１７を埋め込んだリードフレーム２を絶縁樹脂９上に固定する。ここでは、絶縁体３として絶縁樹脂９を用いている。
　放熱板８の上に展開した絶縁樹脂９の上に、リードフレーム２が放熱板８に接触せず、またリードフレーム２の一方の面が絶縁樹脂９上に露出するように、表面にナノ粒子１７を埋め込んだポーラスニッケルめっき２０を施したリードフレーム２を置き、絶縁樹脂９を硬化して、リードフレーム２を絶縁樹脂９上に固定する。
　次に、図７（ｄ）に示すように、リードフレーム２の露出面に、クリームはんだ１０をスクリーン印刷し、その上にパワー半導体素子５を置き、本発明の配置構造を構成する。クリームはんだ１０は、本発明の配置構造を有するパワー半導体装置を使用する環境に合わせて、適切なものを選択する。
　なお、パワー半導体素子５に、クリームはんだ１０を印刷するときは、厚みが５０～１００μｍになるように供給する。はんだ層の厚みが５０μｍ以下の場合は、パワー半導体素子５とポーラスニッケルめっき２０との接合強度の低下が発生し、１００μｍより厚い場合は熱抵抗が増加するため、はんだ層の厚みが５０～１００μｍになるようにクリームはんだ１０を供給する。
　次に、この構造体を、リフロー炉（図示しない）に通すことで、図６（ａ）に示すようなリードフレーム２とパワー半導体素子５の間の配線構造が得られる。
　本実施の形態２の半導体装置の構成によれば、パワー半導体素子５とリードフレーム２の間に、線膨張係数と弾性率の低い層が介在することになる。したがって、パワー半導体素子５が発熱して、リードフレーム２が大きく膨張し、ナノ粒子１７を埋め込んだポーラスニッケルめっき２０に歪みが生じても、弾性率が低いために、はんだ層４に誘起される熱応力は緩和される。
　また、ナノ粒子１７を埋め込んだポーラスニッケルめっき２０とパワー半導体素子５との線膨張係数の差によって、はんだ層４に熱歪みが誘起されるが、その差が小さいため、はんだ層４にかかる熱応力は、ナノ粒子１７を埋め込んだポーラスニッケルめっき２０が介在しない場合よりも低減される。
　また、表面の空孔７にナノ粒子１７を埋め込んだポーラスニッケルめっき２０を施したリードフレーム２を、パワー半導体素子５とはんだ接合するだけで接合部の熱応力を低減できるため、接合に必要なはんだ層４は一層で済む。これより、単純なはんだ接合部と比べて、本実施の形態２のはんだ接合部の熱抵抗の増加分は、ポーラスニッケルめっき２０の分だけに抑えることができる。さらに、ポーラスニッケルめっき２０の表面の空孔７に熱伝導率の高いナノ粒子１７を埋め込んでいるので、ポーラスニッケルめっき２０による熱抵抗の増加分を、より小さく抑えることができる。
　図９に、本実施の形態２における他の構成のパワー半導体装置の配置構造を示す模式断面図を示す。図６と同じ構成部分には、同じ符号を用いている。
　図９に示すパワー半導体装置は、パワー半導体素子５の両面にそれぞれリードフレームがはんだ接合されている。パワー半導体素子５の一面には、ポーラスニッケルめっき２０を施したリードフレーム２がはんだ層４を介して接合され、パワー半導体素子５の反対側の面には、第二のポーラスニッケルめっき２１を施した第二のリードフレーム１１が第二のはんだ層１４を介して接合されている。
　ポーラスニッケルめっき２０のはんだ層４が接合される側の表面に位置する空孔７には、図６（ｂ）に示すようにナノ粒子１７が埋め込まれている。同様に、第二のポーラスニッケルめっき２１の第二のはんだ層１４が接合される側の表面に位置する空孔にもナノ粒子が埋め込まれている。
　表面にナノ粒子を埋め込んだ第二のポーラスニッケルめっき２１を施した一端がパワー半導体素子５にはんだ接合されている第二のリードフレーム１１の他の一端は、第二のパワー半導体素子や第三のリードフレーム（図示しない）に接続されている。
　図９に示すような複数のリードフレーム２、１１が、パワー半導体素子５にはんだ接合されている配置構造においても、図６（ａ）に示す配置構造と同様のはんだ層４および第二のはんだ層１４の熱応力低減効果を得ることができる。
　なお、図９における第二のはんだ層１４が、本発明の別のはんだ層の一例にあたり、表面の空孔にナノ粒子を埋め込んだ第二のポーラスニッケルめっき２１が、本発明の多数の空孔を有する別のポーラスニッケルめっき部の一例にあたり、第二のリードフレーム１１が、本発明の別のリードフレームの一例にあたる。
　以上より、本実施の形態２のパワー半導体装置の配置構造とすることにより、接合部の熱抵抗の増加を抑えつつ、はんだ層４への熱応力を低減し、はんだクラックの発生を抑制することが可能となる。
　なお、上記では、パワー半導体素子を備えたパワー半導体装置を例として説明したが、パワー半導体素子以外の半導体素子がリードフレームに直接接合される構成の半導体装置においても、本実施の形態２の構成を適用でき、同様の効果が得られる。
　次に、本実施の形態２についての実施例を比較例と比較することにより、本発明の効果について説明する。
　以下に、本実施の形態２の実施例をシミュレーションを用いて説明するが、本発明は、この実施例に限定されるものではない。
　シミュレーションを行うにあたり、実施例８～実施例１３、比較例１および比較例３に共通する、ポーラスニッケルめっき層以外の構成部材の寸法や材料物性値は、全て同じものとした。
　図１０に、本実施の形態２の実施例８～実施例１３、比較例１および比較例３で使用したパワー半導体装置の配置構造を示す模式断面図を示す。
　なお、実施例８～実施例１３、比較例１および比較例３では、リードフレーム２にめっきを施す際、図７（ａ）のようにマスク１３を用いてパワー半導体素子５が接合される側の面にのみめっきを施した。
　（実施例８）
　実施例８のパワー半導体装置は、図１０に示すように、縦４ｍｍ×横６ｍｍ×厚み０．４ｍｍのパワー半導体素子５（弾性率４５０ＧＰａ、線膨張係数４．２ｐｐｍ）と、厚み２０μｍ、空孔率２０％のポーラスニッケルめっき２０（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率１７２．８Ｗ／（ｍ・Ｋ））が施された、縦１０ｍｍ×横１０ｍｍ×厚み１．５ｍｍのリードフレーム２（銅、弾性率１２０ＧＰａ、線膨張係数１６．６ｐｐｍ）が、縦４ｍｍ×横６ｍｍ×厚み１００μｍのはんだ層４（Ｓｎ－Ａｇ－Ｃｕ、弾性率４１．６ＧＰａ、線膨張係数２１．７ｐｐｍ、熱伝導率５５Ｗ／（ｍ・Ｋ））で接合されている。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。
　なお、表面の空孔７にナノ粒子１７を埋め込んだポーラスニッケルめっき２０の弾性率、線膨張係数は、ニッケルの弾性率（２１０ＧＰａ）、線膨張係数（１２．８ｐｐｍ）に、それぞれ（１００－空孔率）％を乗じたものとした。実施例９～実施例１３のポーラスニッケルめっきの弾性率と線膨張係数も同様に定義した。
　また、表面の空孔７にナノ粒子１７を埋め込んだポーラスニッケルめっき２０の熱伝導率は、ニッケルの熱伝導率（９１Ｗ／（ｍ・Ｋ））に（１００－空孔率）％を乗じたものに、ナノダイヤ（熱伝導率２０００Ｗ／（ｍ・Ｋ））の熱伝導率に（ナノ粒子の厚み/ポーラスニッケルめっき厚み）×空孔率）％を乗じたものを足したものとした。実施例９～実施例１３のポーラスニッケルめっきの熱伝導率も同様に定義した。
　また、表面の空孔にナノダイヤを埋め込んだポーラスニッケルめっき２０の熱抵抗とはんだ層４の熱抵抗を合計したものを、接合部の熱抵抗値として算出した。実施例９～実施例１３の接合部の熱抵抗値についても同様に算出した。
　（実施例９）
　実施例９のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを２０μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率３３６．４Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　（実施例１０）
　実施例１０のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを１００μｍ、空孔率を２０％（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率９２．８Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　（実施例１１）
　実施例１１のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを１００μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率９６．４Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　（実施例１２）
　実施例１２のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを２００μｍ、空孔率を２０％（弾性率１６８ＧＰａ、線膨張係数１０．２ｐｐｍ、熱伝導率８２．８Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　（実施例１３）
　実施例１３のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを２００μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率６６．４Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　（比較例１）
　比較例１のパワー半導体装置は、実施例８の構成において、リードフレーム２に、表面の空孔にナノダイヤを埋め込んだポーラスニッケルめっき２０ではなく４μｍのニッケルめっきを施して、パワー半導体素子５とリードフレーム２をはんだ接合した。この比較例１の構成は、実施の形態１で比較例として用いた比較例１と同じ構成である。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　また、はんだ層４の熱抵抗を、接合部の熱抵抗値として算出した。
　（比較例３）
　比較例３のパワー半導体装置は、実施例８の構成のうち、ポーラスニッケルめっき２０の厚みを３００μｍ、空孔率を６０％（弾性率８４ＧＰａ、線膨張係数５．１ｐｐｍ、熱伝導率５６．４Ｗ／（ｍ・Ｋ））とした。ポーラスニッケルめっき２０の表面の空孔７にはナノ粒子１７（ナノダイヤ：熱伝導率２０００Ｗ／（ｍ・Ｋ））が埋め込まれており、その厚みを５μｍとした。
　このパワー半導体装置のパワー半導体素子５とリードフレーム２間の配線構造において、構成部材の温度が、２００℃から－４０℃まで変化したときの、はんだ層４に印加される熱応力を、線形構造解析（ＦＥＭ）による計算によって求めた。その他の構成は、実施例８と同一である。
　また、表面の空孔にナノダイヤを埋め込んだポーラスニッケルめっき２０の熱抵抗とはんだ層４の熱抵抗を合計したものを、接合部の熱抵抗値として算出した。
　（評価）
　表２に、実施例８～実施例１３、比較例１および比較例３の各はんだ層４に印加される最大熱応力と接合部の熱抵抗値を示す。
　なお、参考として、実施例８～実施例１１および実施例１３については、各構成においてナノダイヤを埋め込んでいないポーラスニッケルめっき２０とした場合の熱抵抗値も表２に記載した。
Figure JPOXMLDOC01-appb-T000002
　表２より、実施例８～実施例１３において、はんだ層４に印加される熱応力は、比較例１と比べて約９～６０％低減している。また熱抵抗値は、比較例１と比べて１．０～２．６倍に抑えられている。
　パワー半導体の接合部として適切な熱抵抗値の範囲は、パワー半導体素子５の接合面の面積により変化するが、本シミュレーションで用いたパワー半導体素子５（縦４ｍｍ×横６ｍｍ）とリードフレーム２の場合におけるパワー半導体の接合部としての熱抵抗値としては、一つの接合面につき、０．２Ｋ／Ｗ以下が適切であり、０．１５Ｋ／Ｗ以下であれば、より好ましい。
　比較例３では、熱応力については４０３Ｍｐａと十分に小さいものの、熱抵抗値が０．２９８Ｋ／Ｗと大きい値になっており、パワー半導体の接合部としては適切ではない。
　また、表面の空孔にナノダイヤを埋め込んだポーラスニッケルめっき２０の厚みが２０μｍである実施例８、９では、熱応力の低減は比較例１と比べて１０％以下であるが、表面の空孔にナノダイヤを埋め込んだポーラスニッケルめっき２０の厚みが１００μｍ以上である実施例１０～実施例１３では、はんだ層４の熱応力は、比較例１と比べて約４５％以上低減しており、より効果的な応力低減が見られた。
　また、表２より、実施例８～実施例１３に示す構成において、ポーラスニッケルめっき２０の表面にナノダイヤを埋め込むことにより、ナノダイヤを埋め込まないポーラスニッケルめっきとした場合に比べて、接合部の熱抵抗値をより低減できることがわかる。
　したがって、ポーラスニッケルめっきにナノダイヤを埋め込むことにより、より厚みの小さいポーラスニッケルめっきで適切な熱抵抗値を得ることができる。また、低い熱抵抗値を維持しながらポーラスニッケルめっきの厚さを大きくして、さらに熱応力を低減させることができる。
　以上に説明したように、本実施の形態２のパワー半導体装置は、リードフレーム２にポーラスニッケルめっき２０を施し、さらにポーラスニッケルめっき２０のはんだ層４側の表面の空孔７に、熱伝導率の高いナノ粒子１７を埋め込むことにより、パワー半導体素子５とリードフレーム２の間に、線膨張係数と弾性率が低く、局所的に熱抵抗が小さい層が介在することになる。これより、パワー半導体素子５が発熱して、リードフレーム２が大きく膨張し、ポーラスニッケルめっき２０の層に歪みが生じても、ポーラスニッケルめっき２０の弾性率が低いために、はんだ層４に誘起される熱応力は緩和される。
　また、ポーラスニッケルめっき２０の層と、パワー半導体素子５との線膨張係数の差によって、はんだ層４に熱歪みが誘起されるが、その差が小さいため、はんだ層４にかかる熱応力は小さくなる。さらに、ポーラスニッケルめっき２０とはんだ層４との接合面の熱抵抗が小さいため、その接合面での熱拡散性が向上し、熱サイクルにおける、ポーラスニッケルめっき２０の層とはんだ層４の接合界面の熱応力集中は緩和される。
　本発明にかかる半導体装置およびその製造方法は、接合部の熱抵抗の増加を抑えつつ、はんだ層への熱応力を低減し、はんだクラックの発生を抑制できる効果を有し、電気自動車のモーター用インバーター基板や、屋内外で使用する発電システムのパワーコンディショナーなど、自動車、環境、住宅、インフラ分野へ利用することが出来る。
　１、２０　ポーラスニッケルめっき
　２　リードフレーム
　３　絶縁体
　４　はんだ層
　５　パワー半導体素子
　６　ニッケルめっき槽
　７　空孔
　８　放熱板
　９　絶縁樹脂
　１０　クリームはんだ
　１１　第二のリードフレーム
　１２、２１　第二のポーラスニッケルめっき
　１３　マスク
　１４　第二のはんだ層
　３０１　パワー半導体素子
　３０２、３０２ａ、３０２ｂ　はんだ層
　３０３　ポーラス金属板
　３０４　リードフレーム
　３０５　絶縁体
　３０６　放熱板

Claims (16)

  1. 　半導体素子と、
    　前記半導体素子の少なくとも一面に配置されたはんだ層と、
    　前記はんだ層に、ポーラスニッケルめっき部を挟んで配置されたリードフレームとを備えた半導体装置。
  2. 　前記ポーラスニッケルめっき部は、厚さが１０～１００μｍで、空孔率が２０～６０％である、請求項１に記載の半導体装置。
  3. 　前記ポーラスニッケルめっき部は、前記リードフレームに施されているものである、請求項１または２に記載の半導体装置。
  4. 　前記ポーラスニッケルめっき部の線膨張係数は、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、請求項１に記載の半導体装置。
  5. 　前記はんだ層が配置された前記半導体素子の一面の反対側の面に配置された他のはんだ層と、
    　前記他のはんだ層に、他のポーラスニッケルめっき部を挟んで配置された他のリードフレームとを備えた、請求項１に記載の半導体装置。
  6. 　前記ポーラスニッケルめっき部は、多数の空孔を有し、
    　前記ポーラスニッケルめっき部の前記はんだ層と接合する面に位置する前記空孔には、ニッケルよりも高い熱伝導率を有する粒子が埋め込まれている、請求項１に記載の半導体装置。
  7. 　前記粒子が埋め込まれた前記ポーラスニッケルめっき部の線膨張係数は、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、請求項６に記載の半導体装置。
  8. 　前記空孔に埋め込まれた前記粒子は、炭素系材料の粒子である、請求項６または７に記載の半導体装置。
  9. 　前記ポーラスニッケルめっき部は、厚さが１０～２００μｍで、空孔率が２０～６０％である、請求項６に記載の半導体装置。
  10. 　前記空孔に埋め込まれた粒子の直径は、４～５０ｎｍである、請求項６に記載の半導体装置。
  11. 　前記はんだ層が配置された前記半導体素子の一面の反対側の面に配置された別のはんだ層と、
    　前記別のはんだ層に、多数の空孔を有する別のポーラスニッケルめっき部を挟んで配置された別のリードフレームとを備え、
    　前記別のポーラスニッケルめっき部の前記別のはんだ層と接合する面に位置する前記空孔には、ニッケルよりも高い熱伝導率を有する粒子が埋め込まれている、請求項６に記載の半導体装置。
  12. 　リードフレームにポーラスニッケルめっきを施すポーラスニッケルめっき工程と、
    　前記リードフレームの前記ポーラスニッケルめっきが施された側を、はんだによって半導体素子と接合するはんだ接合工程と、を備えた半導体装置の製造方法。
  13. 　前記ポーラスニッケルめっき工程により前記リードフレームに施された前記ポーラスニッケルめっきの表面に位置する空孔に、ニッケルよりも高い熱伝導率を有する粒子を埋め込む、粒子埋め込み工程をさらに備えた、請求項１２に記載の半導体装置の製造方法。
  14. 　前記ポーラスニッケルめっき工程では、前記リードフレームの前記半導体素子と接合される側の面に選択的に前記ポーラスニッケルめっきを施す、請求項１２または１３に記載の半導体装置の製造方法。
  15. 　請求項１２に記載の半導体装置の製造方法によって製造した半導体装置は、
    　前記ポーラスニッケルめっき部の線膨張係数が、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、半導体装置。
  16. 　請求項１３に記載の半導体装置の製造方法によって製造した半導体装置は、
    　前記粒子が埋め込まれた前記ポーラスニッケルめっき部の線膨張係数が、前記半導体素子の線膨張係数よりも大きく、前記リードフレームの線膨張係数よりも小さい、半導体装置。
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