JP6418126B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6418126B2 JP6418126B2 JP2015201381A JP2015201381A JP6418126B2 JP 6418126 B2 JP6418126 B2 JP 6418126B2 JP 2015201381 A JP2015201381 A JP 2015201381A JP 2015201381 A JP2015201381 A JP 2015201381A JP 6418126 B2 JP6418126 B2 JP 6418126B2
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Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。絶縁基板1上に純アルミ又は合金アルミ材からなるアルミパターン2が形成されている。アルミパターン2の表面にめっき3a,3bが形成されている。めっき3a,3bは互いに横並びに配置されている。めっき3a,3bはニッケルめっきであり、その厚みは10μm以上である。
図6は、本発明の実施の形態2に係る半導体装置を示す断面図である。本実施の形態では、めっき3aは、下層膜10aと、下層膜10a上に形成された上層膜11aとを有する多層膜である。同様に、めっき3bは、下層膜10bと、下層膜10b上に形成された上層膜11bとを有する多層膜である。下層膜10a,10bは、上層膜11a,11bよりも剛性が高く、変形しにくいニッケルなどである。上層膜11a,11bは、下層膜10a,10bよりもはんだ5に対する濡れ性が高い金などである。これにより、強度を保って信頼性を向上させ、かつ、はんだ5の濡れ性が向上してボイド等も減ることでアセンブリ性を向上させることもできる。
図7は、本発明の実施の形態3に係る半導体装置を示す断面図である。本実施の形態では、半導体素子4aは半導体素子4bより薄い。そこで、めっき3aをめっき3bより厚くする。これにより、IGBTとダイオードなど厚みが異なる半導体素子4a,4bを搭載する場合に、はんだ5の厚みを調整することなく半導体素子4a,4bの上面の高さを揃えることができる。このため、半導体素子4a,4b上への電極接合等が容易になり、アセンブリ性が向上する。また、はんだ5の厚みを統一できるため、誤搭載を防止し、同一仕様の購入により単価を低下できる。
図8は、本発明の実施の形態4に係る半導体装置を示す断面図である。本実施の形態では、めっき3a,3bの厚みは半導体素子4a,4bの直下において変化する。これにより、変形が大きくなる半導体素子4a,4bの中央部直下のめっき3a,3bを厚くし、半導体素子4a,4bの変形を抑制することができる。また、その箇所のはんだ5の厚みを薄くすることができるため、熱抵抗が低減する。
図11は、本発明の実施の形態5に係る半導体装置を示す断面図である。図12及び図13は、本発明の実施の形態5に係る半導体装置の一部を拡大した上面図である。アルミパターン2の上面において半導体素子4a,4bの周囲に溝12が設けられている。図12のように半導体素子4a,4bの周囲全体に溝12が設けられていてもよいし、図13のように周囲の一部に溝12が設けられていてもよい。これにより、アルミパターン2の溝12より外周からの変形を溝12で抑えることができる。また、溝12によりはんだ流れを抑制することができ、アセンブリ性も向上できる。また、封止材9の密着性も向上する。
Claims (6)
- 絶縁基板と、
前記絶縁基板上に形成された純アルミ又は合金アルミ材からなるアルミパターンと、
前記アルミパターンの表面に形成されためっきと、
前記めっき上に接合された半導体素子とを備え、
前記めっきの厚みは10μm以上であり、
前記めっきは、互いに横並びに配置された第1及び第2のめっきを有し、
前記半導体素子は、前記第1及び第2のめっき上にそれぞれ接合された第1及び第2の半導体素子を有し、
前記第1の半導体素子は前記第2の半導体素子より薄く、
前記第1のめっきは前記第2のめっきより厚いことを特徴とする半導体装置。 - 前記半導体素子を前記めっきに接合するはんだを更に備え、
前記めっきは、下層膜と、前記下層膜上に形成された上層膜とを有し、
前記下層膜は前記上層膜よりも剛性が高く、
前記上層膜は前記下層膜よりも前記はんだに対する濡れ性が高いことを特徴とする請求項1に記載の半導体装置。 - 前記めっきの厚みは前記半導体素子の直下において変化することを特徴とする請求項1又は2に記載の半導体装置。
- 前記アルミパターンの上面において前記半導体素子の周囲又は周囲の一部に溝が設けられていることを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 前記アルミパターンの表面には全面的又は部分的に加工硬化が施されていることを特徴とする請求項1〜4の何れか1項に記載の半導体装置。
- 前記半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1〜5の何れか1項に記載の半導体装置。
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JP2015201381A JP6418126B2 (ja) | 2015-10-09 | 2015-10-09 | 半導体装置 |
US15/173,742 US20170103960A1 (en) | 2015-10-09 | 2016-06-06 | Semiconductor device |
DE102016214155.4A DE102016214155B4 (de) | 2015-10-09 | 2016-08-01 | Halbleiteranordnung |
CN201610881663.8A CN107104080A (zh) | 2015-10-09 | 2016-10-09 | 半导体装置 |
US16/107,966 US10658324B2 (en) | 2015-10-09 | 2018-08-21 | Semiconductor device |
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JP7187664B2 (ja) * | 2019-03-08 | 2022-12-12 | 京セラ株式会社 | 接合体および光源装置 |
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US20170103960A1 (en) | 2017-04-13 |
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