JP6418126B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6418126B2
JP6418126B2 JP2015201381A JP2015201381A JP6418126B2 JP 6418126 B2 JP6418126 B2 JP 6418126B2 JP 2015201381 A JP2015201381 A JP 2015201381A JP 2015201381 A JP2015201381 A JP 2015201381A JP 6418126 B2 JP6418126 B2 JP 6418126B2
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Prior art keywords
plating
semiconductor device
semiconductor
semiconductor element
layer film
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JP2015201381A
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JP2017073529A (ja
Inventor
大輔 村田
大輔 村田
井本　裕児
裕児 井本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2015201381A priority Critical patent/JP6418126B2/ja
Priority to US15/173,742 priority patent/US20170103960A1/en
Priority to DE102016214155.4A priority patent/DE102016214155B4/de
Priority to CN201610881663.8A priority patent/CN107104080A/zh
Publication of JP2017073529A publication Critical patent/JP2017073529A/ja
Priority to US16/107,966 priority patent/US10658324B2/en
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Publication of JP6418126B2 publication Critical patent/JP6418126B2/ja
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Description

本発明は、絶縁基板上のアルミパターンの表面にめっきが形成され、めっき上に半導体素子が接合された半導体装置に関する。
電気モーターを動力とする自動車又は電車において、モーターを制御するインバータ又は回生コンバータとして半導体装置が使用されている。このような半導体装置において、絶縁基板上のアルミパターンの表面にめっきが形成され、めっき上に半導体素子が接合されている。従来の半導体装置では、めっきは接合に必要な最低限の３〜５μｍ程度であり、熱抵抗等の関係からめっき厚は薄い方が良いと考えられていた（例えば、特許文献１参照）。
特開平７−１２２６７８号公報
半導体素子が動作して発熱して温度スイングが発生すると、アルミパターンと絶縁基板の線膨張係数差が大きいため、熱応力が発生する。従って、塑性変形しやすいアルミパターンは熱応力により変形する。従来のような３〜５μｍ程度のめっき厚だと、この変形の影響がめっき及びはんだを通じて半導体素子へ伝わって半導体素子も変形する。これにより、半導体素子の特性変動が生じ、半導体素子が破壊に至る場合もある。半導体素子が薄くなるほど、素子にかかる応力は増加するため、特に対策が必要となる。
本発明は、上述のような課題を解決するためになされたもので、その目的は特性変動を防ぎ、信頼性を向上させることができる半導体装置を得るものである。
本発明に係る半導体装置は、絶縁基板と、前記絶縁基板上に形成された純アルミ又は合金アルミ材からなるアルミパターンと、前記アルミパターンの表面に形成されためっきと、前記めっき上に接合された半導体素子とを備え、前記めっきの厚みは１０μｍ以上であり、前記めっきは、互いに横並びに配置された第１及び第２のめっきを有し、前記半導体素子は、前記第１及び第２のめっき上にそれぞれ接合された第１及び第２の半導体素子を有し、前記第１の半導体素子は前記第２の半導体素子より薄く、前記第１のめっきは前記第２のめっきより厚いことを特徴とする。
本発明では、めっきの厚みを１０μｍ以上にする。これにより、熱応力により変形したアルミパターンの影響を半導体素子が受け難くなる。従って、半導体素子の変形による特性変動を防ぎ、半導体素子の破壊に対する信頼性（パワーサイクル）を向上させることができる。
本発明の実施の形態１に係る半導体装置を示す断面図である。 めっきの硬度を測定した結果を示す図である。 従来のめっき厚みのアルミパターンの塑性変形ひずみを示す図である。 めっき厚み１０μｍのアルミパターンの塑性変形ひずみを示す図である。 パワーサイクル数に対する累積欠陥率を示す図である。 本発明の実施の形態２に係る半導体装置を示す断面図である。 本発明の実施の形態３に係る半導体装置を示す断面図である。 本発明の実施の形態４に係る半導体装置を示す断面図である。 本発明の実施の形態４に係る半導体装置の変形例を示す断面図である。 本発明の実施の形態４に係る半導体装置の変形例を示す断面図である。 本発明の実施の形態５に係る半導体装置を示す断面図である。 本発明の実施の形態５に係る半導体装置の一部を拡大した上面図である。 本発明の実施の形態５に係る半導体装置の一部を拡大した上面図である。 本発明の実施の形態５に係る半導体装置の変形例を示す断面図である。 本発明の実施の形態５に係る半導体装置の変形例を示す断面図である。 本発明の実施の形態５に係る半導体装置の変形例を示す断面図である。 本発明の実施の形態５に係る半導体装置の変形例を示す断面図である。
本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。絶縁基板１上に純アルミ又は合金アルミ材からなるアルミパターン２が形成されている。アルミパターン２の表面にめっき３ａ，３ｂが形成されている。めっき３ａ，３ｂは互いに横並びに配置されている。めっき３ａ，３ｂはニッケルめっきであり、その厚みは１０μｍ以上である。
めっき３ａ，３ｂ上にそれぞれ半導体素子４ａ，４ｂがはんだ５により接合されている。半導体素子４ａ，４ｂの上面に電極６がはんだ７により接合されている。はんだ５とはんだ７は同一組成でも別組成でも構わない。電極８がアルミパターン２に接合されている。これら全体が樹脂等の封止材９で封止されている。
図２はめっきの硬度を測定した結果を示す図である。表１にも測定結果を示す。圧痕深さは装置レーザ検出器の数値である。
Figure 0006418126
めっき厚みを１０μｍにした場合、めっき厚み５μｍの場合に比べてアルミパターンとの密着度には優位性は見られず、何れもめっき部分の破断モードであった。また、めっき表面のビッカース硬度はニッケルの物性に依存し、厚みの影響を受けないため、めっき厚みを１０μｍにしても優位性は見られなかった。一方、めっき厚みを１０μｍにすることで、アルミパターンも含めたみかけのビッカース硬度が約２．５倍となった。従って、めっきを厚くすることで、めっきの変形とアルミパターンの変形が抑制されると考えられる。
図３は、従来のめっき厚みのアルミパターンの塑性変形ひずみを示す図である。図４は、めっき厚み１０μｍのアルミパターンの塑性変形ひずみを示す図である。何れもパワーサイクル５ｃｙｃ後を模擬した解析結果である。めっき厚みを１０μｍにすることで、アルミパターンの塑性変形が抑制されると共に、最大点を半導体素子の中央部から外側に移動させることができる。また、めっき自体の塑性変形も抑制され、アルミパターン変形の半導体素子への伝播が抑制される。
図５は、パワーサイクル数に対する累積欠陥率を示す図である。めっき厚１０μｍの場合にはめっき厚４μｍの場合に比べてパワーサイクル寿命が向上することが分かる。
以上説明したように、本実施の形態では、めっき３ａ，３ｂの厚みを１０μｍ以上にする。これにより、熱応力により変形したアルミパターン２の影響を半導体素子４ａ，４ｂが受け難くなる。従って、半導体素子４ａ，４ｂの変形による特性変動を防ぎ、半導体素子４ａ，４ｂの破壊に対する信頼性（パワーサイクル寿命）を向上させることができる。
また、アルミパターン２の表面には、ショットピーニング等により全面的又は部分的に加工硬化が施されていることが好ましい。これにより、アルミパターン２自体の変形を抑制することでめっき３ａ，３ｂの効果を増幅させることができる。
実施の形態２．
図６は、本発明の実施の形態２に係る半導体装置を示す断面図である。本実施の形態では、めっき３ａは、下層膜１０ａと、下層膜１０ａ上に形成された上層膜１１ａとを有する多層膜である。同様に、めっき３ｂは、下層膜１０ｂと、下層膜１０ｂ上に形成された上層膜１１ｂとを有する多層膜である。下層膜１０ａ，１０ｂは、上層膜１１ａ，１１ｂよりも剛性が高く、変形しにくいニッケルなどである。上層膜１１ａ，１１ｂは、下層膜１０ａ，１０ｂよりもはんだ５に対する濡れ性が高い金などである。これにより、強度を保って信頼性を向上させ、かつ、はんだ５の濡れ性が向上してボイド等も減ることでアセンブリ性を向上させることもできる。
実施の形態３．
図７は、本発明の実施の形態３に係る半導体装置を示す断面図である。本実施の形態では、半導体素子４ａは半導体素子４ｂより薄い。そこで、めっき３ａをめっき３ｂより厚くする。これにより、ＩＧＢＴとダイオードなど厚みが異なる半導体素子４ａ，４ｂを搭載する場合に、はんだ５の厚みを調整することなく半導体素子４ａ，４ｂの上面の高さを揃えることができる。このため、半導体素子４ａ，４ｂ上への電極接合等が容易になり、アセンブリ性が向上する。また、はんだ５の厚みを統一できるため、誤搭載を防止し、同一仕様の購入により単価を低下できる。
実施の形態４．
図８は、本発明の実施の形態４に係る半導体装置を示す断面図である。本実施の形態では、めっき３ａ，３ｂの厚みは半導体素子４ａ，４ｂの直下において変化する。これにより、変形が大きくなる半導体素子４ａ，４ｂの中央部直下のめっき３ａ，３ｂを厚くし、半導体素子４ａ，４ｂの変形を抑制することができる。また、その箇所のはんだ５の厚みを薄くすることができるため、熱抵抗が低減する。
図９及び図１０は、本発明の実施の形態４に係る半導体装置の変形例を示す断面図である。図９のように半導体素子４ａ，４ｂの外周部直下のめっき３ａ，３ｂを厚くしてもよいし、図１０のように半導体素子４ａ，４ｂの中央部と外周部直下のめっき３ａ，３ｂを厚くしてもよい。また、ＩＧＢＴの中央部直下、ダイオードの外周部直下など、半導体素子ごとに厚くする箇所を変えてもよい。
実施の形態５．
図１１は、本発明の実施の形態５に係る半導体装置を示す断面図である。図１２及び図１３は、本発明の実施の形態５に係る半導体装置の一部を拡大した上面図である。アルミパターン２の上面において半導体素子４ａ，４ｂの周囲に溝１２が設けられている。図１２のように半導体素子４ａ，４ｂの周囲全体に溝１２が設けられていてもよいし、図１３のように周囲の一部に溝１２が設けられていてもよい。これにより、アルミパターン２の溝１２より外周からの変形を溝１２で抑えることができる。また、溝１２によりはんだ流れを抑制することができ、アセンブリ性も向上できる。また、封止材９の密着性も向上する。
図１４〜１７は、本発明の実施の形態５に係る半導体装置の変形例を示す断面図である。図１１では溝１２の断面形状は長方形又は正方形であるが、これに限らず、図１４及び図１５のように台形、図１６のように三角形、又は図１７のように半円でも同様の効果を得ることができる。
なお、半導体素子４ａ，４ｂは、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。これにより、半導体素子４ａ，４ｂが高温になっても、半導体素子の変形を抑制し、高信頼性を確保することができる。また、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された半導体素子４ａ，４ｂを用いることで、この半導体素子４ａ，４ｂを組み込んだ半導体装置も小型化できる。また、半導体素子４ａ，４ｂの耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、半導体素子４ａ，４ｂの電力損失が低く高効率であるため、半導体装置を高効率化できる。また、半導体素子４ａ，４ｂの両方がワイドバンドギャップ半導体によって形成されていることが望ましいが、何れか一方の素子がワイドバンドギャップ半導体よって形成されていてもよく、この実施の形態に記載の効果を得ることができる。
１ 絶縁基板、２ アルミパターン、３ａ，３ｂ めっき、４ａ，４ｂ 半導体素子、５ はんだ、１０ａ，１０ｂ 下層膜、１１ａ，１１ｂ 上層膜、１２ 溝

Claims (6)

  1. 絶縁基板と、
    前記絶縁基板上に形成された純アルミ又は合金アルミ材からなるアルミパターンと、
    前記アルミパターンの表面に形成されためっきと、
    前記めっき上に接合された半導体素子とを備え、
    前記めっきの厚みは１０μｍ以上であり、
    前記めっきは、互いに横並びに配置された第１及び第２のめっきを有し、
    前記半導体素子は、前記第１及び第２のめっき上にそれぞれ接合された第１及び第２の半導体素子を有し、
    前記第１の半導体素子は前記第２の半導体素子より薄く、
    前記第１のめっきは前記第２のめっきより厚いことを特徴とする半導体装置。
  2. 前記半導体素子を前記めっきに接合するはんだを更に備え、
    前記めっきは、下層膜と、前記下層膜上に形成された上層膜とを有し、
    前記下層膜は前記上層膜よりも剛性が高く、
    前記上層膜は前記下層膜よりも前記はんだに対する濡れ性が高いことを特徴とする請求項１に記載の半導体装置。
  3. 前記めっきの厚みは前記半導体素子の直下において変化することを特徴とする請求項１又は２に記載の半導体装置。
  4. 前記アルミパターンの上面において前記半導体素子の周囲又は周囲の一部に溝が設けられていることを特徴とする請求項１〜３の何れか１項に記載の半導体装置。
  5. 前記アルミパターンの表面には全面的又は部分的に加工硬化が施されていることを特徴とする請求項１〜４の何れか１項に記載の半導体装置。
  6. 前記半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１〜５の何れか１項に記載の半導体装置。
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