TWI600132B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TWI600132B
TWI600132B TW104138216A TW104138216A TWI600132B TW I600132 B TWI600132 B TW I600132B TW 104138216 A TW104138216 A TW 104138216A TW 104138216 A TW104138216 A TW 104138216A TW I600132 B TWI600132 B TW I600132B
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electronic component
electronic
conductive
layer
package
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TW104138216A
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TW201719841A (zh
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張宏達
姜亦震
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矽品精密工業股份有限公司
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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Description

電子封裝件及其製法
本發明係有關一種封裝技術，尤指一種半導體封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，例如，扇出式封裝堆疊(Fan Out Package on package，簡稱FO PoP)等，以配合各種晶片上大幅增加之輸入/出埠數量，進而將不同功能之積體電路整合於單一封裝結構，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1圖係為習知用於PoP之半導體封裝件1的剖面示意圖。如第1圖所示，該半導體封裝件1係包括一具有至少一線路層101之封裝基板10、以及藉由覆晶方式結合於該線路層101上之一半導體元件11。
具體地，該半導體元件11具有相對之作用面11a與非作用面11b，該作用面11a具有複數電極墊110，以藉由複數如銲錫凸塊12電性連接該電極墊110與該線路層101，並形成底膠13於該半導體元件11與該線路層101之間，以包覆該些銲錫凸塊12。
再者，該半導體元件11形成有一封裝膠體15於該封裝基板10上，以包覆該底膠13及該半導體元件11，且形成複數導電通孔14於該封裝膠體15中，以令該導電通孔14之端面外露於該封裝膠體15，俾供後續藉由銲球(圖略)結合一如半導體晶片、矽中介板或封裝結構等之電子裝置(圖略)。
然而，習知半導體封裝件1中，係以該導電通孔14之外露端面作為外接點，故當該外接點之數量增加時，該導電通孔14之間的間距需縮小，此時各該導電通孔14之端面上之銲球之間容易發生橋接(bridge)。
再者，若習知半導體封裝件1需要更多功能時，於該封裝基板10上需設置更多種類之半導體元件11，此時需增加該封裝基板10之設置面積或增加整體封裝高度(如該封裝膠體15之高度)，因而導致該半導體封裝件1的尺寸增大。
因此，如何克服習知技術之種種缺點，實為目前各界亟欲解決之技術問題。
鑒於上述習知技術之缺失，本發明提供一種電子封裝 件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有至少一電性連接該第一線路結構之導電柱；第一電子元件，係結合並電性連接至該第一線路結構之第一側上；第二電子元件，係結合至該第一電子元件上；包覆層，係形成於該第一線路結構之第一側上，以包覆該第一電子元件、第二電子元件與該導電柱，且令該導電柱之端面與該第二電子元件外露於該包覆層；以及第二線路結構，係形成於該包覆層上且電性連接該導電柱與該第二電子元件。
本發明復提供一種電子封裝件之製法，包括：提供一第一線路結構，該第一線路結構具有相對之第一側與第二側，且該第一側上形成有至少一電性連接該第一線路結構之導電柱；形成一電子元件堆疊結構於該第一線路結構之第一側上，其中，該電子元件堆疊結構包含有結合並電性連接至該第一線路結構之第一電子元件、及結合至該第一電子元件之第二電子元件；形成包覆層於該第一線路結構之第一側上，以令該包覆層包覆該電子元件堆疊結構與該導電柱，且令該導電柱之端面與該第二電子元件外露於該包覆層；以及形成第二線路結構於該包覆層上，以由該第二線路結構電性連接該導電柱與該第二電子元件。
前述之製法中，該第二電子元件係具有相對之作用面與非作用面，且該作用面上具有複數導電凸塊與一覆蓋該些導電凸塊之絕緣層。
前述之製法中，該第二電子元件係具有相對之作用面 與非作用面，該作用面上具有一絕緣層與外露於該絕緣層之複數導電凸塊。
前述之電子封裝件及其製法中，該第一電子元件係以覆晶方式設於該第一線路結構之第一側上。
前述之電子封裝件及其製法中，該第二電子元件以結合層設於該第一電子元件上。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該第一線路結構之第二側上，以接置電子裝置。
前述之電子封裝件及其製法中，復包括形成複數導電元件於該第二線路結構上。
由上可知，本發明之電子封裝件及其製法，主要藉由該電子元件堆疊結構之設計，以利於整合多種晶片於單一封裝件中，且能縮小該電子封裝件之尺寸。
再者，藉由在該電子元件堆疊結構之上、下方形成第一與第二線路結構，而無需使用傳統的封裝基板，故可減少該電子封裝件之厚度，並降低生產成本。
另外，藉由該第一與第二線路結構之接觸墊(即該第一與第二線路重佈層之外露表面)作為外接點，可利於控制各該接觸墊之間的距離，以符合細間距的需求，且能避免各該導電元件之間發生橋接。
1‧‧‧半導體封裝件
10‧‧‧封裝基板
101‧‧‧線路層
11‧‧‧半導體元件
11a,21a,22a‧‧‧作用面
11b,21b,22b‧‧‧非作用面
110,210,210‧‧‧電極墊
12,211‧‧‧銲錫凸塊
13‧‧‧底膠
14‧‧‧導電通孔
15‧‧‧封裝膠體
2‧‧‧電子封裝件
2a‧‧‧電子元件堆疊結構
20‧‧‧第一線路結構
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧第一絕緣層
201‧‧‧第一線路重佈層
21‧‧‧第一電子元件
211a‧‧‧銅塊
22‧‧‧第二電子元件
221‧‧‧絕緣層
222‧‧‧導電凸塊
23‧‧‧導電柱
24,91‧‧‧結合層
25‧‧‧包覆層
26‧‧‧第二線路結構
260,260’‧‧‧第二絕緣層
261,261’‧‧‧第二線路重佈層
27‧‧‧導電元件
270‧‧‧凸塊底下金屬層
28‧‧‧絕緣保護層
4‧‧‧電子裝置
9‧‧‧承載板
90‧‧‧離型層
S‧‧‧切割路徑
第1圖係為習知半導體封裝件的剖面示意圖；以及第2A至2G圖係為本發明之電子封裝件及其製法的剖面示意圖，其中，第2C’圖係為第2C圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一設於承載板9上之第一線路結構20，該第一線路結構20具有相對之第一側20a與第二側20b，該第一側20a上形成有複數導電柱23，且該第二側20b結合至該承載板9上。
於本實施例中，該第一線路結構20係包括至少一第一絕緣層200與設於該第一絕緣層200上之一第一線路重佈層(redistribution layer，簡稱RDL)201。
再者，形成該第一線路重佈層201之材質係為銅，且形成該第一絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)之介電材。
又，該導電柱23設於該第一線路重佈層201上以電性連接該第一線路重佈層201，且形成該導電柱23之材質係為如銅之金屬材或銲錫材。
另外，該承載板9係為如玻璃之半導體材質之圓形板體，其上以塗佈方式依序形成有一離型層90與一結合層91，以供該第一線路結構20設於該結合層91上。
如第2B及2C圖所示，先結合一第一電子元件21至該第一線路結構20之第一側20a上，再結合一第二電子元件22於該第一電子元件21上，以令該第一電子元件21與該第二電子元件22形成一電子元件堆疊結構2a，且該第一電子元件21電性連接至該第一線路結構20。
於本實施例中，該第一電子元件21係為半導體元件係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係為半導體晶片，如微控制器(Microcontroller Unit，簡稱MCU)或特殊應用積體電路(Application Specific Integrated Circuit，簡稱ASIC)，其具有相對之作用面21a與非作用面21b，該作用面21a具有複數電極墊210，且該第一電子元件21以覆晶方式(如藉由複數具有銅塊211a之銲錫凸塊211)電性連接該第一線 路重佈層201與該電極墊210。
再者，該第二電子元件22係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係為半導體晶片，如動態隨機存取記憶體(Dynamic Random Access Memory，簡稱DRAM)或電源管理晶片(Power Management IC，簡稱PMIC)，其具有相對之作用面22a與非作用面22b，該作用面22a設有複數電極墊220與一絕緣層221，且於該電極墊220上形成如銅柱或錫球之導電凸塊222，使該絕緣層221覆蓋該些電極墊220與該些導電凸塊222。
或者，如第2C’圖所示，亦可令該導電凸塊222外露於該絕緣層221。
又，該第二電子元件22係以其非作用面22b藉由一結合層24黏固於該第一電子元件21之非作用面21b上。例如，先於該第二電子元件22下側形成該結合層24，再將該第二電子元件22黏固於該第一電子元件21上。應可理解地，亦可先於該第一電子元件21上形成該結合層24，再將該第二電子元件22黏固於該結合層24上。
如第2D圖所示，接續第2C圖之製程，形成一包覆層25於該第一線路結構20之第一側20a上，以令該包覆層25包覆該電子元件堆疊結構2a與該些導電柱23，再藉由整平製程，令該導電柱23之端面與該第二電子元件22之導電凸塊222外露於該包覆層25。
於本實施例中，該包覆層25係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一線路結構20之第一側20a上。
再者，該整平製程係藉由研磨方式，移除該導電柱23之部分材質與該絕緣層221之部分材質(依需求，可移除該導電凸塊222之部分材質)與該包覆層25之部分材質。
應可理解地，若接續第2C’圖之製程，移除該導電柱23之部分材質，即可令該些導電凸塊222外露於該包覆層25(依需求，可移除該絕緣層221之部分材質與該導電凸塊222之部分材質)。
如第2E圖所示，形成一第二線路結構26於該包覆層25上，且該第二線路結構26電性連接該些導電柱23與該第二電子元件22之導電凸塊222。
於本實施例中，該第二線路結構26係包括複數第二絕緣層260、及設於該第二絕緣層260上之複數第二線路重佈層261，且最外層之第二絕緣層260’可作為防銲層，以令最外層之第二線路重佈層261’外露於該防銲層。或者，該第二線路結構26亦可僅包括單一第二絕緣層260及單一第二線路重佈層261。
再者，形成該第二線路重佈層261,261’之材質係為銅，且形成該第二絕緣層260,260’之材質係為如聚對二唑苯(PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)之介電材。
又，形成複數如銲球之導電元件27於最外層之第二線 路重佈層261’上。另外，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)270於最外層之第二線路重佈層261’上，以利於結合該導電元件27。
如第2F圖所示，移除該承載板9及其上之離型層90。接著，形成一絕緣保護層28於該第一線路結構20之第二側20b上之結合層91上。
如第2G圖所示，沿如第2F圖所示之切割路徑S進行切單製程，以完成本發明之電子封裝件2，此外可形成複數如銲球之導電元件27於該第一線路結構20之第二側20b上，俾供後續接置如封裝結構或其它結構(如另一封裝件或晶片)之電子裝置4。
於本實施例中，該絕緣保護層28係為防銲層，且形成複數開孔於該絕緣保護層28與該結合層91上，以令該第一線路重佈層201外露於該些開孔，俾供結合該些導電元件27。
因此，本發明之電子封裝件2之製法係藉由將複數晶片(即第一與第二電子元件21,22)進行堆疊，以製成該電子元件堆疊結構2a，使該電子封裝件2內具有多種功能之晶片，故相較於習知技術，本發明之電子封裝件2不僅可提供更多功能，且可縮小該電子封裝件2之尺寸。
再者，該電子元件堆疊結構2a之上、下側均形成有線路結構(即該第一與第二線路結構20,26)，因而無需使用習知封裝基板，故可減少該電子封裝件2之厚度，並降低生產成本(即免用習知封裝基板)。
另外，藉由該第一與第二線路結構20,26之接觸墊(即該第一與第二線路重佈層201,261’外露於該開孔與第二絕緣層260’)作為外接點，可利於控制各該接觸墊之間的距離，以符合細間距的需求，且能避免各該導電元件27之間發生橋接。
本發明亦提供一種電子封裝件2，其包括：一第一線路結構20、一第一電子元件21、一第二電子元件22、一包覆層25以及一第二線路結構26。
所述之第一線路結構20係具有相對之第一側20a與第二側20b，該第一側20a上形成有複數導電柱23，且該導電柱23電性連接該第一線路結構20。
所述之第一電子元件21係結合並電性連接至該第一線路結構20。
所述之第二電子元件22係結合至該第一電子元件21上。
所述之包覆層25係形成於該第一線路結構20之第一側20a上，以令該包覆層25包覆該第一電子元件21、第二電子元件22與該些導電柱23，且令該導電柱23之端面與該第二電子元件22外露於該包覆層25。
所述之第二線路結構26係形成於該包覆層25上，且該第二線路結構26電性連接該導電柱23與該第二電子元件22。
於一實施例中，該第一電子元件21係以覆晶方式設於該第一線路結構20之第一側20a上。
於一實施例中，該第二電子元件22以一結合層24堆疊於該第一電子元件21上。
於一實施例中，該電子封裝件2復包括複數導電元件27，係形成於該第一線路結構20之第二側20b上。
於一實施例中，該電子封裝件2復包括複數導電元件27，係形成於該第二線路結構26上。
綜上所述，本發明之電子封裝件及其製法，係藉由該電子元件堆疊結構之設計，以整合多種晶片於單一封裝件中，不僅使封裝件的尺寸較小，且能增加外接點之數量，並當應用於細間距產品時，可避免各該導電元件之間發生橋接。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧第一線路結構
20a‧‧‧第一側
20b‧‧‧第二側
201‧‧‧第一線路重佈層
21‧‧‧第一電子元件
22‧‧‧第二電子元件
23‧‧‧導電柱
24,91‧‧‧結合層
25‧‧‧包覆層
26‧‧‧第二線路結構
27‧‧‧第一導電元件
28‧‧‧絕緣保護層
4‧‧‧電子裝置

Claims (12)

  1. 一種電子封裝件，係包括：第一線路結構，係具有相對之第一側與第二側，且該第一側上形成有至少一電性連接該第一線路結構之導電柱；第一電子元件，係結合並直接電性連接至該第一線路結構之第一側上；第二電子元件，係結合至該第一電子元件上；包覆層，係形成於該第一線路結構之第一側上，以包覆該第一電子元件、第二電子元件與該導電柱，且令該導電柱之端面與該第二電子元件外露於該包覆層；以及第二線路結構，係形成於該包覆層上且直接電性連接該導電柱與該第二電子元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件係以覆晶方式設於該第一線路結構之第一側上。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第二電子元件以結合層設於該第一電子元件上。
  4. 如申請專利範圍第1項所述之電子封裝件，復包括複數導電元件，係形成於該第一線路結構之第二側上，以接置電子裝置。
  5. 如申請專利範圍第1項所述之電子封裝件，復包括複數導電元件，係形成於該第二線路結構上。
  6. 一種電子封裝件之製法，係包括：提供一第一線路結構，該第一線路結構具有相對之第一側與第二側，且該第一側上形成有至少一電性連接該第一線路結構之導電柱；形成一電子元件堆疊結構於該第一線路結構之第一側上，其中，該電子元件堆疊結構包含有結合並直接電性連接至該第一線路結構之第一電子元件、及結合至該第一電子元件之第二電子元件；形成包覆層於該第一線路結構之第一側上，以令該包覆層包覆該電子元件堆疊結構與該導電柱，且令該導電柱之端面與該第二電子元件外露於該包覆層；以及形成第二線路結構於該包覆層上，以由該第二線路結構直接電性連接該導電柱與該第二電子元件。
  7. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該第一電子元件係以覆晶方式設於該第一線路結構之第一側上。
  8. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該第二電子元件以結合層設於該第一電子元件上。
  9. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該第二電子元件係具有相對之作用面與非作用面，且該作用面上具有複數導電凸塊與一覆蓋該些導電凸塊之絕緣層。
  10. 如申請專利範圍第6項所述之電子封裝件之製法，其 中，該第二電子元件係具有相對之作用面與非作用面，該作用面上具有一絕緣層與外露於該絕緣層之複數導電凸塊。
  11. 如申請專利範圍第6項所述之電子封裝件之製法，復包括形成複數導電元件於該第一線路結構之第二側上，以接置電子裝置。
  12. 如申請專利範圍第6項所述之電子封裝件之製法，復包括形成複數導電元件於該第二線路結構上。
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TW201209974A (en) * 2010-08-26 2012-03-01 Unimicron Technology Corp Package structure having (TSV) through-silicon-vias chip embedded therein and fabrication method thereof
TW201404047A (zh) * 2012-07-06 2014-01-16 Omnivision Tech Inc 具有多種類比數位轉換器模式之混合類比數位轉換器

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TW200947636A (en) * 2008-05-13 2009-11-16 Phoenix Prec Technology Corp An insulating board having a multilayer structure and a packing substrate using the same
TW201209974A (en) * 2010-08-26 2012-03-01 Unimicron Technology Corp Package structure having (TSV) through-silicon-vias chip embedded therein and fabrication method thereof
TW201404047A (zh) * 2012-07-06 2014-01-16 Omnivision Tech Inc 具有多種類比數位轉換器模式之混合類比數位轉換器

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