TWI645527B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI645527B
TWI645527B TW107107457A TW107107457A TWI645527B TW I645527 B TWI645527 B TW I645527B TW 107107457 A TW107107457 A TW 107107457A TW 107107457 A TW107107457 A TW 107107457A TW I645527 B TWI645527 B TW I645527B
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Taiwan
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conductive
electronic component
item
patent application
electronic package
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TW107107457A
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TW201939696A (zh
Inventor
邱志賢
陳嘉揚
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矽品精密工業股份有限公司
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Priority to TW107107457A priority Critical patent/TWI645527B/zh
Priority to CN201810378273.8A priority patent/CN110233112A/zh
Priority to US15/993,108 priority patent/US10410970B1/en
Application granted granted Critical
Publication of TWI645527B publication Critical patent/TWI645527B/zh
Publication of TW201939696A publication Critical patent/TW201939696A/zh

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Abstract

一種電子封裝件，係將電子元件與複數導電柱設於承載結構上，並以封裝層包覆該電子元件與導電柱，其中，該導電柱之周面之寬度係小於該導電柱之兩端面之寬度，以使該封裝層與該導電柱之間具有較佳的固定效果。本發明復提供該電子封裝件之製法。

Description

電子封裝件及其製法
本發明係有關一種半導體封裝製程，尤指一種電子封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂疊加複數封裝結構以形成封裝堆疊結構(Package on Package，簡稱POP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1圖係為習知封裝堆疊結構1之剖面示意圖。如第1圖所示，該封裝堆疊結構1係包含第一封裝基板11及第二封裝基板12。該第一封裝基板11具有相對之第一表面11a及第二表面11b，且於該第一表面11a上設有電性連接該第一封裝基板11之第一半導體元件10，而該第二表面11b上具有植球墊112以供結合銲球17。該第二封裝基板 12係具有相對之第三表面12a及第四表面12b，且該第三表面12a設有複數電性接觸墊120，又該第三表面12a及第四表面12b上具有防銲層123，並形成有複數開孔以外露該些電性接觸墊120。
於製作時，先將該第一半導體元件10係以覆晶方式電性連接該第一封裝基板11，且藉由底膠16充填於該第一半導體元件10與第一封裝基板11之間，並於該第一封裝基板11之第一表面11a上形成複數銲錫球13，再令該第二封裝基板12以其第四表面12b藉由該銲錫球13疊設且電性連接於該第一封裝基板11上。接著，形成封裝膠體14於該第一封裝基板11之第一表面11a與該第二封裝基板12之第四表面12b之間，以包覆該第一半導體元件10及銲錫球13。之後，以覆晶方式設置複數第二半導體元件15於該第三表面12a上以電性連接該些電性接觸墊120，且藉由底膠16充填於該第二半導體元件15與第二封裝基板12之間。
惟，習知封裝堆疊結構1之製法中，由於第一封裝基板11與第二封裝基板12間係以該銲錫球13作為支撐與電性連接之元件，且該銲錫球13具有一定的寬度，故隨著電子產品的接點(即I/O)數量愈來愈多，在封裝件的尺寸大小不變的情況下，各該銲錫球13間的間距需縮小，致使容易發生橋接(bridge)的現象，而造成產品良率過低及可靠度不佳等問題，因而該銲錫球13無法達到細間距(fine pitch)的需求。
再者，該銲錫球13係以植球或網印(screen printing)的方式形成於該第一封裝基板11上，且於回銲後之體積及高度之公差大，不僅接點容易產生缺陷，導致電性連接品質不良，而且該銲錫球13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該第一封裝基板11與第二封裝基板12之間呈傾斜接置，甚至產生接點偏移之問題。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種電子封裝件，係包括：承載結構；電子元件，係設於該承載結構上且電性連接該承載結構；複數導電柱，係設於該承載結構上，其中，該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於該兩端面之寬度；以及封裝層，係包覆該電子元件與該導電柱。
本發明復提供一種電子封裝件之製法，係包括：將導電架及至少一電子元件設於一承載結構上，其中，該導電架包含有板體與複數連接該板體之導電柱，並以該導電柱結合於該承載結構上，又該導電柱具有相對之兩端面及鄰接該兩端面之周面，該周面之寬度係小於該兩端面之寬度；以封裝層包覆該電子元件與該導電柱；以及移除該板體。
前述之製法中，該導電架之製作係移除金屬板之部分 材質，以形成用以間隔各該導電柱之凹部。
前述之電子封裝件及其製法中，該導電柱係電性連接該承載結構。
前述之電子封裝件及其製法中，該導電柱係藉由導電體結合至該承載結構上。
前述之電子封裝件及其製法中，該承載結構係具有相對之第一側與第二側，且該第一側與該第二側上均佈設有該電子元件或該封裝層。
前述之電子封裝件及其製法中，該電子元件之部分表面係外露出該封裝層之表面。
前述之電子封裝件及其製法中，該導電架復包含有結合墊，且該結合墊對應該電子元件之位置並至少部分外露出該封裝層。
前述之電子封裝件及其製法中，復包括形成屏蔽件以遮蓋該電子元件。
前述之電子封裝件及其製法中，復包括於移除該板體後，形成佈線結構於該封裝層上，且該佈線結構電性連接該導電柱或該電子元件。
由上可知，本發明之電子封裝件及其製法，主要藉由該導電架之導電柱取代習知銲錫球，以依需求調整各該導電柱之間的間距，故相較於習知技術，該些導電柱之間不會發生橋接之問題，因而能有效提高產品良率及可靠度，以達到細間距的需求。
再者，本發明之電子封裝件之製法係先製作該導電 架，再將該導電架設於該承載結構上，故相較於習知技術，本發明之製法可使該些導電柱的高度一致，使該些導電柱所排列成之柵狀陣列之共面性良好，因而能避免於後續製程中產生接點偏移之問題。
又，該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於該兩端面之寬度，使該導電柱之側壁內凹，而可容納該封裝層，以提供較佳的固定效果，故可避免因該封裝層與該導電柱的結合性不佳而於後續製程發生脫層之問題。
1‧‧‧封裝堆疊結構
10‧‧‧第一半導體元件
11‧‧‧第一封裝基板
11a‧‧‧第一表面
11b‧‧‧第二表面
112‧‧‧植球墊
12‧‧‧第二封裝基板
12a‧‧‧第三表面
12b‧‧‧第四表面
120‧‧‧電性接觸墊
123,202‧‧‧防銲層
13‧‧‧銲錫球
14‧‧‧封裝膠體
15‧‧‧第二半導體元件
16‧‧‧底膠
17‧‧‧銲球
2,3,4,5,6,7‧‧‧電子封裝件
2a,5a‧‧‧導電架
20,30‧‧‧承載結構
20a,30a‧‧‧第一側
20b,30b‧‧‧第二側
200‧‧‧線路層
201‧‧‧絕緣層
21‧‧‧第一電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
210,220‧‧‧導電凸塊
22‧‧‧第二電子元件
23‧‧‧導電柱
23a,23b‧‧‧端面
23c‧‧‧周面
230‧‧‧導電體
24‧‧‧板體
240‧‧‧凹部
25,55‧‧‧第一封裝層
25a‧‧‧第一表面
25b,55b‧‧‧第二表面
25c,26c‧‧‧側面
26‧‧‧第二封裝層
26a‧‧‧頂面
27,77,80‧‧‧導電元件
51‧‧‧結合層
53‧‧‧結合墊
68‧‧‧屏蔽件
71‧‧‧黏著層
79‧‧‧佈線結構
790‧‧‧介電層
791‧‧‧線路重佈層
8‧‧‧電子裝置
9‧‧‧支撐板
90‧‧‧離形膜
S‧‧‧切割路徑
W‧‧‧寬度
第1圖係為習知封裝堆疊結構之剖視示意圖；第2A至2E圖係為本發明之電子封裝件之製法之第一實施例之剖視示意圖；第3A至3C圖係為本發明之電子封裝件之製法之第二實施例之剖視示意圖；第4A至第4B圖係為本發明之電子封裝件之製法之第三實施例之不同態樣之剖視示意圖；第5A至5D圖係為本發明之電子封裝件之製法之第四實施例之剖視示意圖；其中，第5D’圖係為第5D圖之另一態樣；第6A至6E圖係為本發明之電子封裝件之製法之第五實施例之剖視示意圖；其中，第6C’圖係為第6C圖之另一步驟；以及第7A至7C圖係為本發明之電子封裝件之製法之第六 實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2E圖，係為本發明之電子封裝件2之製法之第一實施例之剖視示意圖。
如第2A圖所示，提供一導電架2a，其包含一板體24及複數分離設於該板體24上之導電柱23，其中，該導電柱23具有相對之兩端面23a,23b及鄰接該兩端面23a,23b之周面23c，且該周面23c之寬度係小於該兩端面23a,23b之寬度W。
於本實施例中，該導電柱23之周面23c係相對兩端面 23a,23b呈凹狀，使該兩端面23a,23b之寬度W大於該周面23c之寬度，且該板體24與導電柱23係一體成形。例如，以蝕刻、雷射或其它方式移除一金屬板之部分材質，以形成該導電架2a。具體地，該金屬板係經由蝕刻方式形成用以間隔各該導電柱23之底切型凹部240，使該導電柱23之周面23c呈內凹弧形。
如第2B圖所示，將該導電架2a設置於一承載結構20上，且設置至少一第一電子元件21於該承載結構20上。
於本實施例中，該承載結構20係具有相對之第一側20a與第二側20b，且該承載結構20係例如具有核心層與線路部之封裝基板(substrate)或具有線路部之無核心層(coreless)式封裝基板，其線路部具有至少一絕緣層201與設於該絕緣層201上之線路層200，該線路層200例如為扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)，並可依需求形成防焊層202於該第一側20a與第二側20b上。另外，形成該線路層200之材質係例如為銅，且形成該絕緣層201之材質係例如為聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，該承載結構亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(leadframe)或矽中介板(silicon interposer)，並不限於上述。
再者，該第一電子元件21係設於該承載結構20之第一側20a上，且該第一電子元件21係為主動元件、被動元 件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係具有相對之作用面21a與非作用面21b，其作用面21a藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該線路層200上並電性連接該線路層200；或者，該第一電子元件21可藉由複數銲線(圖略)以打線方式電性連接該線路層200。然而，有關該第一電子元件電性連接該承載結構之方式不限於上述。
又，該導電架2a以其導電柱23之端面23a藉由如銲錫材之導電體230結合至該承載結構20之第一側20a之線路層200上。
如第2C圖所示，形成第一封裝層25於該承載結構20之第一側20a上，以包覆該第一電子元件21與該些導電柱23及導電體230，且令該導電架2a之板體24外露出該第一封裝層25。
於本實施例中，該第一封裝層25具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合於該承載結構20之第一側20a上，並令該板體24外露出該第一封裝層25之第二表面25b。
再者，形成於該第一封裝層25之材質係例如為聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，但不限於上述。
如第2D圖所示，進行整平製程，以移除該導電架2a之板體24及部分該第一封裝層25，令該導電柱23之端面 23b與該第一封裝層25之第二表面25b共平面(齊平)，使該導電柱23之端面23b外露出該第一封裝層25之第二表面25b。
於本實施例中，係採用研磨、蝕刻、燒灼、切除或其它適合方式移除該板體24及部分該第一封裝層25，使該導電柱23之端面23b外露出該第一封裝層25，俾供後續進行電子電路之相關導路配置，如第2E圖所示之藉由如銲球之導電元件80外接如封裝結構或半導體晶片之其它電子裝置8。
再者，該第一封裝層25係填入該第一電子元件21與該承載結構20之第一側20a之間以包覆該些導電凸塊210；或者，可先填充底膠(圖略)於該第一電子元件21與該承載結構20之第一側20a之間以包覆該些導電凸塊210，再使該第一封裝層25包覆該底膠。
如第2E圖所示，結合複數如銲球之導電元件27於該承載結構20之第二側20b之線路層200上，俾供後續接置電路板(圖未示)。
請參閱第3A至3C圖，係為本發明之電子封裝件3之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於提供不同型式之承載結構30，其它製程則大致相同。
如第3A圖所示，於一支撐板9上進行RDL製程以形成線路部，並使該線路部作為承載結構30。接著，將導電架2a與複數第一電子元件21設於該承載結構30之第一側 30a上。
於本實施例中，該支撐板9上設有離形膜90，以利於後續分離該承載結構30。
再者，該承載結構30係為具有線路部之無核心層式封裝基板，其線路部具有至少一絕緣層201與設於該絕緣層201上之線路層200。
如第3B圖所示，形成第一封裝層25於該承載結構30之第一側30a上，以包覆該些第一電子元件21與該些導電柱23。接著，進行整平製程，使該導電柱23之端面23b外露出該第一封裝層25之第二表面25b。
如第3C圖所示，移除該支撐板9及其離形膜90，以外露該承載結構30之第二側30b，再結合複數如銲球之導電元件27於該承載結構30之第二側30b之線路層200上。
請參閱第4A及4B圖，係為本發明之電子封裝件4之第三實施例之剖面示意圖。本實施例與上述實施例之差異在於該承載結構20之第二側20b之佈設。
如第4A圖所示，於形成第一封裝層25之前，先設置第二電子元件22於該承載結構20之第二側20b上，再進行雙側模封(double side molding)製程，係形成該第一封裝層25於該承載結構20之第一側20a與第二側20b上以包覆該第一電子元件21與第二電子元件22。之後，於該些導電柱23之外露表面(端面23b)上形成有如銲球之導電元件27，俾供接置如電路板之電子裝置(圖未示)。
於本實施例中，該第二電子元件22係為主動元件、 被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第二電子元件22係藉由複數如銲錫材料之導電凸塊220以覆晶方式設於該線路層200上；或者，該第二電子元件22可藉由複數銲線(圖略)以打線方式電性連接該線路層200；亦或，該第二電子元件22可直接接觸該線路層200。然而，有關該第二電子元件電性連接該承載結構之方式不限於上述。
再者，該第一電子元件21之非作用面21b可選擇性不外露出該第一封裝層25之第二表面25b；或者，如第4B圖所示，該第一電子元件21之非作用面21b可外露出該第一封裝層25之第二表面25b。
請參閱第5A至5D圖，係為本發明之電子封裝件5之第四實施例之剖面示意圖。本實施例與第三實施例之差異在於該導電架5a之結構及製程步驟。
如第5A圖所示，該導電架5a係包含一板體24、相分離設於該板體24上之複數導電柱23與至少一結合墊53。
於本實施例中，該板體24、導電柱23與結合墊53係一體成形。例如，以蝕刻、雷射或其它方式移除一金屬板上之部分材質，以形成該導電架5a。
如第5B圖所示，將該導電架5a透過其導電柱23與導電體230設於承載結構20之第一側20a上，且第一電子元件21之非作用面21b可藉由結合層51結合至該結合墊53，並使該結合墊53作為散熱用。
於本實施例中，該結合層51係例如為薄膜(film)、環氧樹脂(epoxy)或熱介面材料(thermal interface material，簡稱TIM)。
再者，該承載結構20之第二側20b係設有第二電子元件22，且於形成該第一封裝層25之前，形成第二封裝層26於該承載結構20之第二側20b上以包覆該第二電子元件22。例如，形成該第二封裝層26之材質係為聚醯亞胺(PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，但不限於上述。
如第5C圖所示，形成第一封裝層55於該承載結構20之第一側20a與該板體24之間，使該第一封裝層55包覆該第一電子元件21、結合層51、結合墊53、導電體230與該些導電柱23。之後，移除該板體24，使該些導電柱23之端面23b與該結合墊53外露出該第一封裝層55之第二表面55b。
於本實施例中，該第一封裝層55之材質與該第二封裝層26之材質可相同(圖略)或不相同(如第5C圖所示)，亦或可同時形成該第一封裝層55與該第二封裝層26。
如第5D圖所示，於該些導電柱23之端面23b上形成有如銲球之導電元件27，俾供接置如電路板之電子裝置(圖略)。
於本實施例中，可依據散熱需求，該第一電子元件21與該結合墊53之間亦可免用該結合層51，如第5D’圖所示。
再者，可藉由該結合墊53之表面與該第一封裝層55之第二表面55b共平面(齊平)，使該結合墊53外露出該第一封裝層55之第二表面55b，如第5D圖所示；或者，可藉由形成開口(圖未示)於該第一封裝層55之第二表面55b之方式，使該結合墊53外露出該開口。
請參閱第6A至6E圖，係為本發明之電子封裝件6之第五實施例之剖面示意圖。本實施例與第四實施例之差異在於第一與第二封裝層25,26之製程順序。
如第6A圖所示，接續第2C圖所示之結構之製程，即已形成第一封裝層25於承載結構20之第一側20a上。
如第6B圖所示，設置第二電子元件22於承載結構20之第二側20b上，再形成第二封裝層26於該承載結構20之第二側20b上，使該第二封裝層26包覆該第二電子元件22。
於本實施例中，該第一封裝層25之材質與該第二封裝層26之材質可相同或不相同(圖略)。
如第6C圖所示，進行整平製程，以移除部分該板體24、部分該第一封裝層25之材質及該第一電子元件21之部分材質，使該導電柱23之端面23b與該第一封裝層25之第二表面25b共平面(齊平)。
於本實施例中，係以切除方式一次整平；亦可如第6C’圖所示，先以蝕刻方式移除部分該板體24、該第一封裝層25之第二表面25b之部分材質，再以該研磨方式移除該第一電子元件21之非作用面21b之部分材質，使該第一電子 元件21之非作用面21b與該第一封裝層25之第二表面25b共平面(如第6C圖所示)。
如第6D圖所示，沿如第6C圖所示之切割路徑S進行切單製程。
如第6E圖所示，形成一屏蔽件68於該第二封裝層26之頂面26a與側面26c及該第一封裝層25之側面25c，使該屏蔽件68接觸及電性連接該承載結構20之線路層200，以避免外界電磁干擾(Electro-Magnetic Interference，簡稱EMI)該第一電子元件21與第二電子元件22。
於本實施例中，可藉由濺鍍(sputtering)、蒸鍍(vaporing)、電鍍、化鍍或貼膜(foiling)等方式製作該屏蔽件68。
再者，於該些導電柱23之端面23b上形成有如銲球之導電元件27，俾供接置如電路板或另一線路板之電子裝置(圖略)。
請參閱第7A至7C圖，係為本發明之電子封裝件7之第六實施例之剖面示意圖。本實施例與第二實施例之差異在於第一電子元件21之設置方式。
如第7A圖所示，將第一電子元件21以其非作用面21b藉由黏著層71結合承載結構30之第一側30a，並於該第一電子元件21之作用面21a上設有複數導電凸塊210，且令導電架2a設於該承載結構30之第一側30a上。
如第7B圖所示，形成第一封裝層25於該承載結構30 之第一側30a上，再進行整平製程，使該第一電子元件21之導電凸塊210與該導電柱23之端面23b外露出該第一封裝層25之第二表面25b。
如第7C圖所示，形成佈線結構79於該第一封裝層25之第二表面25b上，且該佈線結構79電性連接該些導電柱23與該第一電子元件21。之後，移除該支撐板9及其離形膜90，以外露該承載結構30之第二側30b。
於本實施例中，該佈線結構79係包括複數介電層790、及設於該介電層790上之複數線路重佈層(RDL)791，且該線路重佈層791電性連接該些導電柱23與該第一電子元件21之導電凸塊210。例如，形成該線路重佈層791之材質係為銅，且形成該介電層790之材質係為聚對二唑苯(PBO)、聚醯亞胺(PI)或預浸材(PP)。
再者，可形成複數如銲球之導電元件77於最外層之線路重佈層791上，俾供後續接置如封裝結構或其它結構(如另一封裝件或晶片)之電子裝置(圖略)。
又，可依需求形成防焊層202於該第二側20b上，且可形成複數如銲球之導電元件27於該承載結構20之第二側20b之線路層200上，俾供後續接置如封裝結構或半導體晶片之電子裝置8。
綜上，本發明之電子封裝件之製法係藉由該導電架2a,5a之導電柱23取代習知銲錫球，以依需求調整各該導電柱23之間的間距，故相較於習知技術，該些導電柱23之間不會發生橋接之問題，因而能有效提高產品良率及可 靠度，以達到細間距(fine pitch)的需求。
再者，本發明之導電架2a,5a之製作係移除金屬板之部分材質，以形成用以間隔各該導電柱23之凹部240，再將該導電架2a,5a設於該承載結構20,30上，故相較於習知技術，本發明之製法可使該些導電柱23的高度一致，使該些導電柱23所排列成之柵狀陣列之共面性良好，因而能避免於後續製程中產生接點偏移之問題。
又，該導電柱23具有相對之兩端面23a,23b及鄰接該兩端面23a,23b之周面23c，且該周面23c之寬度係小於該兩端面23a,23b之寬度W，使該導電柱23之側壁內凹，而能容納該第一封裝層25,55，以提供該第一封裝層25,55與該導電柱23之間較佳的固定效果，故本發明之製法能避免因該第一封裝層25,55與該導電柱23的結合性不佳而於後續製程發生脫層之問題。
本發明復提供一種電子封裝件2,3,4,5,6,7，係包括：一承載結構20,30、第一與第二電子元件21,22、複數導電柱23以及第一與第二封裝層25,55,26。
所述之承載結構20,30係具有相對之第一側20a,30a與第二側20b,30b。
所述之第一電子元件21與第二電子元件22係設於該承載結構20,30之第一側20a,30a與第二側20b,30b上且電性連接該承載結構20,30。
所述之導電柱23係設於該承載結構20,30之第一側20a,30a上，其中，該導電柱23具有相對之兩端面23a,23b 及鄰接該兩端面23a,23b之周面23c，且該周面23c之寬度係小於該兩端面23a,23b之寬度W。
所述之第一封裝層25,55係包覆該第一電子元件21與該導電柱23。
所述之第二封裝層26係包覆該第二電子元件22。
於一實施例中，該導電柱23係電性連接該承載結構20,30。
於一實施例中，該導電柱23係藉由導電體230結合至該承載結構20,30上。
於一實施例中，該第一封裝層25具有相對之第一表面25a與第二表面25b，且其以第一表面25a結合於該承載結構20之第一側20a上，並令該第一電子元件21之部分表面(非作用面21b)外露出該第一封裝層25之第二表面25b。
於一實施例中，所述之電子封裝件5復包括結合墊53，係嵌埋於該第一封裝層55中且對應該第一電子元件21之位置並部分外露出該第一封裝層55之第二表面55b。
於一實施例中，所述之電子封裝件6復包括屏蔽件68，係遮蓋該第一電子元件21與第二電子元件22。
於一實施例中，所述之電子封裝件7復包括佈線結構79，係設於該第一封裝層25之第二表面25b上並電性連接該導電柱23與該第一電子元件21。
綜上所述，本發明之電子封裝件及其製法，可依需求調整各該導電柱之間的間距，故該些導電柱之間不會發生 橋接之問題，因而能有效提高產品良率及可靠度，以達到細間距的需求。
再者，藉由先製作該導電架，再將該導電架設於該承載結構上，故相較於習知技術，本發明之製法可使該些導電柱的高度一致，使該些導電柱所排列成之柵狀陣列之共面性良好，因而能避免於後續製程中產生接點偏移之問題。
又，該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之寬度係小於該兩端面之寬度，使該導電柱之側壁內凹，而可容納該封裝層，以提供較佳的固定效果，故能避免因該封裝層與該導電柱的結合性不佳而於後續製程發生脫層之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (17)

  1. 一種電子封裝件，係包括：承載結構；電子元件，係設於該承載結構上且電性連接該承載結構；複數導電柱，係藉由導電體結合且電性連接該承載結構，其中，該導電柱具有相對之兩端面及鄰接該兩端面之周面，且該周面之縱剖面呈一內凹之弧線；以及封裝層，係包覆該電子元件與該導電柱。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該承載結構係具有相對之第一側與第二側，且該第一側與該第二側上均佈設有該電子元件。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該承載結構係具有相對之第一側與第二側，且該第一側與該第二側上均佈設有該封裝層。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件之部分表面係外露出該封裝層之表面。
  5. 如申請專利範圍第1項所述之電子封裝件，復包括結合墊，係嵌埋於該封裝層中且對應該電子元件之位置並至少部分外露出該封裝層之表面。
  6. 如申請專利範圍第1項所述之電子封裝件，復包括遮蓋該電子元件之屏蔽件。
  7. 如申請專利範圍第1項所述之電子封裝件，復包括設於該封裝層上並電性連接該導電柱之佈線結構。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括設於該封裝層上並電性連接該電子元件之佈線結構。
  9. 一種電子封裝件之製法，係包括：製備導電架，其中，該導電架包含有板體與複數連接該板體之導電柱，且該導電柱具有相對之兩端面及鄰接該兩端面之周面，該周面之縱剖面呈一內凹之弧線；於製備導電架之後，將該導電架及至少一電子元件設於一承載結構上，其中，該導電架以該導電柱接置於該承載結構上，且該導電柱藉由導電體結合且電性連接該承載結構；於將該導電架及至少一電子元件設於一承載結構上之後，以封裝層包覆該電子元件與該導電柱；以及於以封裝層包覆該電子元件與該導電柱之後，移除該板體。
  10. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電架之製作係移除金屬板之部分材質，以形成用以間隔各該導電柱之凹部。
  11. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該承載結構係具有相對之第一側與第二側，且該第一側與該第二側上均佈設有該電子元件。
  12. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該承載結構係具有相對之第一側與第二側，且該第一側與該第二側上均佈設有該封裝層。
  13. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該電子元件之部分表面係外露出該封裝層之表面。
  14. 如申請專利範圍第9項所述之電子封裝件之製法，其中，該導電架復包含有結合墊，且該結合墊對應該電子元件之位置並至少部分外露出該封裝層。
  15. 如申請專利範圍第9項所述之電子封裝件之製法，復包括形成屏蔽件以遮蓋該電子元件。
  16. 如申請專利範圍第9項所述之電子封裝件之製法，復包括於移除該板體後，於該封裝層上形成電性連接該導電柱之佈線結構。
  17. 如申請專利範圍第9項所述之電子封裝件之製法，復包括於移除該板體後，於該封裝層上形成電性連接該電子元件之佈線結構。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700796B (zh) * 2019-05-23 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR20220000273A (ko) * 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
TWI731737B (zh) * 2020-07-03 2021-06-21 財團法人工業技術研究院 導線架封裝結構
TWI723932B (zh) * 2020-08-06 2021-04-01 強茂股份有限公司 側面可潤濕封裝元件及其製法
US12033923B2 (en) * 2020-09-16 2024-07-09 Advanced Semiconductor Engineering, Inc. Semiconductor package structure having a lead frame and a passive component
KR20220093507A (ko) * 2020-12-28 2022-07-05 삼성전기주식회사 패키지 내장기판
CN115472574A (zh) * 2021-06-10 2022-12-13 矽品精密工业股份有限公司 电子封装件及其制法
WO2023043548A1 (en) * 2021-09-20 2023-03-23 Qualcomm Incorporated Package comprising a substrate with high density interconnects
US20230230854A1 (en) * 2022-01-18 2023-07-20 Wenkai Wu Power module packaging systems and fabrication methods
TWI807665B (zh) * 2022-03-03 2023-07-01 復盛精密工業股份有限公司 預成型導電柱結構及其製作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100289126A1 (en) * 2009-05-18 2010-11-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame
US20120112326A1 (en) * 2010-06-02 2012-05-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die
US20130307140A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US20160276248A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1851798B1 (en) * 2005-02-25 2016-08-03 Tessera, Inc. Microelectronic assemblies having compliancy
KR101025349B1 (ko) * 2007-07-25 2011-03-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US8349658B2 (en) * 2010-05-26 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
TWI435427B (zh) * 2012-02-01 2014-04-21 矽品精密工業股份有限公司 半導體承載件暨封裝件及其製法
CN203351587U (zh) * 2012-09-17 2013-12-18 新科金朋有限公司 半导体器件
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
TWI571185B (zh) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9875970B2 (en) * 2016-04-25 2018-01-23 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100289126A1 (en) * 2009-05-18 2010-11-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame
US20120112326A1 (en) * 2010-06-02 2012-05-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die
US20130307140A1 (en) * 2012-05-18 2013-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US20160276248A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI700796B (zh) * 2019-05-23 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法

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