TWI652787B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TWI652787B
TWI652787B TW106117381A TW106117381A TWI652787B TW I652787 B TWI652787 B TW I652787B TW 106117381 A TW106117381 A TW 106117381A TW 106117381 A TW106117381 A TW 106117381A TW I652787 B TWI652787 B TW I652787B
Authority
TW
Taiwan
Prior art keywords
circuit structure
electronic component
conductive
electronic
electronic package
Prior art date
Application number
TW106117381A
Other languages
English (en)
Other versions
TW201901908A (zh
Inventor
邱志賢
陳嘉揚
何志強
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW106117381A priority Critical patent/TWI652787B/zh
Priority to CN201710436397.2A priority patent/CN108962840B/zh
Priority to US15/694,613 priority patent/US10643974B2/en
Publication of TW201901908A publication Critical patent/TW201901908A/zh
Application granted granted Critical
Publication of TWI652787B publication Critical patent/TWI652787B/zh
Priority to US16/837,470 priority patent/US10916526B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一種電子封裝件及其製法，係先提供一包含有一支撐板與複數設於該支撐板上之導電柱的金屬件，再將線路結構結合至該些導電柱上，且接置電子元件於該金屬件上並電性連接該線路結構，並以封裝層包覆該些導電柱與該第一電子元件，無需配合該電子封裝件之尺寸使用特定尺寸之模壓模具，因而能降低生產成本。

Description

電子封裝件及其製法
本發明係關於一種半導體結構，特別是關於一種封裝結構及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢發展，其中，應用於該可攜式電子產品之各態樣的半導體封裝結構也因而配合推陳出新，以期能符合輕薄短小與高密度的要求。
第1圖係為習知半導體封裝結構1的剖視示意圖。該半導體封裝結構1係於一線路結構10之上、下兩側設置半導體元件11與被動元件11’，再以封裝膠體14包覆該些半導體元件11與被動元件11’，並使該線路結構10之接點(I/O)100外露出該封裝膠體(molding compound)14，之後形成複數銲球13於該些接點100上，以於後續製程中，該半導體封裝結構1透過該銲球13接置如電路板之電子裝置(圖略)。
惟，習知半導體封裝結構1中，由於需使該封裝膠體 14的模壓(molding)範圍縮減以外露該些接點100，因而需視該半導體封裝結構1之尺寸而使用特定尺寸之模壓模具，故單一模壓模具無法適用於各式半導體封裝結構之尺寸，因而增加生產成本。
又，該些半導體元件11與被動元件11’包覆於該封裝膠體14中，致使該些半導體元件11與被動元件11’之散熱效果不佳。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：線路結構，係具有相對之第一側與第二側；複數導電柱，係設於該線路結構之第一側上；複數導電體，係對應設於各該導電柱上以位於各該導電柱與該線路結構之第一側之間，使該些導電柱藉由該些導電體電性連接該線路結構；至少一第一電子元件，係設於該線路結構之第一側上並電性連接該線路結構；至少一第二電子元件，係設於該線路結構之第二側上並電性連接該線路結構；以及封裝層，係形成於該線路結構之第一側上以包覆該些導電柱與該第一電子元件。
本發明復提供一種電子封裝件之製法，係包括：提供一金屬件，該金屬件包含有一支撐板及複數設於該支撐板上之導電柱；將具有相對之第一側與第二側之線路結構以該第一側結合至該些導電柱上，使該些導電柱藉由導電體 電性連接該線路結構，其中，該線路結構之第一側與第二側上分別接置有至少一第一電子元件與至少一第二電子元件，並以封裝層包覆該些導電柱、該些導電體與該第一電子元件；以及移除該支撐板。
前述之製法中，該線路結構之第一側第二側係先接置有該第一電子元件與第二電子元件，接著將該線路結構之第一側接置於該導電柱上，再於該線路結構之第一側與該支撐板間形成包覆該導電柱與該第一電子元件之封裝層，之後移除該支撐板。
前述之製法中，該第一電子元件係先接置於該支撐板上，接著於該支撐板上形成包覆該導電柱及該第一電子元件之封裝層，然後於該封裝層上形成電性連接該導電柱與該第一電子元件之該線路結構，再於該線路結構上接置該第二電子元件，之後移除該支撐板。
前述之電子封裝件及其製法中，該金屬件復具有嵌設於該封裝層中以結合該第一電子元件之結合墊。
前述之電子封裝件及其製法中，該線路結構之第二側形成有包覆該第二電子元件之包覆層；亦或該封裝層復形成於該線路結構之第二側上以包覆該第二電子元件。
前述之電子封裝件及其製法中，該導電柱之頂面係外露出該封裝層。進一步地，該導電柱之部分側面亦外露出該封裝層。
前述之電子封裝件及其製法中，復包括結合該導電柱之電性接觸墊。進一步地，該電性接觸墊之側面外露出該 封裝層。
前述之電子封裝件及其製法中，該導電體係為銲錫材、金屬柱或其二者組合。
由上可知，本發明之電子封裝件及其製法中，主要藉由包含有支撐板及導電柱之金屬件之設計，以令電子元件及線路結構接置於該支撐板及導電柱上，再於該支撐板上形成包覆該電子元件、導電體及該導電柱之封裝層，故相較於習知技術，本發明使用共用模壓模具形成該封裝層即可，而無需配合該電子封裝件之尺寸，因而能降低生產成本。
再者，藉由該金屬架包含有用以結合至電子元件之結合墊之設計，以提升該電子封裝件之散熱效果。
1‧‧‧半導體封裝結構
10,20,30‧‧‧線路結構
100‧‧‧接點
11‧‧‧半導體元件
11’‧‧‧被動元件
13‧‧‧銲球
14‧‧‧封裝膠體
2,2’,2”,3,4,4’,5,5’‧‧‧電子封裝件
2a‧‧‧電子組件
20a,30a‧‧‧第一側
20b,30b‧‧‧第二側
200,300‧‧‧線路層
21‧‧‧第一電子元件
210,220‧‧‧導電凸塊
22‧‧‧第二電子元件
23,33,53‧‧‧導電體
24‧‧‧包覆層
25‧‧‧金屬件
250‧‧‧導電柱
250a‧‧‧頂面
250b‧‧‧端部
250c‧‧‧側面
251‧‧‧結合墊
252‧‧‧支撐板
252’‧‧‧電性接觸墊
252c‧‧‧側面
26,26’‧‧‧封裝層
26a‧‧‧第一表面
26b‧‧‧第二表面
26c‧‧‧側表面
28‧‧‧結合層
40‧‧‧銲錫材料
第1圖係為習知半導體封裝結構之剖面示意圖；第2A至2C圖係為本發明之電子封裝件之製法之第一實施例之剖面示意圖；第2C’及2C”圖係為對應第2C圖之其它實施態樣之剖面示意圖；第3A至3C圖係為本發明之電子封裝件之製法之第二實施例之剖面示意圖；第4A及4B圖係為本發明之電子封裝件之第三實施例之剖面示意圖；以及第5A及5B圖係為本發明之電子封裝件之第四實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之電子封裝件之製法之第一實施例之剖面示意圖。
如第2A圖所示，提供一金屬件25，其包含一支撐板252、相分離地設於該支撐板252上之複數導電柱250與至少一結合墊251。
於本實施例中，該支撐板252、導電柱250與結合墊251係一體成形。例如，以蝕刻、雷射或其它方式移除一金屬板體上之材質，以形成該金屬件25。
如第2B圖所示，將一電子組件2a結合至該些導電柱 250上，使該電子組件2a堆疊於該金屬件25上。
於本實施例中，該電子組件2a包含有線路結構20以及設於該線路結構20上之第一電子元件21與第二電子元件22。
所述之線路結構20係具有相對之第一側20a與第二側20b。於本實施例中，該線路結構20係為如具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，其具有複數線路層200，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該線路結構20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(leadframe)，並不限於上述。
所述之第一電子元件21係設於該線路結構20之第一側20a上。於本實施例中，該第一電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第一電子元件21係藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該線路層200上並電性連接該線路層200；或者，該第一電子元件21可藉由複數銲線(圖略)以打線方式電性連接該線路層200。然而，有關該第一電子元件21電性連接該線路結構20之方式不限於上述。
所述之第二電子元件22係設於該線路結構20之第二側20b上。於本實施例中，該第二電子元件22係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例 如，該第二電子元件22係藉由複數如銲錫材料之導電凸塊220以覆晶方式設於該線路層200上；或者，該第二電子元件22可藉由複數銲線(圖略)以打線方式電性連接該線路層200；亦或，該第二電子元件22可直接接觸該線路層200。然而，有關該第二電子元件22電性連接該線路結構20之方式不限於上述。
再者，該第一電子元件21可藉由一結合層28結合至該結合墊251，其中，該結合層28係例如為薄膜(film)、環氧樹脂(epoxy)或熱介面材料(thermal interface material，簡稱TIM)。
又，該些導電柱250可藉由如銲錫材之導電體23結合至該線路結構20之第一側20a之線路層200上。
另外，該電子組件2a復可包含一包覆層24，其形成於該線路結構20之第二側20b上以包覆該第二電子元件22。例如，形成該包覆層24之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)，但不限於上述。
如第2C圖所示，形成一封裝層26於該線路結構20之第一側20a與該金屬件25(該支撐板252)之間，使該封裝層26包覆該第一電子元件21、導電體23與該些導電柱250。之後，移除該支撐板252，使該些導電柱250之頂面250a與該結合墊251外露出該封裝層26，以形成本發明之電子封裝件2。
於本實施例中，該封裝層26具有相對之第一表面26a 與第二表面26b，使該封裝層26以其第二表面26b結合該線路結構20之第一側20a，且該些導電柱250與該結合墊251嵌設於該封裝層26之第一表面26a，並使該些導電柱250之頂面250a與該結合墊251外露出該封裝層26之第一表面26a(例如，該些導電柱250之頂面250a與該結合墊251之表面齊平該封裝層26之第一表面26a)，以於該些導電柱250之外露表面(頂面)上形成有如銲球之銲錫材料(圖略)，俾供接置如電路板之電子裝置。
再者，形成該封裝層26之材質係為聚醯亞胺(PI)、乾膜、環氧樹脂或封裝材，故該封裝層26之材質與該包覆層24之材質可相同或不相同。
又，如第2C’圖所示之電子封裝件2’，於移除該支撐板252後，可移除該封裝層26之部分第一表面26a，使該些導電柱250凸出該封裝層26之第一表面26a，以令該些導電柱250之頂面250a與部分側面250c外露出該封裝層26之第一表面26a。
另外，如第2C”圖所示之電子封裝件2”，若該電子組件2a未事先形成包覆層24，則可於線路結構20之第一側20a及第二側20b上形成封裝層26,26’，令封裝層26包覆該第一電子元件21及令封裝層26’包覆該第二電子元件22；或者，亦可保留部分該支撐板252以作為該電性接觸墊252’，其中，該電性接觸墊252’連接至該導電柱250，且該電性接觸墊252’之側面252c外露出該封裝層26之側表面26c。應可理解地，亦可依需求，使該些導電 柱250之側面250c及該電性接觸墊252’之側面252c外露出該封裝層26之側表面26c。
本發明之製法中，係先製作該金屬件25，再形成該封裝層26，並使該導電柱250外露出該封裝層26以作為電性接點，故無需配合該電子封裝件2,2’,2”之尺寸而使用特定尺寸之模壓模具，亦即使用共用模壓模具形成該封裝層26即可，因而能降低生產成本。
再者，藉由該結合墊251之設計，以傳導該第一電子元件21之熱量，故能提升該電子封裝件2,2’,2”之散熱效果。
第3A至3C圖係為本發明之電子封裝件3之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異在於製程步驟順序，故以下僅說明相異處，而不再贅述相同處。
如第3A圖所示，首先於金屬件25之結合墊251上藉由結合層28結合第一電子元件21，且於該金屬件25之支撐板25上形成該封裝層26以包覆該第一電子元件21與該金屬件25之導電柱250。
於本實施例中，係以壓合方式形成該封裝層26，使該封裝層26覆蓋該第一電子元件21與該些導電柱250之端部250b。
如第3B圖所示，形成一線路結構30於該封裝層26上。
於本實施例中，係於該封裝層26上直接進行扇出型重 佈線路層之製作以形成該線路結構30，使該線路結構30於製作該線路層300時，可將部分線路(即導電盲孔)延伸至該封裝層26中以作為金屬柱之導電體33，俾供電性連接該線路層300、該些導電柱250與該第一電子元件21。應可理解地，若該些導電柱250之端部250b不低於該封裝層26之第二表面26b(亦即，該些導電柱250之端部250b可齊平該封裝層26之第二表面26b)，則該線路層200無需延伸入該封裝層26中，即可電性連接該些導電柱250與該第一電子元件21。
如第3C圖所示，接置複數第二電子元件22於該線路結構30之第二側30b上，且形成包覆層24於該線路結構30之第二側30b上以包覆該第二電子元件22，再移除該支撐板252，以形成本發明之電子封裝件3。
因此，本發明之電子封裝件3，藉由先製作該金屬件25，再形成該封裝層26，並使該導電柱250外露出該封裝層26以作為電性接點，故無需配合該電子封裝件3之尺寸而使用特定尺寸之模壓模具，亦即使用共用模壓模具形成該封裝層26即可，因而能降低生產成本。
再者，藉由該結合墊251之設計，以傳導該第一電子元件21之熱量，故能提升該電子封裝件3之散熱效果。。
第4A及4B圖係為本發明之電子封裝件4,4’之第三實施例之剖面示意圖。本實施例與第一實施例之差異在於金屬件25之加工，故以下僅說明相異處，而不再贅述相同處。
如第4A圖所示，該結合墊251係作為散熱片，其凸出該封裝層26之第一表面26a。
如第4B圖所示，該第一電子元件21未結合至該結合墊251，因而省略使用該結合層28，且於該些導電柱250之外露表面(頂面)上形成有如銲球之銲錫材料40，俾供接置如電路板之電子裝置。
第5A及5B圖係為本發明之電子封裝件5,5’之第四實施例之剖面示意圖。本實施例與第一實施例之差異在於導電體之構造，故以下僅說明相異處，而不再贅述相同處。
如第5A圖所示，該導電體23,53係由金屬柱與銲錫材所構成。
於本實施例中，係於第2B圖之製程前，先將金屬柱之導電體53形成於該線路結構20之第一側20a之線路層200上，再將銲錫材之導電體23形成於該金屬柱上，以於第2B圖之製程中，將銲錫材之導電體23結合該導電柱250。
再者，如第5B圖所示，該些導電柱250與該結合墊251亦可凸出該封裝層26之第一表面26a。
本發明復提供一種電子封裝件2,2’,2”,3,4,4’,5,5’，其包括：一線路結構20,30、複數導電柱250、複數導電體23,33,53、至少一第一電子元件21以及一封裝層26,26’。
所述之線路結構20,30係具有相對之第一側20a,30a與第二側20b,30b。
所述之導電柱250係設於該線路結構20,30之第一側 20a,30a上。
所述之導電體23,33,53係對應設於各該導電柱250上以位於各該導電柱250與該線路結構20,30之第一側20a,30a之間，使該些導電柱250藉由該些導電體23,33,53電性連接該線路結構20,30。
所述之第一電子元件21係設於該線路結構20,30之第一側20a,30a上並電性連接該線路結構20,30。
所述之封裝層26係形成於該線路結構20,30之第一側20a,30a上以包覆該些導電柱250、該些導電體23,33,53與該第一電子元件21。
於一實施例中，所述之電子封裝件2,2’,2”,3,4,5,5’復包括一結合該第一電子元件21且外露於該封裝層26之結合墊251。
於一實施例中，該線路結構20,30之第二側20b,30b設有第二電子元件22。
於一實施例中，該導電柱250之頂面250a係外露出該封裝層26之第一表面26a、或該導電柱250之頂面250a與部分側面250c係外露出該封裝層26之第一表面26a。
於一實施例中，該導電柱250之側面250c外露出該封裝層26之側表面26c。
於一實施例中，所述之電子封裝件2”復包括至少一嵌設於該封裝層26中以結合該導電柱250之電性接觸墊252’。例如，該電性接觸墊252’之側面252c外露出該封裝層26之側表面26c。
於一實施例中，該導電體23,33,53係為銲錫材、金屬柱或其二者組合。
綜上所述，本發明之電子封裝件及其製法，係藉由包含有支撐板、結合墊及導電柱之該金屬件之設計，以令電子元件及線路結構接置於該結合墊及導電柱上，再於該支撐板上形成該封裝層，故無需配合該電子封裝件之尺寸而使用特定尺寸之模壓模具，亦即使用共用模壓模具形成該封裝層即可，因而能降低生產成本。
再者，藉由該結合墊之設計，以傳導該第一電子元件之熱量，故能提升該電子封裝件之散熱效果。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (13)

  1. 一種電子封裝件，係包括：線路結構，係具有相對之第一側與第二側；複數導電柱，係設於該線路結構之第一側上；複數導電體，係對應設於各該導電柱上以位於各該導電柱與該線路結構之第一側之間，使該些導電柱藉由該些導電體電性連接該線路結構；至少一第一電子元件，係設於該線路結構之第一側上並電性連接該線路結構；結合墊，係設於該第一電子元件上；至少一第二電子元件，係設於該線路結構之第二側上並電性連接該線路結構；以及封裝層，係形成於該線路結構之第一側上以包覆該些導電柱、該些導電體與該第一電子元件，其中，該些導電柱之頂面和部分側面與設於該第一電子元件上之該結合墊係外露出該封裝層。
  2. 如申請專利範圍第1項所述之電子封裝件，復包括形成於該線路結構之第二側上以包覆該第二電子元件之包覆層。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該封裝層復形成於該線路結構之第二側上以包覆該第二電子元件。
  4. 如申請專利範圍第1項所述之電子封裝件，復包括結合於該導電柱上之電性接觸墊，且該電性接觸墊係外露出該封裝層。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該導電體係為銲錫材、金屬柱或其二者組合。
  6. 一種電子封裝件之製法，係包括：提供一金屬件，該金屬件包含有一支撐板、設於該支撐板上之結合墊及複數設於該支撐板上之導電柱，且該支撐板、導電柱與結合墊係一體成形；將具有相對之第一側與第二側之線路結構以該第一側結合至該些導電柱上，使該些導電柱藉由導電體電性連接該線路結構，其中，該線路結構之第一側與第二側上分別接置有至少一第一電子元件與至少一第二電子元件，其中，該第一電子元件係結合至該結合墊上，並以封裝層包覆該些導電柱、該些導電體與該第一電子元件，且令該些導電柱之頂面與結合該第一電子元件上之該結合墊係外露出該封裝層；以及移除部分該支撐板並保留部分該支撐板以作為電性接觸墊，其中，該電性接觸墊連結至該導電柱。
  7. 如申請專利範圍第6項所述之電子封裝件之製法，復包括形成包覆層於該線路結構之第二側上以包覆該第二電子元件。
  8. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該導電柱之部分側面亦外露出該封裝層。
  9. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該封裝層復形成於該線路結構之第二側上以包覆該第二電子元件。
  10. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該電性接觸墊係外露出該封裝層。
  11. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該線路結構之第一側第二側係先接置有該第一電子元件與第二電子元件，接著將該線路結構之第一側接置於該導電柱上，再於該線路結構之第一側與該支撐板間形成包覆該導電柱與該第一電子元件之封裝層，之後移除該支撐板。
  12. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該第一電子元件係先接置於該支撐板上，接著於該支撐板上形成包覆該導電柱及該第一電子元件之封裝層，然後於該封裝層上形成電性連接該導電柱與該第一電子元件之該線路結構，再於該線路結構上接置該第二電子元件，之後移除該支撐板。
  13. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該導電體係為銲錫材、金屬柱或其二者組合。
TW106117381A 2017-05-25 2017-05-25 電子封裝件及其製法 TWI652787B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW106117381A TWI652787B (zh) 2017-05-25 2017-05-25 電子封裝件及其製法
CN201710436397.2A CN108962840B (zh) 2017-05-25 2017-06-12 电子封装件及其制法
US15/694,613 US10643974B2 (en) 2017-05-25 2017-09-01 Electronic package with conductive pillars
US16/837,470 US10916526B2 (en) 2017-05-25 2020-04-01 Method for fabricating electronic package with conductive pillars

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106117381A TWI652787B (zh) 2017-05-25 2017-05-25 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TW201901908A TW201901908A (zh) 2019-01-01
TWI652787B true TWI652787B (zh) 2019-03-01

Family

ID=64401404

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106117381A TWI652787B (zh) 2017-05-25 2017-05-25 電子封裝件及其製法

Country Status (3)

Country Link
US (2) US10643974B2 (zh)
CN (1) CN108962840B (zh)
TW (1) TWI652787B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
TWI740305B (zh) * 2019-12-13 2021-09-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI719866B (zh) * 2020-03-25 2021-02-21 矽品精密工業股份有限公司 電子封裝件及其支撐結構與製法
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
TWI839645B (zh) * 2021-10-13 2024-04-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI804411B (zh) * 2022-08-09 2023-06-01 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859250B2 (en) * 2013-12-20 2018-01-02 Cyntec Co., Ltd. Substrate and the method to fabricate thereof
KR101651362B1 (ko) * 2015-05-22 2016-08-25 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
TWI570842B (zh) * 2015-07-03 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9881902B2 (en) * 2015-08-05 2018-01-30 Mediatek Inc. Semiconductor package, semiconductor device using the same and manufacturing method thereof
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US11569176B2 (en) * 2017-03-21 2023-01-31 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing thereof

Also Published As

Publication number Publication date
US10643974B2 (en) 2020-05-05
US20180342484A1 (en) 2018-11-29
US10916526B2 (en) 2021-02-09
US20200227390A1 (en) 2020-07-16
CN108962840B (zh) 2020-01-31
TW201901908A (zh) 2019-01-01
CN108962840A (zh) 2018-12-07

Similar Documents

Publication Publication Date Title
TWI652787B (zh) 電子封裝件及其製法
TWI645527B (zh) 電子封裝件及其製法
TWI611542B (zh) 電子封裝結構及其製法
US9907186B1 (en) Electronic package structure and method for fabricating the same
TW202135244A (zh) 電子封裝件
TWI765778B (zh) 電子封裝件及其製法
TWI640068B (zh) 電子封裝件及其製法
CN111725146A (zh) 电子封装件及其制法
TWI732509B (zh) 電子封裝件
TWI587465B (zh) 電子封裝件及其製法
TWI733142B (zh) 電子封裝件
TWI610402B (zh) 電子封裝結構及其製法
TWI645518B (zh) 封裝結構及其製法
TWI691041B (zh) 電子封裝件及其封裝基板與製法
TWI529898B (zh) 半導體封裝件及其製法
TWI612627B (zh) 電子封裝件及其製法
TWI634629B (zh) 電子封裝件及其製法
TWI570856B (zh) 封裝結構及其製法
TW201933563A (zh) 電子封裝件及其製法
TWI856575B (zh) 裸晶封裝、積體電路封裝及其製造方法
TW201822331A (zh) 電子封裝件
TW202249193A (zh) 電子封裝件及其製法
TWI570861B (zh) 封裝結構及其製法
TWI557844B (zh) 封裝結構及其製法
TW202339141A (zh) 裸晶封裝、積體電路封裝及其製造方法