TWI637465B - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TWI637465B
TWI637465B TW106118407A TW106118407A TWI637465B TW I637465 B TWI637465 B TW I637465B TW 106118407 A TW106118407 A TW 106118407A TW 106118407 A TW106118407 A TW 106118407A TW I637465 B TWI637465 B TW I637465B
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Taiwan
Prior art keywords
supporting structure
item
conductive
electronic package
scope
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TW106118407A
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English (en)
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TW201903980A (zh
Inventor
蔡國清
梁肇恩
陳信龍
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW106118407A priority Critical patent/TWI637465B/zh
Priority to CN201710450359.2A priority patent/CN108987355B/zh
Priority to US15/696,389 priority patent/US20180068870A1/en
Application granted granted Critical
Publication of TWI637465B publication Critical patent/TWI637465B/zh
Publication of TW201903980A publication Critical patent/TW201903980A/zh

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    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Abstract

一種電子封裝件及其製法，係於第一承載結構上透過結合層結合電子元件，再將該第一承載結構藉由複數導電元件堆疊於第二承載結構上，且令該電子元件電性連接該第二承載結構，使該第一承載結構與該第二承載結構之間的距離得以維持固定。

Description

電子封裝件及其製法
本發明係關於一種封裝結構，特別是關於一種電子封裝件及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品亦逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢發展，為因應此趨勢，半導體封裝業界遂開發各態樣的堆疊封裝(package on package，簡稱PoP)技術，以期能符合輕薄短小與高密度的要求。
如第1圖所示，習知堆疊式半導體封裝件1的製法係將半導體晶片11以複數銲錫凸塊110覆晶結合至一第一封裝基板10上，並於回銲該些銲錫凸塊110後進行第一次助銲劑清洗作業，再以底膠14包覆該些銲錫凸塊110，之後將第二封裝基板12藉由複數包含銲錫材之導電元件18支撐且電性連接於該第一封裝基板10上，再於回銲該些導電元件18後進行第二次助銲劑清洗作業，最後將封裝膠體13形成於該第一封裝基板10與第二封裝基板12之間以包覆該些導電元件18。
惟，習知半導體封裝件1中，該第一封裝基板10與第二封裝基板12之間的間隔係由該導電元件18所控制，故該導電元件18於回銲後之體積及高度之公差大，不僅接點容易產生缺陷，導致電性連接品質不良，而且該導電元件18所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該第一與第二封裝基板10,12之間呈傾斜接置，甚至產生接點偏移之問題。
再者，習知半導體封裝件1的製程較為複雜(例如需進行兩次助銲劑清洗作業)且製作成本較高。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝件，係包括：第一承載結構；電子元件，係透過結合層設於該第一承載結構上；第二承載結構，係藉由複數導電元件與該第一承載結構相堆疊，且電性連接該電子元件；以及包覆層，係形成於該第一承載結構與第二承載結構之間，以包覆該電子元件與該些導電元件。
本發明復提供一種電子封裝件之製法，係包括：將一電子元件透過結合層結合至一第一承載結構上；將該第一承載結構藉由複數導電元件堆疊於一第二承載結構上，且令該電子元件電性連接該第二承載結構；以及於該第一承載結構與該第二承載結構之間形成包覆該電子元件與該些 導電元件之包覆層。
前述之製法中，係包括：形成該些導電元件於該第一承載結構上；形成該包覆層於該第一承載結構上，以包覆該電子元件與該些導電元件，且令該導電元件之部分表面外露出該包覆層；以及將該第一承載結構藉由該些導電元件堆疊於該第二承載結構上，使該包覆層位於該第一承載結構與該第二承載結構之間。
前述之製法中，係包括：形成該些導電元件於該第一承載結構上；將該第一承載結構藉由該些導電元件堆疊於該第二承載結構上；以及形成該包覆層於該第一承載結構與該第二承載結構之間，以包覆該電子元件與該些導電元件。
前述之製法中，復包括將該第一承載結構藉由複數導電元件堆疊於該第二承載結構後，進行助銲劑清洗作業。
前述之電子封裝件及其製法中，該電子元件係藉由導電凸塊電性連接該第二承載結構。
前述之電子封裝件及其製法中，該包覆層復包覆該導電凸塊。
前述之電子封裝件及其製法中，該結合層係為黏著材、薄膜或散熱材。
前述之電子封裝件及其製法中，該導電元件係包含金屬塊與包覆該金屬塊之導電材。
前述之電子封裝件及其製法中，該包覆層與該第二承載結構之間形成有間隔。進一步，該導電元件之部分表面 係凸出該包覆層之部分表面，復包括形成絕緣層於該間隔中，以包覆該些導電元件。例如，該絕緣層與該包覆層係分佈於相同之區域內。另該電子元件具有相對之作用面與非作用面，該非作用面係結合該結合層，且該作用面係齊平該包覆層之表面。
由上可知，本發明之電子封裝件及其製法中，主要藉由該電子元件透過結合層結合至該第一承載結構上，使該第一承載結構與該第二承載結構之間的距離得以固定，故相較於習知技術，本發明於回銲該些導電元件後，該些導電元件所構成之接點能維持良好之電性連接品質，且該些導電元件所排列成之柵狀陣列之共面性良好，因而接點應力保持平衡而不會造成該第一與第二承載結構之間呈傾斜接置，以避免產生接點偏移之問題。
再者，本發明之製法僅需進行一次助銲劑清洗作業，故能減少助銲劑清洗之次數，因而能簡化製程及降低製作成本並提高產量。
1‧‧‧半導體封裝件
10‧‧‧第一封裝基板
11‧‧‧半導體晶片
110‧‧‧銲錫凸塊
12‧‧‧第二封裝基板
13‧‧‧封裝膠體
14‧‧‧底膠
18,28‧‧‧導電元件
2,3‧‧‧電子封裝件
20‧‧‧第一承載結構
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧導電凸塊
22‧‧‧第二承載結構
23,33‧‧‧包覆層
23a‧‧‧表面
24‧‧‧絕緣層
28a‧‧‧端部
280‧‧‧金屬塊
281‧‧‧導電材
29‧‧‧結合層
S‧‧‧間隔
A‧‧‧區域
d‧‧‧厚度
t‧‧‧高度
第1圖係為習知堆疊式半導體封裝件之剖面示意圖；第2A至2E圖係為本發明之電子封裝件之製法之剖面示意圖；以及第3A及3B圖係為本發明之電子封裝件之製法之另一實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之剖面示意圖。
如第2A圖所示，於一第一承載結構20上藉由一如黏著材、薄膜(film)或散熱材之結合層29接置至少一電子元件21。
於本實施例中，該第一承載結構20例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，其係於介電材上形成線路層，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該第一承載結構20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(leadframe)或矽中介板 (silicon interposer)，並不限於上述。
再者，該電子元件21係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如為半導體晶片，且該被動元件係例如為電阻、電容及電感。例如於本實施例中，該電子元件21係為半導體晶片，其具有相對之作用面21a與非作用面21b，該作用面21a上設有複數如銲錫材料之導電凸塊210，且該非作用面21b係結合該結合層29。
如第2B圖所示，形成複數導電元件28於該第一承載結構20上。
於本實施例中，該導電元件28係為具有銅核心的錫球，其包含金屬塊280與包覆該金屬塊280之導電材281，亦即該金屬塊280係為銅球，且該導電材281係為銲錫材，如鎳錫、錫鉛或錫銀。應可理解地，有關該導電元件28之種類繁多，例如，該導電元件28僅包含銅塊或銲錫凸塊，並不限於上述。
如第2C圖所示，形成一包覆層23於該第一承載結構20上以包覆該電子元件21與該些導電元件28，並使該些導電元件28之部分表面與該些導電凸塊210外露於該包覆層23。
於本實施例中，形成該包覆層23之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等，但並不限於上述。
再者，該包覆層23之表面23a係齊平該電子元件21之作用面21a。
又，於本實施例中，該導電凸塊210係完全凸出該包覆層23之表面23a，且該導電元件28係僅端部28a凸出該包覆層23之表面23a。當然於其它實施例中，該導電凸塊210亦可選擇部分表面外露出該包覆層23。
如第2D圖所示，將該第一承載結構20透過導電元件28結合至一第二承載結構22上，使該第一承載結構20堆疊於該第二承載結構22上，且該第二承載結構22與該包覆層23之間具有間隔S。
於本實施例中，該第二承載結構22例如為具有核心層與線路結構之封裝基板或無核心層之線路結構，其係於介電材上形成線路層，如扇出(fan out)型重佈線路層(RDL)。應可理解地，該第二承載結構22亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架，並不限於上述。
再者，該電子元件21係透過該導電凸塊210電性連接該第二承載結構22。
又，待回銲該些導電元件28與該些導電凸塊210，以令其結合至該第二承載結構22後，進行助銲劑清洗作業。
如第2E圖所示，形成一如底膠之絕緣層24於該間隔S中，以包覆該些導電元件28之端部28a與該些導電凸塊210。之後，可依需求進行切單製程。
於本實施例中，該絕緣層24係填滿該間隔S，使該絕緣層24與該包覆層23分佈於相同之區域A內。
再者，該絕緣層24之厚度d與該導電凸塊210之高度t(如第2A圖所示)相同。
於另一實施例中，如第3A至3B圖所示之電子封裝件3之製法，係接續於第2B圖之製程後，先將該第一承載結構20透過該導電元件28堆疊於該第二承載結構22上，再形成該包覆層33於該第一承載結構20與該第二承載結構22之間的剩餘空間，使該包覆層33包覆該電子元件21、該些導電元件28與該些導電凸塊210，藉此省略形成該絕緣層24之製程，其中，該包覆層33係填滿該第一承載結構20與該第二承載結構22之間的剩餘空間。
另外，該第一承載結構20之下側可結合且電性連接該電子元件21，另該第一承載結構20之上側亦可結合及電性連接至少一電子組件(圖略)，其中，該電子組件係為主動元件、被動元件或其二者組合等，且該主動元件係例如為半導體晶片，而該被動元件係例如為電阻、電容及電感。
本發明之製法僅需進行一次助銲劑清洗作業，故相較於習知技術，本發明之製法能減少一次助銲劑清洗，因而能簡化製程及降低製作成本並提高產量。
再者，該電子元件21透過該結合層29結合至該第一承載結構20上，能得到較佳的支撐效果。具體地，該第一承載結構20與該第二承載結構22之間的距離得以固定，因而能控制該些導電元件28的高度與體積，故相較於習知技術，於回銲該些導電元件28後，該些導電元件28所構成之接點能維持良好之電性連接品質，且該些導電元件28所排列成之柵狀陣列之共面性良好，致使接點應力保持平衡而不會造成該第一與第二承載結構20,22之間呈傾斜接 置，以避免產生接點偏移之問題。因此，本發明之製法能提高產品良率。
又，藉由該結合層29之設計，以於形成該包覆層23之模壓過程中，於該包覆層23之封裝材產生向上推擠力時，該結合層29亦可吸收應力，以減少該些導電元件28所承受的應力，故能避免該些導電元件28發生破裂。
另外，藉由如第2C至2D圖之製程，亦即先形成該包覆層23再進行堆疊之步驟流程，該電子封裝件2能得到更好的支撐效果。具體地，相較於該些導電元件28之整體高度與體積，該些導電元件28之端部28a的高度與體積較小，故於回銲該些導電元件28之端部28a後，該些導電元件28之端部28a所構成之接點能維持良好之電性連接品質，且該些導電元件28之端部28a所排列成之柵狀陣列之共面性良好，致使接點應力保持平衡而不會造成該第一與第二承載結構20,22之間呈傾斜接置，以避免產生接點偏移之問題。
本發明提供一種電子封裝件2,3，其包括：第一承載結構20、透過結合層29設於該第一承載結構20上之電子元件21、與該第一承載結構20相堆疊之第二承載結構22、以及包覆該電子元件21的包覆層23,33。
所述之第二承載結構22係藉由複數導電元件28與該第一承載結構20相堆疊。
所述之包覆層23,33係形成於該第一承載結構20與第二承載結構22之間，以包覆該電子元件21與該些導電元 件28。
於一實施例中，該電子元件21係藉由複數導電凸塊210電性連接該第二承載結構22。例如，該包覆層33復包覆該些導電凸塊210。
於一實施例中，該結合層29係為黏著材、薄膜或散熱材。
於一實施例中，該導電元件28係包含金屬塊280與包覆該金屬塊280之導電材281。
於一實施例中，該導電元件280之部分表面(如端部28a)凸出該包覆層23之表面23a。
於一實施例中，該包覆層23與該第二承載結構22之間形成有間隔S。進一步，復包括形成於該間隔S中之絕緣層24，係包覆該些導電元件28之端部28a，例如，該絕緣層24與該包覆層23分佈於相同之區域A內。
於一實施例中，該包覆層23之表面23a係齊平該電子元件21之作用面21a。
綜上所述，本發明之電子封裝件及其製法係藉由該電子元件透過結合層結合至該第一承載結構上，以得到較佳的支撐效果，且能提高產品良率。
再者，本發明之製法僅需進行一次助銲劑清洗作業，故能減少助銲劑清洗之次數，因而能簡化製程及降低製作成本並提高產量。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (23)

  1. 一種電子封裝件，係包括：第一承載結構；電子元件，係具有相對之作用面與非作用面，並以該非作用面透過結合層設於該第一承載結構上；第二承載結構，係藉由複數導電元件與該第一承載結構相堆疊，且電性連接該電子元件；導電凸塊，係設於該電子元件之該作用面上並與該第二承載結構結合；以及包覆層，係形成於該第一承載結構與第二承載結構之間，以包覆該電子元件與該些導電元件。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件係藉由該導電凸塊電性連接該第二承載結構。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層復包覆該導電凸塊。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該結合層係為黏著材、薄膜或散熱材。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該導電元件係包含金屬塊與包覆該金屬塊之導電材。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該包覆層與該第二承載結構之間形成有間隔。
  7. 如申請專利範圍第6項所述之電子封裝件，其中，該導電元件之部分表面凸出該包覆層之表面。
  8. 如申請專利範圍第7項所述之電子封裝件，復包括形成於該間隔中之絕緣層，以包覆該導電元件凸出該包覆層之部分表面。
  9. 如申請專利範圍第8項所述之電子封裝件，其中，該絕緣層與該包覆層分佈於相同之區域內。
  10. 如申請專利範圍第6項所述之電子封裝件，其中，該作用面係齊平該包覆層之表面。
  11. 一種電子封裝件之製法，係包括：將一電子元件透過結合層結合至一第一承載結構上，其中，該電子元件具有相對之作用面與非作用面，並以該非作用面透過結合層結合至第一承載結構上；將該第一承載結構藉由複數導電元件堆疊於一第二承載結構上，且將導電凸塊設於該電子元件之作用面上並與該第二承載結構結合，以令該電子元件電性連接該第二承載結構；以及於該第一承載結構與該第二承載結構之間形成包覆該電子元件與該些導電元件之包覆層。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該電子元件係藉由該導電凸塊電性連接該第二承載結構。
  13. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該包覆層復包覆該導電凸塊。
  14. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該結合層係為黏著材、薄膜或散熱材。
  15. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該導電元件係包含金屬塊與包覆該金屬塊之導電材。
  16. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該包覆層與該第二承載結構之間形成有間隔。
  17. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該導電元件之部分表面係凸出該包覆層之表面。
  18. 如申請專利範圍第17項所述之電子封裝件之製法，復包括形成絕緣層於該間隔中，以包覆該導電元件凸出該包覆層之部分表面。
  19. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該絕緣層與該包覆層係分佈於相同之區域內。
  20. 如申請專利範圍第16項所述之電子封裝件之製法，其中，該作用面係齊平該包覆層之表面。
  21. 如申請專利範圍第11項所述之電子封裝件之製法，復包括：形成該些導電元件於該第一承載結構上；形成該包覆層於該第一承載結構上，以包覆該電子元件與該些導電元件，且令該導電元件之部分表面外露出該包覆層；以及將該第一承載結構藉由該些導電元件堆疊於該第二承載結構上，使該包覆層位於該第一承載結構與該第二承載結構之間。
  22. 如申請專利範圍第11項所述之電子封裝件之製法，復包括：形成該些導電元件於該第一承載結構上；將該第一承載結構藉由該些導電元件堆疊於該第二承載結構上；以及形成該包覆層於該第一承載結構與該第二承載結構之間，以包覆該電子元件與該些導電元件。
  23. 如申請專利範圍第11項所述之電子封裝件之製法，復包括將該第一承載結構藉由複數導電元件堆疊於該第二承載結構後，進行助銲劑清洗作業。
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