CN111799242A - 封装堆叠结构及其制法与载板组件 - Google Patents
封装堆叠结构及其制法与载板组件 Download PDFInfo
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- CN111799242A CN111799242A CN201910492840.7A CN201910492840A CN111799242A CN 111799242 A CN111799242 A CN 111799242A CN 201910492840 A CN201910492840 A CN 201910492840A CN 111799242 A CN111799242 A CN 111799242A
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Abstract
一种封装堆叠结构及其制法与载板组件,通过于多个有机材基板的最上侧者设置电子元件,而其它有机材基板未接置有芯片,以将预计层数的线路层分别布设于该些有机材基板中,以经由该些有机材基板分散热应力,以避免最下侧有机材基板与电路板之间因CTE不匹配而相分离的问题。
Description
技术领域
本发明关于一种封装制程,特别是关于一种封装堆叠结构及其制法与载板组件。
背景技术
随着近年来可携式电子产品的蓬勃发展,各类相关产品也逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展。
如图1所示,其为现有电子装置1的剖视示意图。该电子装置1包括一如电路板的母板1b及安装于该母板1b上的电子封装件1a。该电子封装件1a包含一封装基板11、利用多个导电凸块100覆晶结合该封装基板11的半导体芯片10、及固定该半导体芯片10且包覆该些导电凸块100的底胶12。该电子封装件1a的封装基板11以多个焊球13接置于该母板1b上。
在半导体技术的发展中,因覆晶封装制程中的半导体芯片10(或该电子封装件1a)的尺寸有愈来愈大的趋势,因而造成该半导体芯片10于封装后会因应力集中而在各角落形成的芯片角落应力(Die Corner Stress)也愈来愈高,致使其与该底胶12之间会产生强大的应力,如图1所示的虚线圆圈处,导致该半导体芯片10会沿角落处发生破裂(Crack)。为解决此问题,业界一般使用超低(Ultra low)热膨胀系数(Coefficient of ThermalExpansion,简称CTE)的绝缘基材作为该封装基板11的板体,如铜箔复合材(copper cladlaminate,简称CCL)、ABF(Ajinomoto Build-up Film)、预浸材(Prepreg,简称PP)、防焊层(Solder Mask,简称SM)等的选材,以降低芯片角落应力(Die Corner Stress)。
然而,现有电子装置1中,该母板1b的板材的CTE并未配合该封装基板11变小,造成该封装基板11与该母板1b之间因CTE不匹配(mismatch)而相分离,进而存在该焊球13的连接可靠度(Reliability)的问题,造成该封装基板11无法有效电性连接该母板1b(如断路)或无法通过可靠度测试(如未完全接合),致使产品的良率不佳。
此外,因该封装基板11的尺寸会依据芯片数量需求增加而愈来愈大,且其层数也愈来愈高,故该封装基板11的制程良率也随之降低(即层数越多,误差越大),因而造成该封装基板11的制作成本剧增。例如,以十层线路层的封装基板11为例,每一层的线路层的制作良率约为95%,则十层的线路层的封装基板11的良率则为59.8%(即0.9510),故以现有制程难以完成该封装基板11的制作,恐需重新规划制程,因而大幅增加制程难度。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺陷,本发明提供一种封装堆叠结构及其制法与载板组件,
封装堆叠结构,包括:至少一电子元件;以及一具有多个线路层的载板组件,其包含有一具有第一线路部的第一有机材基板以及至少一具有第二线路部的第二有机材基板,且该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,其中,用以电性连接该电子元件的该多个线路层的层数分配于该第一线路部及该第二线路部中,且该电子元件接置于该第一有机材基板上并电性连接该多个线路层。
本发明还提供一种封装堆叠结构的制法,包括:提供一具有第一线路部的第一有机材基板及至少一具有第二线路部的第二有机材基板;接置至少一电子元件于该第一有机材基板上;以及将该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,以构成具有多个线路层的载板组件,并令该电子元件电性连接该多个线路层,其中,用以电性连接该电子元件的该多个线路层的层数分配于该第一线路部及该第二线路部中。
前述的封装堆叠结构及其制法中,该第一线路部的线路层的层数不同于该第二线路部的线路层的层数。
前述的封装堆叠结构及其制法中,该第一线路部的线路层的层数相同于该第二线路部的线路层的层数。
前述的封装堆叠结构及其制法中,还包括设置散热件于该第一有机材基板上。
前述的封装堆叠结构及其制法中,该第一有机材基板与多个该第二有机材基板相堆叠,且各该第二有机材基板之间经由多个支撑件相堆叠。
前述的封装堆叠结构及其制法中,该支撑体电性连接该第一有机材基板与第二有机材基板。
前述的封装堆叠结构及其制法中,还包括将该第二有机材基板经由多个导电元件堆叠于一电路板上。例如,该导电元件电性连接该电路板与该第二有机材基板,且该第二有机材基板的热膨胀系数介于该电路板的热膨胀系数与该第一有机材基板的热膨胀系数之间。另外,该第二有机材基板的热膨胀系数不同于该电路板的热膨胀系数。
前述的封装堆叠结构及其制法中,该第一有机材基板的热膨胀系数不同于该第二有机材基板的热膨胀系数。
本发明另提供一种载板组件,其配置有多个线路层,该载板组件包括:第一有机材基板,其具有第一线路部;以及第二有机材基板,其具有第二线路部,且该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,其中,该多个线路层的层数分配于该第一线路部及该第二线路部中。
前述的载板组件中,该第一线路部的线路层的层数不同于该第二线路部的线路层的层数。
前述的载板组件中,该第一线路部的线路层的层数相同于该第二线路部的线路层的层数。
前述的载板组件中,该第一有机材基板与多个该第二有机材基板相堆叠,且各该第二有机材基板之间经由多个支撑件相堆叠。进一步,还包括形成于各该第二有机材基板之间的包覆层,其包覆该多个支撑件。
前述的载板组件中,该支撑体电性连接该第一有机材基板与第二有机材基板。
前述的载板组件中,该第一有机材基板的热膨胀系数不同于该第二有机材基板的热膨胀系数。
前述的载板组件中,还包括包覆该多个支撑体的包覆层。
由上可知,本发明的封装堆叠结构及其制法与载板组件中,主要经由将预计层数的线路层分别布设于该第一与第二有机材基板中,故相比于现有技术,本发明可经由该第二有机材基板分散热应力,以避免该第一有机材基板与该电路板之间因CTE不匹配而相分离的问题,令该第二有机材基板能有效电性连接该电路板或能通过可靠度测试,进而提高产品的良率。
此外,即使线路层的层数愈来愈高,仍可经由将预计层数的线路层分别布设于该第一与第二有机材基板中,以提升制程良率,故能有效降低制作成本。
另外,经由该第一与第二有机材基板的CTE不相同,以令该封装堆叠结构的CTE逐步变化,而避免该封装堆叠结构因热应力变化过大而发生翘曲的问题。
附图说明
图1为现有电子装置的剖面示意图。
图2A至图2E为本发明的封装堆叠结构的制法的剖面示意图。
图3为本发明的封装堆叠结构的另一实施例的剖面示意图。
图4A及图4B为本发明的载板组件的不同实施例的剖面示意图。
符号说明
1 电子装置 1a 电子封装件
1b 母板 10 半导体芯片
100 导电凸块 11 封装基板
12,202 底胶 13 焊球
2,3 封装堆叠结构 2a,3a,4a,4b 载板组件
20 电子元件 20a 作用面
20b 非作用面 200 电极垫
201 导电凸块 21 第一有机材基板
21a 第一表面 21b 第二表面
21’ 第一线路部 210 第一绝缘层
211 第一线路层 22 第二有机材基板
22a 第一侧 22b 第二侧
22’ 第二线路部 220 第二绝缘层
221 第二线路层 23 散热件
23a 结合层 23b 粘着层
230 片体 231 脚部
24 支撑体 25 导电元件
26 电路板 30 支撑件
40 包覆层 S 空旷空间。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“第一”、“第二”、及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2E为本发明的封装堆叠结构2的制法的剖面示意图。
如图2A所示,提供一具有第一线路部21’的第一有机材基板21。
在本实施例中,该第一有机材基板21为具有核心层或无核心层(coreless)的线路结构,如封装基板(substrate),其定义有相对的第一表面21a与第二表面21b,且该第一线路部21’包含至少一第一绝缘层210与设于该第一绝缘层210上的第一线路层211。例如,以线路重布层(redistribution layer,简称RDL)方式形成扇出(fan out)型第一线路层211,其材质为铜,且形成该第一绝缘层210的材质为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材或如绿漆、石墨的防焊材。
如图2B所示,接置至少一电子元件20于该第一有机材基板21上,且令该电子元件20电性连接该第一线路部21’的第一线路层211。
在本实施例中,该电子元件20例如为封装件、主动元件、被动元件或其三者组合等,其中,该封装件为例如芯片级封装(Chip Scale Package,简称CSP),该主动元件为例如半导体芯片,该被动元件为例如电阻、电容及电感。在本实施例中,该电子元件20为主动元件,其具有相对的作用面20a与非作用面20b,该作用面20a具有多个电极垫200,使该些电极垫200经由多个如焊锡材料的导电凸块201以覆晶方式设于该第一有机材基板21的第一表面21a上且电性连接该第一线路层211,并以底胶202包覆该些导电凸块201;或者,该电子元件20可以其非作用面20b设于该第一有机材基板21的第一表面21a上且该些电极垫200经由多个焊线(图略)以打线方式电性连接该第一线路层211;亦或,该电子元件20可直接接触该第一线路层211以电性连接该第一线路层211。然而,有关该电子元件20电性连接该第一有机材基板21的方式不限于上述。
此外,有关该电子元件20的配置方式繁多,如设于该第一有机材基板21的第二表面21b,并无特别限制。
如图2C所示,可选择性设置一散热件23于该第一有机材基板21的第一表面21a上。
在本实施例中,该散热件23为金属构造并包含有片体230及脚部231,且以其片体230经由结合层23a结合于该电子元件20的非作用面20b上,并使该散热件23的脚部231经由粘着层23b架设于该第一有机材基板21的第一表面21a(或第一线路层211)上。例如,该结合层23a为导热介面材(Thermal Interface Material,简称TIM)、导热胶或其它适当材料,且该粘着层23b为绝缘胶、导电胶或其它适当材料等。
如图2D所示,将该第一有机材基板21经由多个支撑体24堆叠于至少一具有第二线路部22’的第二有机材基板22上,且该第二有机材基板22未接置有芯片,并使该第一与第二有机材基板21,22之间呈现有空旷空间S。
在本实施例中,该第二有机材基板22为具有核心层或无核心层(coreless)的线路结构,如封装基板(substrate),其定义有相对的第一侧22a与第二侧22b,以令该第一有机材基板21以其第二表面21b堆叠于该第二有机材基板22的第一侧22a上,且该第二线路部22’包含至少一第二绝缘层220与设于该第二绝缘层220上的第二线路层221。例如,以线路重布层(redistribution layer,简称RDL)方式形成扇出(fan out)型第二线路层221,其材质为铜,且形成该第二绝缘层220的材质为如聚对二唑苯(Polybenzoxazole,简称PBO)、聚酰亚胺(Polyimide,简称PI)、预浸材(Prepreg,简称PP)等的介电材或如绿漆、石墨的防焊材。
此外,该第一有机材基板21的热膨胀系数(Coefficient of Thermal Expansion,简称CTE)不同于(如小于)该第二有机材基板22的热膨胀系数。例如,当该第一线路部21’的第一线路层211的层数相同于该第二线路部22’的第二线路层221的层数时,经由形成该第一绝缘层210的材质不同于形成该第二绝缘层220的材质,以令该第一有机材基板21的热膨胀系数不同于该第二有机材基板22的热膨胀系数。
或者,当形成该第一绝缘层210的材质相同于形成该第二绝缘层220的材质时,经由该第一线路部21’的第一线路层211(或该第一绝缘层210)的层数不同于该第二线路部22’的第二线路层221(或该第二绝缘层220)的层数,以令该第一有机材基板21的热膨胀系数不同于该第二有机材基板22的热膨胀系数。
另外,该支撑体24为焊球(solder ball)、铜核心球或如铜材或金材等的金属件(如柱状、块状或针状)等,其电性连接该第一与第二有机材基板21,22。
如图2E所示,将该第二有机材基板22以其第二侧22b经由多个导电元件25接置于一电路板26上。
在本实施例中,该电路板26的绝缘板体的材质不同于该第一与第二绝缘层210,220的材质,且该第二有机材基板22的热膨胀系数不同于(如小于)该电路板26的热膨胀系数。
此外,该导电元件25为焊球(solder ball)、铜核心球或如铜材或金材等的金属件(如柱状、块状或针状)等,其电性连接该电路板26与该第二有机材基板22。
本发明的制法主要经由将预计层数的线路层分别布设于该第一有机材基板21与第二有机材基板22中,再将第一有机材基板21与第二有机材基板22以组合方式(如堆叠)构成所需线路层数量的载板组件2a,且该第一有机材基板21与第二有机材基板22的CTE不相同,故相比于现有技术,本发明的制法于该电路板26的CTE维持不变的情况下,可经由该第二有机材基板22缓冲该载板组件2a的整体热膨胀变形量,以避免该载板组件2a与该电路板26之间因CTE不匹配而相分离的问题,即避免该导电元件25的连接可靠度的问题,因而该第二有机材基板22能有效电性连接该电路板26或该载板组件2a能通过可靠度测试,进而提高产品的良率。
此外,即使该载板组件2a的尺寸依据芯片数量需求增加而愈来愈大,致使其线路层的层数愈来愈高,仍可经由将预计层数的线路层(第一与第二线路层211,221)分别布设于该第一与第二有机材基板21,22中,以提升该载板组件2a的制程良率,故能有效降低该载板组件2a的制作成本。
例如,以十层线路层的载板组件2a为例,可将七层的第一线路层211配置于该第一有机材基板21,而将三层的第二线路层221配置于该第二有机材基板22,若每一层的线路层的制作良率约为95%,则该第一有机材基板21的良率为68.8%(即0.957),而该第二有机材基板22的良率为85.7%(即0.953),故以现有制程即可完成该载板组件2a的制作,因而大幅降低制程成本。
应可理解地,也可将六层的第一线路层211配置于该第一有机材基板21,而将四层的第二线路层221配置于该第二有机材基板22;或者,可将五层的第一线路层211配置于该第一有机材基板21,而将五层的第二线路层221配置于该第二有机材基板22。因此,有关线路层的层数可依需求配置于该第一与第二有机材基板21,22中。
另外,于该封装堆叠结构2中,各板结构的排设可依CTE的大小依序,如由上而下依序为第一有机材基板21(CTE最小)、第二有机材基板22(CTE介于第一有机材基板与电路板之间)及电路板26(CTE最大),以令CTE由上往下逐步变化,而避免因热应力变化过大而发生翘曲的问题。
在另一实施例中,如图3所示的封装堆叠结构3,也可依良率需求,使该载板组件3a包含多个第二有机材基板22,且各该第二有机材基板22之间经由多个支撑件30相堆叠。例如,各该第二有机材基板22的热膨胀系数可相同或不相同,且该支撑件30为焊球(solderball)、铜核心球或如铜材或金材等的金属件(如柱状、块状或针状)等,其电性连接该电路板26与各该第二有机材基板22。具体地,若各该第二有机材基板22的热膨胀系数不相同时,各该第二有机材基板22的热膨胀系数的数值可由第一有机材基板21的侧朝向该电路板26的侧依序增大。
因此,若以十层线路层的载板组件3a为例,可将两层的第一线路层211配置于该第一有机材基板21,而将两层的第二线路层221配置于四个第二有机材基板22,若每一层的线路层的制作良率约为95%,则该第一有机材基板21的良率为90.3%(即0.952),而各该第二有机材基板22的良率为90.3%(即0.952),故以现有制程即可完成该载板组件3a的制作,因而大幅降低制程成本。
本发明还提供一种封装堆叠结构2,3,其包括:一第一有机材基板21、至少一电子元件20以及至少一第二有机材基板22。
所述的第一有机材基板21具有第一线路部21’。
所述的电子元件20接置于该第一有机材基板21上且电性连接该第一线路部21’。
所述的第二有机材基板22具有第二线路部22’且供该第一有机材基板21经由多个支撑体24堆叠于其上,其中,该第二有机材基板22未接置有芯片。
在一实施例中,该第一线路部21’的线路层的层数不同于该第二线路部22’的线路层的层数。
在一实施例中,该第一线路部21’的线路层的层数相同于该第二线路部22’的线路层的层数。
在一实施例中,该第一有机材基板21上设有散热件23。
在一实施例中,该第一有机材基板21与多个该第二有机材基板22相堆叠,且各该第二有机材基板22之间经由多个支撑件30相堆叠。
在一实施例中,该支撑体24电性连接该第一与第二有机材基板21,22。
在一实施例中,所述的封装堆叠结构2,3还包括一电路板26,供该第二有机材基板22经由多个导电元件25堆叠于其上。例如,该导电元件25电性连接该电路板26与该第二有机材基板22。另外,该第二有机材基板22的热膨胀系数不同于该电路板26的热膨胀系数。
在一实施例中,该第一有机材基板21的热膨胀系数不同于该第二有机材基板22的热膨胀系数。
请一并参见图4A及图4B,本发明还提供一种载板组件2a,3a,4a,4b,其配置有多个线路层,该载板组件2a,3a,4a,4b包括:至少一第一有机材基板21以及至少一第二有机材基板22。
所述的第一有机材基板21具有第一线路部21’。
所述的第二有机材基板22具有第二线路部22’,且该第一有机材基板21经由多个支撑体24堆叠于该第二有机材基板22上,其中,该载板组件2a,3a,4a,4b的多个线路层的层数分配于该第一线路部21’及该第二线路部22’中。
在一实施例中,该第一线路部21’的线路层的层数不同于该第二线路部22’的线路层的层数。
在一实施例中,该第一线路部21’的线路层的层数相同于该第二线路部22’的线路层的层数。
在一实施例中,该第一有机材基板21与多个该第二有机材基板22相堆叠,且各该第二有机材基板22之间经由多个支撑件30相堆叠。进一步,所述的载板组件4b还包括形成于各该第二有机材基板22之间的包覆层40,其包覆该多个支撑件30。具体地,该包覆层40为绝缘材,如聚酰亚胺(polyimide,简称PI)、干膜(dry film)、环氧树脂(epoxy)的封装胶体或封装材(molding compound)。
在一实施例中,该支撑体24电性连接该第一有机材基板21与第二有机材基板22。
在一实施例中,该第一有机材基板21的热膨胀系数不同于该第二有机材基板22的热膨胀系数。
在一实施例中,所述的载板组件4b还包括包覆该多个支撑体24的包覆层40。具体地,该包覆层40为绝缘材,如聚酰亚胺(PI)、干膜、环氧树脂的封装胶体或封装材。
综上所述,本发明的封装堆叠结构及其制法与载板组件,经由将预计层数的线路层分别布设于该第一与第二有机材基板中,且该第一与第二有机材基板的CTE不相同,故本发明能经由该第二有机材基板分散热应力,以避免该第一有机材基板与该电路板之间因CTE不匹配而相分离的问题,因而该第二有机材基板能有效电性连接该电路板或该第一及第二有机材基板能通过可靠度测试,进而提高产品的良率。
此外,即使线路层的层数需求多,仍可经由将预计层数的线路层分别布设于多个第二有机材基板中,以提升各有机材基板的制程良率,故能有效降低各有机材基板的制作成本。
另外,于该封装堆叠结构中,有机材基板与电路板可依CTE的大小依序排设,以避免因热应力变化过大而发生翘曲的问题。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (28)
1.一种封装堆叠结构,其特征在于,包括:
至少一电子元件;以及
一具有多个线路层的载板组件,其包含有一具有第一线路部的第一有机材基板以及至少一具有第二线路部的第二有机材基板,且该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,其中,该电子元件接置于该第一有机材基板上并电性连接该多个线路层,且用以电性连接该电子元件的该多个线路层的层数分配于该第一线路部及该第二线路部中。
2.根据权利要求1所述的封装堆叠结构,其特征在于,该第一线路部的线路层的层数不同于该第二线路部的线路层的层数。
3.根据权利要求1所述的封装堆叠结构,其特征在于,该第一线路部的线路层的层数相同于该第二线路部的线路层的层数。
4.根据权利要求1所述的封装堆叠结构,其特征在于,该第一有机材基板上设有散热件。
5.根据权利要求1所述的封装堆叠结构,其特征在于,该第一有机材基板与多个该第二有机材基板相堆叠,且各该第二有机材基板之间经由多个支撑件相堆叠。
6.根据权利要求1所述的封装堆叠结构,其特征在于,该支撑体电性连接该第一有机材基板与第二有机材基板。
7.根据权利要求1所述的封装堆叠结构,其特征在于,该结构还包括一电路板,其供该第二有机材基板经由多个导电元件堆叠于其上。
8.根据权利要求7所述的封装堆叠结构,其特征在于,该导电元件电性连接该电路板与该第二有机材基板。
9.根据权利要求7所述的封装堆叠结构,其特征在于,该第二有机材基板的热膨胀系数不同于该电路板的热膨胀系数,且该第二有机材基板的热膨胀系数介于该电路板的热膨胀系数与该第一有机材基板的热膨胀系数之间。
10.根据权利要求1所述的封装堆叠结构,其特征在于,该第一有机材基板的热膨胀系数不同于该第二有机材基板的热膨胀系数。
11.一种封装堆叠结构的制法,其特征在于,包括:
提供一具有第一线路部的第一有机材基板及至少一具有第二线路部的第二有机材基板;
接置至少一电子元件于该第一有机材基板上;以及
将该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,以构成具有多个线路层的载板组件,并令该电子元件电性连接该多个线路层,
其中,用以电性连接该电子元件的该多个线路层的层数分配于该第一线路部及该第二线路部中。
12.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该第一线路部的线路层的层数不同于该第二线路部的线路层的层数。
13.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该第一线路部的线路层的层数相同于该第二线路部的线路层的层数。
14.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该制法还包括设置散热件于该第一有机材基板上。
15.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该第一有机材基板与多个该第二有机材基板相堆叠,且各该第二有机材基板之间经由多个支撑件相堆叠。
16.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该支撑体电性连接该第一有机材基板与第二有机材基板。
17.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该制法还包括将该第二有机材基板经由多个导电元件堆叠于一电路板上。
18.根据权利要求17所述的封装堆叠结构的制法,其特征在于,该导电元件电性连接该电路板与该第二有机材基板。
19.根据权利要求17所述的封装堆叠结构的制法,其特征在于,该第二有机材基板的热膨胀系数不同于该电路板的热膨胀系数,且该第二有机材基板的热膨胀系数介于该电路板的热膨胀系数与该第一有机材基板的热膨胀系数之间。
20.根据权利要求11所述的封装堆叠结构的制法,其特征在于,该第一有机材基板的热膨胀系数不同于该第二有机材基板的热膨胀系数。
21.一种载板组件,其配置有多个线路层,其特征在于,该载板组件包括:
第一有机材基板,其具有第一线路部;以及
第二有机材基板,其具有第二线路部,且该第一有机材基板经由多个支撑体堆叠于该第二有机材基板上,其中,该多个线路层的层数分配于该第一线路部及该第二线路部中。
22.根据权利要求21所述的载板组件,其特征在于,该第一线路部的线路层的层数不同于该第二线路部的线路层的层数。
23.根据权利要求21所述的载板组件,其特征在于,该第一线路部的线路层的层数相同于该第二线路部的线路层的层数。
24.根据权利要求21所述的载板组件,其特征在于,该第一有机材基板与多个该第二有机材基板相堆叠,且各该第二有机材基板之间经由多个支撑件相堆叠。
25.根据权利要求24所述的载板组件,其特征在于,该载板组件还包括形成于各该第二有机材基板之间且包覆该多个支撑件的包覆层。
26.根据权利要求21所述的载板组件,其特征在于,该支撑体电性连接该第一有机材基板与第二有机材基板。
27.根据权利要求21所述的载板组件,其特征在于,该第一有机材基板的热膨胀系数不同于该第二有机材基板的热膨胀系数。
28.根据权利要求21所述的载板组件,其特征在于,该载板组件还包括包覆该多个支撑体的包覆层。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1547772A (zh) * | 2001-08-24 | 2004-11-17 | 3M | 具有降低的功率分配阻抗的互连模块 |
JP2005039241A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2005050878A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 積層型配線基板および電気装置並びにその実装構造 |
US20050189636A1 (en) * | 2003-12-17 | 2005-09-01 | Sergey Savastiouk | Packaging substrates for integrated circuits and soldering methods |
US8067829B2 (en) * | 2009-04-29 | 2011-11-29 | Bae Systems Information And Electronic Systems Integration Inc. | System and method for multi-chip module die extraction and replacement |
CN107863326A (zh) * | 2016-09-20 | 2018-03-30 | 联发科技股份有限公司 | 半导体封装结构及其形成方法 |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1547772A (zh) * | 2001-08-24 | 2004-11-17 | 3M | 具有降低的功率分配阻抗的互连模块 |
JP2005039241A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
JP2005050878A (ja) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | 積層型配線基板および電気装置並びにその実装構造 |
US20050189636A1 (en) * | 2003-12-17 | 2005-09-01 | Sergey Savastiouk | Packaging substrates for integrated circuits and soldering methods |
US8067829B2 (en) * | 2009-04-29 | 2011-11-29 | Bae Systems Information And Electronic Systems Integration Inc. | System and method for multi-chip module die extraction and replacement |
CN107863326A (zh) * | 2016-09-20 | 2018-03-30 | 联发科技股份有限公司 | 半导体封装结构及其形成方法 |
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