CN107863326A - 半导体封装结构及其形成方法 - Google Patents
半导体封装结构及其形成方法 Download PDFInfo
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- CN107863326A CN107863326A CN201710827237.0A CN201710827237A CN107863326A CN 107863326 A CN107863326 A CN 107863326A CN 201710827237 A CN201710827237 A CN 201710827237A CN 107863326 A CN107863326 A CN 107863326A
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Abstract
本发明实施例公开了一种半导体封装结构及其形成方法。其中该半导体封装结构包括:第一载体基板,具有第一表面与相对于该第一表面的第二表面;第二载体基板,堆叠在该第一载体基板上并且具有第三表面以及相对于该第三表面的第四表面,其中该第四表面面向该第一表面;半导体晶粒,安装于该第二载体基板的该第三表面上;以及散热器,设置在该第一载体基板的该第一表面上,以覆盖并围绕该第二载体基板与该半导体晶粒。本发明实施例,可以简化半导体封装结构以及降低其制造成本。
Description
技术领域
本发明涉及半导体封装技术,尤其涉及一种半导体封装结构及其形成方法。
背景技术
在半导体封装工业中,存在降低半导体封装的制造成本的需求。为了实现这种需求,发展了各种各样的封装结构设计。其中之一就是当前使用的倒装芯片(flip-chip)封装结构。性能需求以及使用倒装芯片设计能够实现更小的晶粒的能力驱动了倒装芯片封装结构在许多应用中被采用。
在倒装芯片封装结构中,形成有焊料凸块(solder bump)的半导体晶粒(也被称为IC(Integrated Circuit,集成电路)芯片或者芯片)一般直接接合至封装基板的金属垫。这些焊料凸块被固定至半导体晶粒的I/O接合垫。在封装期间,倒置该半导体晶粒,使得焊料凸块形成该半导体晶粒与该封装基板之间的电性互连。
为了确保电子产品的小型化与多功能性,具有小尺寸、高速操作以及具有高功能性的半导体封装受到期待。相应地,半导体晶粒利用封装基板来作为扇出(fan-out)层。
但是,为了响应I/O垫的增加,需要在封装基板中形成复杂的多层互连结构。如此,显著地增加了封装基板的制造成本,同时降低了封装基板的良品率。这些导致半导体封装结构在稳定性、良品率和生产量方面的下降,同时半导体封装结构的制造成本提高。
如此,一种创新的半导体封装结构受到期待。
发明内容
有鉴于此,本发明实施例提供了一种半导体封装结构及其形成方法,可以降低制造成本。
本发明实施例提供了一种半导体封装结构,包括:第一载体基板,具有第一表面与相对于该第一表面的第二表面;第二载体基板,堆叠在该第一载体基板上并且具有第三表面以及相对于该第三表面的第四表面,其中该第四表面面向该第一表面;半导体晶粒,安装于该第二载体基板的该第三表面上;以及散热器,设置在该第一载体基板的该第一表面上,以覆盖并围绕该第二载体基板与该半导体晶粒。
其中,进一步包括:封装材料,具有被该散热器覆盖的第一部分,其中该第一部分围绕该第二载体基板与该半导体晶粒。
其中,进一步包括:封装材料,具有围绕该散热器的外侧壁的第二部分。
其中,该第一部分覆盖该半导体晶粒的上表面。
其中,进一步包括:热界面材料层,附着于该半导体晶粒与该散热器之间。
其中,进一步包括:第一底部填充材料层,插入于该第一载体基板与该第二载体基板之间;及/或,第二底部填充材料层,插入于该半导体晶粒与该第二载体基板之间。
其中,进一步包括:第一底部填充材料层,插入于该第一载体基板与该第二载体基板之间;以及第二底部填充材料层,插入于该半导体晶粒与该第二载体基板之间;其中,一间隙围绕该半导体晶粒、该第二载体基板、该第一底部填充材料层以及该第二底部填充材料层。
其中,进一步包括:电容,安装于该第一载体基板的该第一表面上,该二载体基板的该第三表面上,或者该第二载体基板的该第四表面上。
本发明实施例提供了一种半导体封装结构,包括:第一载体基板,具有第一表面与相对于该第一表面的第二表面;第二载体基板,堆叠在该第一载体基板上并且具有第三表面以及相对于该第三表面的第四表面,其中该第四表面面向该第一表面;半导体晶粒,安装于该第二载体基板的该第三表面上;第一封装材料,设置在该第二载体基板的该第三表面上并且围绕该半导体晶粒;以及散热器,设置在该第一载体基板的该第一表面上,以覆盖并围绕该第二载体基板与该第一封装材料。
其中,进一步包括:第二封装材料,具有被该散热器覆盖的第一部分,其中该第一部分围绕该第二载体基板与该第一封装材料。
其中,进一步包括:第二封装材料,具有围绕该散热器的外侧壁的第二部分。
其中,进一步包括:一热界面材料层,附着于该半导体晶粒与该散热器之间。
其中,进一步包括:底部填充材料,插入在该半导体晶粒与该第二载体基板之间,并且该第一封装材料围绕该底部填充材料。
其中,该第一封装材料覆盖该半导体晶粒的上表面。
其中,进一步包括:底部填充材料,插入在该第一载体基板与该第二载体基板之间。
其中,进一步包括:底部填充材料,插入在该第一载体基板与该第二载体基板之间,其中一间隙围绕该第一封装材料,该第二载体基板以及该底部填充材料。
其中,进一步包括:电容,安装于该第一载体基板的该第一表面上,该二载体基板的该第三表面上,或者该第二载体基板的该第四表面上。
其中,该第一载体基板为单层封装结构且该第二载体基板为双层封装结构。
本发明实施例提供了一种形成半导体封装结构的方法,包括:提供第一载体基板以及第二载体基板,其中该第一载体基板具有第一表面与相对于该第一表面的第二表面,该第二载体基板具有第三表面以及相对于该第三表面的第四表面;将该第二载体基板堆叠于该第一载体基板上,其中该第四表面面向该第一表面;在该第三表面上堆叠半导体晶粒;以及在该第一表面上形成散热器以覆盖并围绕该第二载体基板与该半导体晶粒。
本发明实施例的有益效果是:
本发明实施例,可以简化半导体封装结构以及降低半导体封装结构的制造成本。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例,能够更全面地理解本发明,其中:
图1A~1E为根据本发明实施例的形成半导体封装结构的方法的各个阶段的剖面示意图;
图1E-1为根据本发明实施例的半导体封装结构的剖面示意图;
图1E-2为根据本发明实施例的半导体封装结构的剖面示意图;
图2A~2F为根据本发明实施例的形成半导体封装结构的方法的各个阶段的剖面示意图;
图3为根据本发明实施例的半导体封装结构的剖面示意图;
图4为根据本发明实施例的半导体封装结构的剖面示意图;
图5为根据本发明实施例的半导体封装结构的剖面示意图;
图6为根据本发明实施例的半导体封装结构的剖面示意图;
图7为根据本发明实施例的半导体封装结构的剖面示意图;
图8为根据本发明实施例的半导体封装结构的剖面示意图;
图9为根据本发明实施例的半导体封装结构的剖面示意图;
图10为根据本发明实施例的半导体封装结构的剖面示意图;
图11为根据本发明实施例的半导体封装结构的剖面示意图;
图12为根据本发明实施例的半导体封装结构的剖面示意图;
图13为根据本发明实施例的半导体封装结构的剖面示意图;
图14为根据本发明实施例的半导体封装结构的剖面示意图;
图15为根据本发明实施例的半导体封装结构的剖面示意图;
图16为根据本发明实施例的半导体封装结构的剖面示意图;
图17为根据本发明实施例的半导体封装结构的剖面示意图。
具体实施方式
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解,硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式,而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语,故应解释成“包括(含)但不限定于”。另外,“耦接”一词在此为包括任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表该第一装置可直接电气连接至该第二装置,或透过其它装置或连接手段间接地电气连接至该第二装置。
以下描述为实现本发明的较佳预期方式。该描述仅出于说明本发明的一般原理的目的,并且不意味着限制。本发明的范围可以通过参考所附的权利要求来确定。
本发明将通过参考特定实施例与确定的附图的方式来描述,但是本发明不限制于此,并且本发明仅由权利要求来限制。描述的附图仅是原理图,并且不意味着限制。在附图中,出于说明目的以及非按比例绘制,夸大了一些元件的尺寸。附图中的尺寸与相对尺寸不对应本发明实践中的真实尺寸。
本发明实施例涉及半导体封装结构,特别是具有高成本效应的扇出封装结构及其形成方法,具体内容将详述如下。
图1E为根据本发明实施例的半导体封装结构10a的剖面示意图。在一些实施例中,该半导体封装结构10a为晶圆级半导体封装结构,例如,扇出晶圆级半导体封装结构。在一个实施例中,该扇出晶圆级半导体封装结构可以包括:倒装芯片封装结构。
参考图1E,该半导体封装结构10a可以安装于基座(未示出)上,诸如PCB(PrintedCircuit Board,印刷电路板),该基座可以由PP(polypropylene,聚丙烯)、PBO(polybenzoxazole,聚苯并恶唑)或者聚酰亚胺(polyimide)来形成。在一些实施例中,该基座可以为单层或者多层结构。多个导电垫以及多条电性耦接至该多个导电垫的导电迹线(trace)一般设置在该基座的顶面上及/或该基座中。在此情形中,该多条导电迹线可以用于该半导体封装结构10a的I/O(Input/output,输入/输出)连接。在一些实施例中,该半导体封装结构10a通过接合工艺(bonding process)安装于该基座上。例如,该半导体封装10a包括:至少一凸块110,通过接合工艺安装在该基座上并且电性耦接至该基座。
在一些实施例中,该半导体封装结构10a包括:第一载体基板100,堆叠在该第一载体基板100上的第二载体基板200,以及安装于该第二载体基板200上的半导体晶粒300。例如,该第一载体基板100具有第一表面100a以及与之相对的第二表面100b。另外,该第二载体基板200具有第一表面200a以及与之相对的第二表面200b。该第二载体基板200可以堆叠(stack)在该第一载体基板100上,使得该第二载体基板200的第二表面200b面向该第一载体基板100的第一表面100a。另外,该半导体晶粒300安装于该第二载体基板200的该第一表面200a上。
该第一载体基板100与该第二载体基板200可以充当该半导体晶粒300的扇出层并且也可以被称为封装基板。在一些实施例中,该第一载体基板100为单层封装基板以及该第二载体基板200为双层封装基板。在这些情形中,该第一载体基板100可以包括:绝缘层102以及导电迹线101与105,其中导电迹线101与105通过导电通孔(conductive via)103彼此电性耦接。导电迹线101与105分别设置在绝缘层102的底面和顶面上(即,第一载体基板100的第二表面100b与第一表面100a),并且导电通孔103设置在绝缘层102中。另外,第二载体基板200可以包括:绝缘层202与204以及导电迹线201,205与209,其中导电迹线201,205与209通过导电通孔203与207彼此电性耦接。例如,导电迹线201设置在绝缘层202的底面上(即第二载体基板200的第二表面200b)。导电迹线209设置在绝缘层204的顶面上(即第二载体基板200的第一表面200a)。导电迹线205设置在绝缘202的顶面上或者绝缘层204的底面上。另外,导电通孔203设置在导电迹线201与205之间的绝缘层202中。另外,导电通孔207设置在导电迹线205与209之间的绝缘层204中。在一些实施例中,绝缘层102,202与204可以由有机材料形成,例如聚合物基材料(如PP、PBO或者聚酰亚胺)或类似物。
在一些实施例中,该第二载体基板200通过至少一导电结构210(诸如焊球)电性耦接至该第一载体基板100。另外,该第二载体基板200通过至少一导电结构310(诸如焊料凸块)电性耦接至该半导体晶粒300。
在一些实施例中,该半导体晶粒300(诸如SOC(System-On-Chip,片上系统)晶粒)可以包括:逻辑晶粒,该逻辑晶粒包括:CPU(Central Processing Unit,中央处理单元)、GPU(Graphics Processing Unit,图像处理单元)、DRAM(Dynamic Random Access Memory,动态随机存取存储器)控制器或者他们的任意组合。可选地,该半导体晶粒300可以包括:调制解调器晶粒(modem die)。
在一些实施例中,该半导体封装结构10a进一步包括:散热器(heat spreader)415,设置在该第一载体基板100的第一表面100a上,以便于在该散热器415与该第一表面100a之间形成一空腔。例如,该散热器415通过粘合层(adhesive layer)412(诸如TIA(Thermal Interface Adhesive,热界面粘合剂)层)固定在该第一载体基板100的第一表面100a上。该散热器415覆盖并且围绕位于该空腔中的第二载体基板200以及半导体晶粒300。另外,TIM(Thermal Interface Material,热界面材料)层410可以附着在半导体晶粒300与散热器415之间。如此,半导体晶粒300产生的热可以通过TIM层传导至散热器415以及通过第二载体基板200、第一载体基板100与粘合层412传导至散热器415。
在一些实施例中,该半导体封装结构10a进一步包括:封装材料(encapsulatingmaterial)420,具有第一部分420a与第二部分420b。该散热器415覆盖封装材料420的第一部分420a,使得该第一部分420a围绕该第二载体基板200与该半导体晶粒300。另外,该封装材料420的第一部分420a填充该半导体晶粒300与该第二载体基板200之间的间隙以及该第二载体基板200与该第一载体基板100之间的间隙。另外,该封装材料420的第二部分420b围绕该散热器415的外侧壁(exterior sidewall)415a,并且露出该散热器415的覆盖该第一部分420a以及该半导体晶粒300的部分。可选地,形成的封装材料420仅被散热器415覆盖而没有围绕散热器415的外侧壁415a。
在一些实施例中,该封装材料420可以为模塑料,该封装材料420(或模塑料)可以由环氧树脂、树脂、可塑聚合物或类似物来形成。可以施加诸如以环氧树脂或者树脂形式的封装材料420,虽然其基本上为液体,但是随后可以通过化学反应固化。在其他的一些实施例中,该封装材料420可以为UV(ultraviolet,紫外)或者热固化聚合物,作为能够设置在散热器周围的以及设置在散热器415与第一载体基板100所创建的空腔中的胶体或可塑固体而施加,并且随后通过UV或者热固化工艺来固化。该封装材料420可以按照模型(未示出)来固化。在一些实施例中,半导体晶粒300产生的热也可以通过封装材料420传导至散热器415。
在一些实施例中,该半导体封装结构10a进一步包括:一个或者多个被动元件220,诸如电容,安装在第二载体基板200的第二表面200b上并且直接位于半导体晶粒300的下方。为了简化示图,仅描绘了一个被动元件。封装材料220可以围绕并支撑被动元件220。如此,可以防止被动元件220在执行热工艺(如回流工艺)之后掉落。
可选地,被动元件220可以安装在第二载体基板200的第一表面200a上,并且接近载体基板200的边缘,如图1E-1所示的半导体封装结构10a’中所示。在其他的一些实施例中,被动元件220安装于第一载体基板100的第一表面100a上并且直接位于半导体晶粒300的下方,如图1E-2所示的半导体封装结构10a”中所示。可选地,安装于该第一载体基板100的第一表面100a上的被动元件220可以接近该第一载体基板100的边缘。
图2F为根据本发明实施例的半导体封装结构20a的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前已参考图1E描述了的,出于简洁而省略。在本实施例中,该半导体封装结构20a类似于图1E所示的半导体封装结构10a。如图2F所示,不同于半导体封装结构10a,半导体封装结构20a包括:封装材料230,设置在第二载体基板200的第一表面200a上并且围绕半导体晶粒300。封装材料420的第一部分420a围绕该封装材料230。另外,散热器415围绕并覆盖封装材料230。
另外,不同于半导体封装结构10a,半导体封装结构20a中的TIM层410的边缘基本对齐封装材料230的边缘。可选地,TIM层410的边缘可以基本对齐半导体晶粒300的边缘。
在一些实施例中,被动元件220可以安装于第二载体基板200的第一表面200a上并且接近第二载体基板200的边缘,正如图1E-1所示的被动元件220的布置。在其他的一些实施例中,被动元件220可以安装于第一载体基板100的第一表面100a上并且直接位于半导体晶粒300的下方,如图1E-2所示的被动元件220的布置。可选地,安装在第一载体基板100的第一表面100a上的被动元件220可以接近第一载体基板100的边缘。
图3为根据本发明实施例的半导体封装结构10b的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图1E已描述了的,出于简洁而省略。在本实施例中,半导体封装结构10b类似于图1E所示的半导体封装结构10a。如图3所示,不同于半导体封装结构10a,半导体封装结构10b中没有插入在散热器415与半导体晶粒300之间的TIM层410。在本实施例中,封装材料420的第一部分420a插入在散热器415与半导体晶粒300之间,以覆盖半导体晶粒300的上表面。
图4为根据本发明实施例的半导体封装结构10c的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图1E已描述了的,出于简洁而省略。在本实施例中,半导体封装结构10c类似于图1E所示的半导体封装结构10a。如图4所示,不同于半导体封装结构10a,半导体封装结构10c包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间,使得该底部填充材料层430a围绕导电结构210与被动元件220。
图5为根据本发明实施例的半导体封装结构10d的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图1E已描述了的,出于简洁而省略。在本实施例中,半导体封装结构10d类似于图1E所示的半导体封装结构10a。如图5所示,不同于半导体封装结构10a,半导体封装结构10d包括:底部填充材料层430b,插入在半导体晶粒300与第二载体基板200之间,使得该底部填充材料层430b围绕导电结构310。
图6为根据本发明实施例的半导体封装结构10e的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图1E已描述了的,出于简洁而省略。在本实施例中,半导体封装结构10e类似于图1E所示的半导体封装结构10a。如图6所示,不同于半导体封装结构10a,半导体封装结构10e包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间,以及底部填充材料层430b,插入在半导体晶粒300与第二载体基板200之间,使得该底部填充材料层430b围绕导电结构210与被动元件220以及该底部填充材料层430a围绕导电结构310。
图7为根据本发明实施例的半导体封装结构10f的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图6已描述了的,出于简洁而省略。在本实施例中,半导体封装结构10f类似于图6所示的半导体封装结构10e。如图7所示,不同于半导体封装结构10e,半导体封装结构10f不具有封装材料420。相应地,形成围绕TIM层410,半导体晶粒300,第二载体基板200以及底部填充材料层430a与430b的间隙450。
图8为根据本发明实施例的半导体封装结构20b的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图2F已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20b类似于图2F所示的半导体封装结构20a。如图8所示,不同于半导体封装结构20a,半导体封装结构20b包括:底部填充材料层430b,插入在半导体晶粒300与第二载体基板200之间并且封装材料230围绕该底部填充材料层430b,其中底部填充材料层430b围绕导电结构310。
图9为根据本发明实施例的半导体封装结构20c的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图8已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20c类似于图8所示的半导体封装结构20b。如图9所示,不同于半导体封装结构20b,半导体封装结构20c不具有插入在散热器415与半导体晶粒300之间的TIM层410。在本实施例中,封装材料230插入在散热器415与半导体晶粒300之间,以覆盖半导体晶粒300的上表面。
图10为根据本发明实施例的半导体封装结构20d的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图8已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20d类似于图8所示的半导体封装结构20b。如图10所示,不同于半导体封装结构20b,半导体封装结构20d包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间并且被封装材料420的第一部分420a围绕。
图11为根据本发明实施例的半导体封装结构20e的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图9已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20e类似于图9所示的半导体封装结构20c。如图11所示,不同于半导体封装结构20c,半导体封装结构20e包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间并且被封装材料420的第一部分420a围绕。
图12为根据本发明实施例的半导体封装结构20f的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图2F已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20f类似于图2F所示的半导体封装结构20a。如图12所示,不同于半导体封装结构20a,半导体封装结构20f包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间并且被封装材料420的第一部分420a围绕。
图13为根据本发明实施例的半导体封装结构20g的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图2F已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20g类似于图2F所示的半导体封装结构20a。如图13所示,不同于半导体封装结构20a,半导体封装结构20g包括:底部填充材料层430a,插入在第一载体基板100与第二载体基板200之间并且被封装材料420的第一部分420a围绕。另外,半导体封装结构20g不具有插入在散热器415与半导体晶粒300之间的TIM层410。在本实施例中,封装材料230插入在散热器415与半导体晶粒300之间,以覆盖半导体晶粒300的上表面。
图14为根据本发明实施例的半导体封装结构20h的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图10已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20h类似于图10所示的半导体封装结构20d。如图14所示,不同于半导体封装结构20d,半导体封装结构20h不具有封装材料420。相应地,形成围绕TIM层410,封装材料230,第二载体基板200以及底部填充材料层430a的间隙450。
图15为根据本发明实施例的半导体封装结构20i的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图11已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20i类似于图11所示的半导体封装结构20e。如图15所示,不同于半导体封装结构20e,半导体封装结构20i不具有封装材料420。相应地,形成围绕TIM层410,封装材料230,第二载体基板200以及底部填充材料层430a的间隙450。
图16为根据本发明实施例的半导体封装结构20j的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图12已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20j类似于图12所示的半导体封装结构20f。如图16所示,不同于半导体封装结构20f,半导体封装结构20j不具有封装材料420。相应地,形成围绕TIM层410,封装材料230,第二载体基板200以及底部填充材料层430a的间隙450。
图17为根据本发明实施例的半导体封装结构20k的剖面示意图。以下实施例中描述的元件,有相同或者类似于先前参考图13已描述了的,出于简洁而省略。在本实施例中,半导体封装结构20k类似于图13所示的半导体封装结构20g。如图17所示,不同于半导体封装结构20g,半导体封装结构20k不具有封装材料420。相应地,形成围绕TIM层410,封装材料230,第二载体基板200以及底部填充材料层430a的间隙450。
图1A~1E为根据本发明实施例的形成半导体封装结构10a的方法的各个阶段的剖面示意图。额外的操作可以在图1A~1E中描述的各个阶段之前、期间及/或之后提供。对于不同实施例,描述的各个阶段中的一部分可以被替换或者忽略。额外的特征可以添加至该半导体封装结构10a。对于不同实施例,以下描述的特征中的一部分可以被替换或者忽略。
如图1A所示,提供第一载体基板100以及第二载体基板200,其中该第一载体基板100具有第一表面100a以及与该第一表面100a相对的第二表面100b,该第二载体基板200具有第一表面200a以及与该第一表面200a相对的第二表面200b。在一些实施例中,该第一载体基板100为单层封装基板并且该第二载体基板200为双层封装基板。在这些情形中,该第一载体基板100可以包括:绝缘层102以及导电迹线101与105,其中导电迹线101与105通过导电通孔103彼此电性耦接。导电迹线101与105分别设置在绝缘层102的底面和顶面上(即,第一载体基板100的第二表面100b与第一表面100a),并且导电通孔103设置在绝缘层102中。
另外,第二载体基板200可以包括:绝缘层202与204以及导电迹线201,205与209,其中导电迹线201,205与209通过导电通孔203和207彼此电性耦接。例如,导电迹线201设置在绝缘层202的底面上(即第二载体基板200的第二表面200b)。导电迹线209设置在绝缘层204的顶面上(即第二载体基板200的第一表面200a)。导电迹线205设置在绝缘层202的顶面上或者绝缘层204的底面上。另外,导电通孔203设置在导电迹线201与205之间的绝缘层202中。另外,导电通孔207设置在导电迹线205与209之间的绝缘层204中。另外,导电结构210(如焊球)以及至少一个被动元件220(诸如电容)安装在载体基板200的第二表面200b上。在其他的一些实施例中,被动元件220可以安装在第二载体基板200的第一表面200b上或者安装在第一载体基板100的第一表面100a上。
接着,将第二载体基板200堆叠在第一载体基板100上,使得第二载体基板200的第二表面200b面向该第一载体基板100的第一表面100a以及通过导电结构210电性耦接至第一载体基板100。
如图1B所示,提供半导体晶粒300。在一些实施例中,该半导体晶粒300(诸如SOC晶粒)可以包括:逻辑晶粒,该逻辑晶粒包括:CPU、GPU、DRAM控制器或者他们的任意组合。可选地,该半导体晶粒300可以包括:调制解调器晶粒(modem die)。接着,将该半导体晶粒300堆叠在第二载体基板200的第一表面200a上,使得第二载体基板200通过导电结构310(如焊料凸块)电性耦接至半导体晶粒300。在一些实施例中,在将第二载体基板200与半导体晶粒300依序地堆叠在第一载体基板100上之后,执行回流(reflow)工艺,使得该第二载体基板200通过导电结构210安装至该第一载体基板100上以及该半导体晶粒300通过导电结构310安装至该第二载体基板200上。
如图1C所示,通过各自的点胶工艺(dispensing process),将可选的TIM层410形成于该半导体晶粒300上,以及将粘合层412(诸如TIA层)形成于该第一载体基板100的第一表面100a上。之后,散热器415形成于TIM层410以及第一载体基板100的第一表面100a上,以便于在散热器415与第一载体基板100之间形成空腔。在一些实施例中,对该TIM层410以及该粘合层412执行固化工艺,使得散热器415通过该粘合层412固定在该第一载体基板100的第一表面100a上以及通过该TIM层410附着至半导体晶粒300。第二载体基板200与半导体晶粒300处于空腔中,使得散热器415覆盖并围绕该第二载体基板200与该半导体晶粒300。
如图1D所示,封装材料420,诸如模塑料,形成于该第一载体基板100上。在一些实施例中,该封装材料420具有第一部分420a以及第二部分420b。该封装材料420的第一部分420a位于该散热器415与该第一载体基板100创建的空腔内,使得该封装材料420的第一部分420a被散热器415覆盖,以及使得该第一部分420a围绕该第二载体基板200以及该半导体晶粒300。另外,半导体晶粒300与第二载体基板200之间的间隙以及第二载体基板200与第一载体基板100之间的间隙被该封装材料420的第一部分420a填充。另外,封装材料420的第二部分420b围绕该散热器415的外侧壁(exterior sidewall)415a,并且露出该散热器415的覆盖该封装材料420的第一部分420a以及半导体晶粒300的部分。可选地,封装材料420仅被散热器415覆盖而没有围绕散热器415的外侧壁415a。
如图1E所示,在第一载体基板100的第二表面100b上形成凸块110(如焊球),以便于完成半导体封装结构10a的制造。
图2A~2F为根据本发明实施例的形成半导体封装结构20a的方法的各个阶段的剖面示意图。以下实施例描述的元件,有相同或者类似于先前参考图1A~1E已描述了的,出于简洁而省略。额外的操作可以在图2A~2F中描述的各个阶段之前、期间及/或之后提供。对于不同实施例,描述的各个阶段中的一部分可以被替换或者忽略。额外的特征可以添加至半导体封装结构20a。对于不同实施例,以下描述的特征中的一部分可以被替换或者忽略。
如图2A所示,提供第二载体基板200以及半导体晶粒300,其中该第二载体基板200具有第一表面200a以及与该第一表面200a相对的第二表面200b。接着,将该半导体晶粒300堆叠在该第二载体基板200的第一表面200a上,使得该第二载体基板200通过导电结构310(诸如焊料凸块)电性耦接至半导体晶粒300。在一些实施例中,在半导体晶粒300堆叠在第二载体基板200之后,执行回流工艺,使得该半导体晶粒300通过导电结构310安装至第二载体基板200上。
如图2B所示,封装材料230,如模塑料,形成于该第二载体基板200的第一表面200a上,以围绕该半导体晶粒300以及露出半导体晶粒300的上表面。另外,半导体晶粒300与第二载体基板200之间的间隙由封装材料230填充。之后,将导电结构210(如焊球)和至少一个被动元件(如电容)安装至载体基板200的第二表面200b上。在其他的一些实施例中,被动元件220可以安装在第二载体基板200的第一表面200b上。
如图2C所示,提供第一载体基板100,其中该第一载体基板100具有第一表面100a以及与该第一表面100a相对的第二表面100b。具有半导体晶粒300和封装材料230的第二载体基板230堆叠在该第一载体基板100的第一表面100a上。在一些实施例中,在将图2B所示的结构堆叠至第一载体基板100之后,执行回流工艺,使得具有半导体晶粒300和封装材料230的第二载体基板230通过导电结构210安装至第一载体基板100上。
如图2D所示,通过分别的点胶工艺将可选的TIM层410形成于该半导体晶粒300上,以及将粘合层412(诸如TIA层)形成于该第一载体基板100的第一表面100a上。在一些实施例中,TIM层410的边缘400a基本对齐于封装材料230的边缘230a。
之后,将散热器415形成于TIM层410以及第一载体基板100的第一表面100a上,以便于在散热器415与第一载体基板100之间形成一空腔。在一些实施例中,对该TIM层410以及粘合层412执行固化工艺,使得散热器415通过该粘合层412固定在该第一载体基板100的第一表面100a上以及通过该TIM层410附着至半导体晶粒300和封装材料230。第二载体基板200与半导体晶粒300处于空腔中,以便于被散热器415覆盖并围绕。
如图2E所示,封装材料420,诸如模塑料,形成于该第一载体基板100上。在一些实施例中,被动元件220不安装于第二载体基板200上并且可以在形成封装材料420之前,安装于第一载体基板100的第一表面100a上。
在一些实施例中,封装材料420具有第一部分420a与第二部分420b。该封装材料420的第一部分420a被散热器415覆盖,并且该第一部分420a围绕该第二载体基板200与该封装材料230。另外,第二载体基板200与第一载体基板100之间的间隙由该封装材料420的第一部分420a填充。另外,封装材料420的第二部分420b围绕该散热器415的外侧壁(exterior sidewall)415a,并且露出该散热器415的覆盖该封装材料420的第一部分420a、封装材料230以及半导体晶粒300的部分。可选地,封装材料420仅被散热器415覆盖而没有围绕散热器415的外侧壁415a。
如图2F所示,在第一载体基板100的第二表面100b上形成凸块110(如焊球),以便于完成半导体封装结构20a的制造。
尽管图1A~1E示出了形成半导体封装结构10a的方法以及图2A~2F示出了形成半导体封装结构20a的方法,但是图3~7分别示出的的半导体封装结构10b~10f以及图8~17分别示出的半导体封装结构20b~20k可以由与形成半导体封装结构10a或20a的方法相同或者类似的方法来制造。
根据前述实施例,由于半导体封装结构利用第一与第二载体基板的组合(即封装基板)来作为半导体封装结构中的半导体晶粒扇出层,因此相比于传统的仅利用单个封装基板(具有复杂的多层互连结构于其中)来作为扇出层的方案相比,可以降低封装基板中的互连层的数量以及封装基板的整个厚度,从而简化半导体封装结构以及降低半导体封装结构的制造成本。
在半导体封装结构中,围绕半导体晶粒并且被散热器覆盖的封装材料可以提供垂直和横向的散热路径。如此,可以增加半导体封装结构的可靠性。另外,由于封装材料形成于第一载体基板上并且封装第二载体基板,因此可以消除或改善半导体封装结构的翘曲(warpage)问题。
另外,由于被动元件可以安装于第一载体基板的上表面、第二载体基板的上表面,或者第二载体基板的下表面上,因此可以增加第一与第二载体基板之间的导电结构(如焊球)的设计灵活性。另外,在被动元件安装于第二载体基板的下表面的情形中,封装材料可以保护和支撑被动元件。如此,可以防止被动元件掉落,从而处理被动元件或第二载体基板的返工(rework)问题。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (19)
1.一种半导体封装结构,其特征在于,包括:
第一载体基板,具有第一表面与相对于该第一表面的第二表面;
第二载体基板,堆叠在该第一载体基板上并且具有第三表面以及相对于该第三表面的第四表面,其中该第四表面面向该第一表面;
半导体晶粒,安装于该第二载体基板的该第三表面上;以及
散热器,设置在该第一载体基板的该第一表面上,以覆盖并围绕该第二载体基板与该半导体晶粒。
2.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:封装材料,具有被该散热器覆盖的第一部分,其中该第一部分围绕该第二载体基板与该半导体晶粒。
3.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:封装材料,具有围绕该散热器的外侧壁的第二部分。
4.如权利要求2所述的半导体封装结构,其特征在于,该第一部分覆盖该半导体晶粒的上表面。
5.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:热界面材料层,附着于该半导体晶粒与该散热器之间。
6.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:
第一底部填充材料层,插入于该第一载体基板与该第二载体基板之间;
及/或,第二底部填充材料层,插入于该半导体晶粒与该第二载体基板之间。
7.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:
第一底部填充材料层,插入于该第一载体基板与该第二载体基板之间;以及
第二底部填充材料层,插入于该半导体晶粒与该第二载体基板之间;
其中,一间隙围绕该半导体晶粒、该第二载体基板、该第一底部填充材料层以及该第二底部填充材料层。
8.如权利要求1所述的半导体封装结构,其特征在于,进一步包括:电容,安装于该第一载体基板的该第一表面上,该二载体基板的该第三表面上,或者该第二载体基板的该第四表面上。
9.一种半导体封装结构,其特征在于,包括:
第一载体基板,具有第一表面与相对于该第一表面的第二表面;
第二载体基板,堆叠在该第一载体基板上并且具有第三表面以及相对于该第三表面的第四表面,其中该第四表面面向该第一表面;
半导体晶粒,安装于该第二载体基板的该第三表面上;
第一封装材料,设置在该第二载体基板的该第三表面上并且围绕该半导体晶粒;以及
散热器,设置在该第一载体基板的该第一表面上,以覆盖并围绕该第二载体基板与该第一封装材料。
10.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:第二封装材料,具有被该散热器覆盖的第一部分,其中该第一部分围绕该第二载体基板与该第一封装材料。
11.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:第二封装材料,具有围绕该散热器的外侧壁的第二部分。
12.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:一热界面材料层,附着于该半导体晶粒与该散热器之间。
13.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:
底部填充材料,插入在该半导体晶粒与该第二载体基板之间,并且该第一封装材料围绕该底部填充材料。
14.如权利要求9所述的半导体封装结构,其特征在于,该第一封装材料覆盖该半导体晶粒的上表面。
15.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:
底部填充材料,插入在该第一载体基板与该第二载体基板之间。
16.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:
底部填充材料,插入在该第一载体基板与该第二载体基板之间,其中一间隙围绕该第一封装材料,该第二载体基板以及该底部填充材料。
17.如权利要求9所述的半导体封装结构,其特征在于,进一步包括:电容,安装于该第一载体基板的该第一表面上,该二载体基板的该第三表面上,或者该第二载体基板的该第四表面上。
18.如权利要求9所述的半导体封装结构,其特征在于,该第一载体基板为单层封装基板且该第二载体基板为双层封装基板。
19.一种形成半导体封装结构的方法,其特征在于,包括:
提供第一载体基板以及第二载体基板,其中该第一载体基板具有第一表面与相对于该第一表面的第二表面,该第二载体基板具有第三表面以及相对于该第三表面的第四表面;
将该第二载体基板堆叠于该第一载体基板上,其中该第四表面面向该第一表面;
在该第三表面上堆叠半导体晶粒;以及
在该第一表面上形成散热器以覆盖并且围绕该第二载体基板与该半导体晶粒。
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---|---|---|---|---|
CN111799242A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法与载板组件 |
CN111799182A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10515887B2 (en) | 2016-09-20 | 2019-12-24 | Mediatek Inc. | Fan-out package structure having stacked carrier substrates and method for forming the same |
US11107747B2 (en) * | 2018-09-19 | 2021-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package with composite thermal interface material structure and method of forming the same |
US11626343B2 (en) | 2018-10-30 | 2023-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with enhanced thermal dissipation and method for making the same |
KR102643069B1 (ko) * | 2019-07-03 | 2024-03-05 | 에스케이하이닉스 주식회사 | 열 방출 구조를 포함하는 적층 반도체 패키지 |
US11450588B2 (en) * | 2019-10-16 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming chip package structure with heat conductive layer |
US11830821B2 (en) * | 2020-10-19 | 2023-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of manufacture |
US11915991B2 (en) * | 2021-03-26 | 2024-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having first heat spreader and second heat spreader and manufacturing method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040063242A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
CN101593734A (zh) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | 倒装芯片封装及半导体芯片封装 |
CN102573279A (zh) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | 半导体封装及其形成方法 |
US20120193779A1 (en) * | 2011-01-28 | 2012-08-02 | Chung-Sun Lee | Semiconductor device and method of fabricating the same |
CN104904006A (zh) * | 2012-11-09 | 2015-09-09 | 安默克技术股份公司 | 半导体器件以及其制造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6972481B2 (en) | 2002-09-17 | 2005-12-06 | Chippac, Inc. | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
JP2004140286A (ja) | 2002-10-21 | 2004-05-13 | Nec Semiconductors Kyushu Ltd | 半導体装置及びその製造方法 |
US7378733B1 (en) * | 2006-08-29 | 2008-05-27 | Xilinx, Inc. | Composite flip-chip package with encased components and method of fabricating same |
US7968979B2 (en) * | 2008-06-25 | 2011-06-28 | Stats Chippac Ltd. | Integrated circuit package system with conformal shielding and method of manufacture thereof |
US8564125B2 (en) * | 2011-09-02 | 2013-10-22 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded thermal heat shield and method of manufacture thereof |
US9263186B2 (en) | 2013-03-05 | 2016-02-16 | Qualcomm Incorporated | DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor |
US9147667B2 (en) | 2013-10-25 | 2015-09-29 | Bridge Semiconductor Corporation | Semiconductor device with face-to-face chips on interposer and method of manufacturing the same |
US10515887B2 (en) | 2016-09-20 | 2019-12-24 | Mediatek Inc. | Fan-out package structure having stacked carrier substrates and method for forming the same |
-
2017
- 2017-09-11 US US15/700,220 patent/US10515887B2/en active Active
- 2017-09-12 TW TW106131207A patent/TW201830606A/zh unknown
- 2017-09-14 CN CN201710827237.0A patent/CN107863326A/zh not_active Withdrawn
- 2017-09-14 EP EP17191014.4A patent/EP3300106B1/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040063242A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
CN101593734A (zh) * | 2008-05-27 | 2009-12-02 | 联发科技股份有限公司 | 倒装芯片封装及半导体芯片封装 |
CN102573279A (zh) * | 2010-11-17 | 2012-07-11 | 三星电子株式会社 | 半导体封装及其形成方法 |
US20120193779A1 (en) * | 2011-01-28 | 2012-08-02 | Chung-Sun Lee | Semiconductor device and method of fabricating the same |
CN104904006A (zh) * | 2012-11-09 | 2015-09-09 | 安默克技术股份公司 | 半导体器件以及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111799242A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法与载板组件 |
CN111799182A (zh) * | 2019-04-09 | 2020-10-20 | 矽品精密工业股份有限公司 | 封装堆叠结构及其制法 |
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EP3300106A1 (en) | 2018-03-28 |
US10515887B2 (en) | 2019-12-24 |
TW201830606A (zh) | 2018-08-16 |
EP3300106B1 (en) | 2022-07-20 |
US20180082936A1 (en) | 2018-03-22 |
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