WO2003050851A2 - A semiconductor device - Google Patents

A semiconductor device Download PDF

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Publication number
WO2003050851A2
WO2003050851A2 PCT/SG2001/000251 SG0100251W WO03050851A2 WO 2003050851 A2 WO2003050851 A2 WO 2003050851A2 SG 0100251 W SG0100251 W SG 0100251W WO 03050851 A2 WO03050851 A2 WO 03050851A2
Authority
WO
WIPO (PCT)
Prior art keywords
chip
electrical
semiconductor chip
contacts
electrical contacts
Prior art date
Application number
PCT/SG2001/000251
Other languages
French (fr)
Inventor
Kin Loke Ong
Fui Jin Chai
Original Assignee
Infineon Technologies A.G.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies A.G. filed Critical Infineon Technologies A.G.
Priority to AU2002217744A priority Critical patent/AU2002217744A1/en
Priority to PCT/SG2001/000251 priority patent/WO2003050851A2/en
Publication of WO2003050851A2 publication Critical patent/WO2003050851A2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors

Definitions

  • the invention relates to a semiconductor device and in particular, a semiconductor device comprising more than one semiconductor chip.
  • Such packages are commonly referred to as multi-chip modules and normally involve attaching a first chip to a substrate and attaching a second chip to the first chip, usually on top of the first chip so that the first chip is located between the first chip and the second chip.
  • one chip may be a logic chip and the other chip may be a memory chip, such as a flash memory.
  • the memory chip is electrically connected to the logic chip so that the logic and memory chips can exchange data directly.
  • the chip which is attached to the substrate is normally the logic chip. This is mechanically attached to the substrate using a suitable adhesive and wire bonds electrically connect contact pads on top of the logic chip to electrical contacts on the substrate.
  • the memory chip is then attached using a suitable adhesive to the top of the logic chip and the pads on the memory chip are electrically connected to contact pads on the logic chip also by wire bonding.
  • the top chip (the memory chip) to be smaller than the bottom chip (the logic chip) in order that the memory chip can be positioned within the contact pads on top of the logic chip and does not cover the contact pads. Therefore, this limits the size of the memory chip that can be attached to the logic chip, as it must necessarily have a smaller footprint than the logic chip.
  • a semiconductor device comprising a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, a second semiconductor chip attached to a second surface of the first chip opposite the first surface, the second chip having a third set of electrical contacts, the third set of electrical contact areas being electrically connected to the second set of electrical contacts by first electrical coupling means and the first set of electrical contacts being provided with a second electrical coupling means to permit the device to be electrically coupled to an electrical circuit.
  • a method of assembling a semiconductor device comprising providing a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, providing a second semiconductor chip having a third set of electrical contacts, attaching the second semiconductor chip to a second surface of the first chip opposite the first surface, forming first electrical couplings between the second set of contacts on the first chip and the third set of contacts on the second chip to electrically couple the first chip to the second chip, and forming second electrical coupling means on the first set of electrical contacts to permit the device to be electrically coupled to an electrical circuit.
  • the first electrical coupling means are wire bonds.
  • the second electrical coupling means are solder bumps.
  • the device may further comprise a substrate having a fourth set of electrical contacts; the fourth set of electrical contacts being coupled to the first set of electrical contacts by the second electrical coupling means.
  • the second semiconductor chip has a larger surface area than the first semiconductor chip.
  • a semiconductor device comprising a first semiconductor chip having first and second sets of electrical contact areas on a first surface of the first semiconductor chip, the first set of electrical contact areas having solder bumps attached thereto, a second semiconductor chip having a third set of electrical contact areas thereon, the second semiconductor chip being mounted to a second surface of the first semiconductor chip opposite to the first surface, the second semiconductor chip having a surface area greater than that of the first semiconductor chip and the third set of electrical contact areas on the second semiconductor chip being electrically connected to the second set of electrical contact areas on the first semiconductor chip by wire bonds.
  • the first semiconductor chip may be a logic chip and the second semiconductor chip may be a memory chip, such as a flash memory.
  • Figure 1 is a cross-sectional view of a semiconductor device package.
  • Figure 1 shows a semiconductor device 1 comprising a substrate 2, a first semiconductor chip 3 and a second semiconductor chip 4.
  • the gap between the surface 11 of the first chip 3 and surface 15 of substrate 2 is underfilled with an underfill material 8.
  • the second chip 4 is attached to surface 19 of the first chip 3 by an epoxy adhesive 9 and bond pads 16 on surface 10 of the semiconductor chip 4 are electrically connected to bond pads 17 on surface 11 of the first semiconductor chip 3 by wire bonds 12.
  • the semiconductor chips 3, 4 and the wire bonds 12 are encapsulated in an epoxy resin molding material 5.
  • the gap between the surface 11 and the surface 15 may be underfilled using the epoxy resin molding material 5 during the encapsulation process.
  • Solder balls 13 are formed on underside 14 of the substrate 2 opposite to the side 15 of the substrate 2 on which the semiconductor chip 3 is attached by the solder bumps 6.
  • the solder balls 13 are electrically connected to the electrical contacts 7 and permit the semiconductor device package 1 to be mounted on an electrical circuit, such as a circuit board.
  • the solder bumps 6 are formed on the appropriate bond pads 18 on the surface 11 of the first semiconductor chip 3.
  • the second semiconductor chip 4 is then attached to the surface 19 of the first semiconductor chip 3 by an epoxy adhesive 9.
  • Wire bonds are then formed between bond pads 16 on the surface 10 of the second semiconductor chip 4 and the appropriate bond pads 17 on the first semiconductor chip 3.
  • the solder bumps 6 are bonded to the pads 7 of the substrate by a solder reflow technique and an underfill material 8 is used to fill the gaps between the bumps 6 and between the surface 11 of the first semiconductor chip 3 and the surface 15 of the substrate.
  • the epoxy resin material 5 is then molded around the semiconductor chips 3, 4 and the wire bonds 12 to form the finished semiconductor device package 1.
  • semiconductor device package 1 is shown mounted on a substrate 2, it is possible that the substrate 2 may be omitted and the solder bumps 6 on the semiconductor chip 3 could be used to directly connect and mount the chips 3, 4 on an electrical circuit, such as a motherboard.
  • the first and second chips 3, 4 and the wire bonds 12 would still be encased in an epoxy resin molding material but the solder bumps 6 would be exposed to permit mechanical and electrical connection of the device to the electrical circuit.
  • underfiller can be used to protect the structure after the device has been attached to the electrical circuit.
  • the invention has the advantage that it enables a second chip 4 having a larger surface area than the first chip 3 to be stacked on top of the first chip 3 and electrically connected to the first chip 3.

Abstract

A semiconductor device (1) includes a first chip (3) having a first set of electrical contacts (18) and a second set of electrical contacts (17) on a first surface (11) of the chip (3). A second semiconductor chip (4) is attached to a second surface (19) of the first chip (3) opposite the first surface (11). The second chip has a third set of electrical contacts (16). The third set of electrical contacts (16) are electrically connected to the second set of electrical contacts by first electrical coupling means (12). The first set of electrical contacts (18) are provided with second electrical coupling means (6) to permit the device (1) to be electrically coupled to an electrical circuit.

Description

A Semiconductor Device
The invention relates to a semiconductor device and in particular, a semiconductor device comprising more than one semiconductor chip.
Recently, it has become possible to manufacture semiconductor device packages that include more than one semiconductor chip. Such packages are commonly referred to as multi-chip modules and normally involve attaching a first chip to a substrate and attaching a second chip to the first chip, usually on top of the first chip so that the first chip is located between the first chip and the second chip. For example, one chip may be a logic chip and the other chip may be a memory chip, such as a flash memory. Typically, in such applications the memory chip is electrically connected to the logic chip so that the logic and memory chips can exchange data directly.
The chip which is attached to the substrate is normally the logic chip. This is mechanically attached to the substrate using a suitable adhesive and wire bonds electrically connect contact pads on top of the logic chip to electrical contacts on the substrate. The memory chip is then attached using a suitable adhesive to the top of the logic chip and the pads on the memory chip are electrically connected to contact pads on the logic chip also by wire bonding.
However, conventionally it has been necessary for the top chip (the memory chip) to be smaller than the bottom chip (the logic chip) in order that the memory chip can be positioned within the contact pads on top of the logic chip and does not cover the contact pads. Therefore, this limits the size of the memory chip that can be attached to the logic chip, as it must necessarily have a smaller footprint than the logic chip.
In theory, it would be possible to solve this problem by positioning the memory chip on the substrate and the logic chip on top of the memory chip. However, this would has the significant disadvantage of requiring a redesign of the layout of the electrical contacts on the substrate, which is complex and expensive, especially if there is no change in the logic chip.
In accordance with a first aspect of the present invention, there is provided a semiconductor device comprising a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, a second semiconductor chip attached to a second surface of the first chip opposite the first surface, the second chip having a third set of electrical contacts, the third set of electrical contact areas being electrically connected to the second set of electrical contacts by first electrical coupling means and the first set of electrical contacts being provided with a second electrical coupling means to permit the device to be electrically coupled to an electrical circuit.
In accordance with a second aspect of the present invention, there is provided a method of assembling a semiconductor device comprising providing a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, providing a second semiconductor chip having a third set of electrical contacts, attaching the second semiconductor chip to a second surface of the first chip opposite the first surface, forming first electrical couplings between the second set of contacts on the first chip and the third set of contacts on the second chip to electrically couple the first chip to the second chip, and forming second electrical coupling means on the first set of electrical contacts to permit the device to be electrically coupled to an electrical circuit.
Typically, the first electrical coupling means are wire bonds.
Preferably, the second electrical coupling means are solder bumps.
Preferably, the device may further comprise a substrate having a fourth set of electrical contacts; the fourth set of electrical contacts being coupled to the first set of electrical contacts by the second electrical coupling means.
Typically, the second semiconductor chip has a larger surface area than the first semiconductor chip.
In accordance with a third aspect of the present invention, there is provided a semiconductor device comprising a first semiconductor chip having first and second sets of electrical contact areas on a first surface of the first semiconductor chip, the first set of electrical contact areas having solder bumps attached thereto, a second semiconductor chip having a third set of electrical contact areas thereon, the second semiconductor chip being mounted to a second surface of the first semiconductor chip opposite to the first surface, the second semiconductor chip having a surface area greater than that of the first semiconductor chip and the third set of electrical contact areas on the second semiconductor chip being electrically connected to the second set of electrical contact areas on the first semiconductor chip by wire bonds.
Typically, in one example of the invention, the first semiconductor chip may be a logic chip and the second semiconductor chip may be a memory chip, such as a flash memory.
A semiconductor device in accordance with the invention will now be described with reference to the accompanying drawings, in which:
Figure 1 is a cross-sectional view of a semiconductor device package.
Figure 1 shows a semiconductor device 1 comprising a substrate 2, a first semiconductor chip 3 and a second semiconductor chip 4. Solder bumps 6, on bond pads 18 on the first chip 3, mechanically and electrically couple the chip 3 to electrical contacts 7 on the substrate 2. The gap between the surface 11 of the first chip 3 and surface 15 of substrate 2 is underfilled with an underfill material 8. The second chip 4 is attached to surface 19 of the first chip 3 by an epoxy adhesive 9 and bond pads 16 on surface 10 of the semiconductor chip 4 are electrically connected to bond pads 17 on surface 11 of the first semiconductor chip 3 by wire bonds 12. The semiconductor chips 3, 4 and the wire bonds 12 are encapsulated in an epoxy resin molding material 5.
As an alternative to using the underfill material 8, the gap between the surface 11 and the surface 15 may be underfilled using the epoxy resin molding material 5 during the encapsulation process.
Solder balls 13 are formed on underside 14 of the substrate 2 opposite to the side 15 of the substrate 2 on which the semiconductor chip 3 is attached by the solder bumps 6. The solder balls 13 are electrically connected to the electrical contacts 7 and permit the semiconductor device package 1 to be mounted on an electrical circuit, such as a circuit board.
In order to assemble the semiconductor device package 1 , the solder bumps 6 are formed on the appropriate bond pads 18 on the surface 11 of the first semiconductor chip 3. The second semiconductor chip 4 is then attached to the surface 19 of the first semiconductor chip 3 by an epoxy adhesive 9. Wire bonds are then formed between bond pads 16 on the surface 10 of the second semiconductor chip 4 and the appropriate bond pads 17 on the first semiconductor chip 3. After the wire bonding has been performed, the solder bumps 6 are bonded to the pads 7 of the substrate by a solder reflow technique and an underfill material 8 is used to fill the gaps between the bumps 6 and between the surface 11 of the first semiconductor chip 3 and the surface 15 of the substrate. After this, the epoxy resin material 5 is then molded around the semiconductor chips 3, 4 and the wire bonds 12 to form the finished semiconductor device package 1.
Although in the above example, semiconductor device package 1 is shown mounted on a substrate 2, it is possible that the substrate 2 may be omitted and the solder bumps 6 on the semiconductor chip 3 could be used to directly connect and mount the chips 3, 4 on an electrical circuit, such as a motherboard. In this example the first and second chips 3, 4 and the wire bonds 12 would still be encased in an epoxy resin molding material but the solder bumps 6 would be exposed to permit mechanical and electrical connection of the device to the electrical circuit.
Alternatively there may be no encapsulation, and underfiller can be used to protect the structure after the device has been attached to the electrical circuit.
The invention has the advantage that it enables a second chip 4 having a larger surface area than the first chip 3 to be stacked on top of the first chip 3 and electrically connected to the first chip 3.

Claims

1. A semiconductor device comprising a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, a second semiconductor chip attached to a second surface of the first chip opposite the first surface, the second chip having a third set of electrical contacts, the third set of electrical contact areas being electrically connected to the second set of electrical contacts by first electrical coupling means and the first set of electrical contacts being provided with a second electrical coupling means to permit the device to be electrically coupled to an electrical circuit.
2. A device according to claim 1 , wherein the first electrical coupling means are wire bonds.
3. A device according to claim 1 or claim 2, wherein the second electrical coupling means are solder bumps.
4. A device according to any of the preceding claims, further comprising a substrate having a fourth set of electrical contacts, the fourth set of electrical contacts being coupled to the first set of electrical contacts by the second electrical coupling means.
5. A device according to any of the preceding claims, wherein the second semiconductor chip has a larger surface area than the first semiconductor chip.
6. A semiconductor device comprising a first semiconductor chip having first and second sets of electrical contact areas on a first surface of the first semiconductor chip, the first set of electrical contact areas having solder bumps attached thereto, a second semiconductor chip having a third set of electrical contact areas thereon, the second semiconductor chip being mounted to a second surface of the first semiconductor chip opposite to the first surface, the second semiconductor chip having a surface area greater than that of the first semiconductor chip and the third set of electrical contact areas on the second semiconductor chip being electrically connected to the second set of electrical contact areas on the first semiconductor chip by wire bonds.
7. A device according to any of the preceding claims, wherein the first semiconductor chip is a logic chip and the second semiconductor chip is a memory chip.
8. A method of assembling a semiconductor device comprising providing a first chip having a first set of electrical contacts and a second set of electrical contacts on a first surface of the chip, providing a second semiconductor chip having a third set of electrical contacts, attaching the second semiconductor chip to a second surface of the first chip opposite the first surface, forming first electrical couplings between the second set of contacts on the first chip and the third set of contacts on the second chip to electrically couple the first chip to the second chip, and forming second electrical coupling means on the first set of electrical contacts to permit the device to be electrically coupled to an electrical circuit.
9. A method according to claim 8, wherein the first electrical coupling means are formed by a wire bonding operation.
10. A method according to claim 8 or claim 9, wherein the second electrical coupling means are formed by a solder bump forming operation.
11. A method according to any of claims 8 to 10, further comprising providing a substrate having a fourth set of electrical contacts, and electrically coupling the fourth set of contacts to the first set of contacts using the second electrical coupling means.
PCT/SG2001/000251 2001-12-12 2001-12-12 A semiconductor device WO2003050851A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002217744A AU2002217744A1 (en) 2001-12-12 2001-12-12 A semiconductor device
PCT/SG2001/000251 WO2003050851A2 (en) 2001-12-12 2001-12-12 A semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2001/000251 WO2003050851A2 (en) 2001-12-12 2001-12-12 A semiconductor device

Publications (1)

Publication Number Publication Date
WO2003050851A2 true WO2003050851A2 (en) 2003-06-19

Family

ID=20429009

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2001/000251 WO2003050851A2 (en) 2001-12-12 2001-12-12 A semiconductor device

Country Status (2)

Country Link
AU (1) AU2002217744A1 (en)
WO (1) WO2003050851A2 (en)

Also Published As

Publication number Publication date
AU2002217744A1 (en) 2003-06-23

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