CN102573279A - 半导体封装及其形成方法 - Google Patents

半导体封装及其形成方法 Download PDF

Info

Publication number
CN102573279A
CN102573279A CN2011103651443A CN201110365144A CN102573279A CN 102573279 A CN102573279 A CN 102573279A CN 2011103651443 A CN2011103651443 A CN 2011103651443A CN 201110365144 A CN201110365144 A CN 201110365144A CN 102573279 A CN102573279 A CN 102573279A
Authority
CN
China
Prior art keywords
semiconductor chip
semiconductor
cap
packaging
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011103651443A
Other languages
English (en)
Inventor
任允赫
李忠善
赵泰济
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN102573279A publication Critical patent/CN102573279A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了半导体封装及其形成方法。该半导体封装包括封装盖，该封装盖能够辐射高温并起到防止电磁波传输到半导体封装中和/或从半导体封装传输到外面的屏蔽功能。包括封装盖的半导体封装防止了芯片故障并改善了器件可靠性。封装盖设置为覆盖半导体封装的第一和第二半导体芯片。

Description

半导体封装及其形成方法
技术领域
示范性实施例涉及一种半导体封装以及制造该半导体封装的方法。
背景技术
随着朝小型、纤薄且紧密的电子产品的趋势，需要小且纤薄的印刷电路板。与电子设备的便携能力一起，多功能以及大量数据的传输和接收功能使得复杂的印刷电路板设计成为必然。因而，对形成有电源电路、接地电路、信号电路等的多层印刷电路板的需求增加。
半导体芯片，诸如中央处理单元、电力集成电路等，可以安装在多层印刷电路板上。这样的半导体芯片会在使用时产生高温。高温会导致半导体器件由于过载而引起的故障。
当多个半导体芯片安装在印刷电路板上时，电磁干扰(EMI)会在半导体芯片之间产生。这样的EMI会导致半导体芯片的故障。
发明内容
根据本发明构思的实施例，一种半导体封装包括：封装基板，包括在封装基板的相反边缘处的封装盖互连通孔(through via)；第一半导体芯片，堆叠在封装基板上；至少一个第二半导体芯片，堆叠在第一半导体芯片上并具有比第一半导体芯片的宽度窄的宽度；模塑膜，覆盖第一半导体芯片的邻近第二半导体芯片的侧表面的上表面，并覆盖第二半导体芯片的侧表面；热界面膜，设置在第二半导体芯片上；封装盖，与热界面膜接触并覆盖第一和第二半导体芯片；以及封装粘合图案，在封装盖互连通孔与封装盖的下部之间。
在示范性实施例中，模塑膜的上表面位于与第二半导体芯片的上表面相同的高度，热界面膜从第二半导体芯片的顶上延伸到模塑膜的顶上，并在模塑膜与封装盖之间。
在另一示范性实施例中，模塑膜的上表面高于第二半导体芯片的上表面。
封装基板还包括封装接地层，封装盖互连通孔与该封装接地层接触。可替代地，封装盖互连通孔不与封装接地层接触。
封装盖互连通孔由导电膜形成。可替代地，封装盖互连通孔由绝缘膜形成。
封装粘合图案是导电的。
封装盖包括从封装盖向上突出的部分(例如，销部分)。
在示范性实施例中，封装基板还包括以多层结构堆叠的导电层和多个绝缘膜，封装盖互连通孔包括穿过绝缘膜且设置在彼此不同层处的多个子通孔。在此情形下，在垂直方向上的相邻子通孔没有彼此对齐(也就是，偏离)。
封装基板还包括电力层，封装盖互连通孔不与该电力层接触。
模塑膜由热环氧树脂形成。
热界面膜由热油脂、环氧材料或包括在环氧材料中的金属固体颗粒形成。
根据本发明构思的实施例，一种制造半导体封装的方法包括：提供包括多个第一半导体芯片的晶片；将多个第二半导体芯片安装在包括多个第一半导体芯片的晶片上，多个第二半导体芯片的每个分别与多个第一半导体芯片中的一第一半导体芯片交叠；形成覆盖第二半导体芯片的模塑膜；去除部分模塑膜以暴露第二半导体芯片的上表面；将晶片分离为具有堆叠在第一半导体芯片上的第二半导体芯片的单元部分；将单元部分的第一半导体芯片安装在封装基板上；以及用封装盖覆盖单元部分的第一和第二半导体芯片，其中热界面膜位于封装盖与单元部分的第二半导体芯片之间。
用封装盖覆盖第一和第二半导体芯片包括：用位于封装盖与封装基板之间的粘合图案来固定封装盖。
形成覆盖第二半导体芯片的侧表面并暴露第二半导体芯片的上表面的模塑膜包括：形成覆盖第二半导体芯片的侧表面和上表面的模塑膜；以及通过研磨模塑膜来暴露第二半导体芯片的上表面。
该方法还包括在分离晶片之前形成热界面材料膜。
根据本发明构思的实施例，一种半导体封装包括：封装基板，包括通孔；第一半导体芯片，堆叠在封装基板上；至少一个第二半导体芯片，堆叠在第一半导体芯片上并具有比第一半导体芯片的宽度窄的宽度；模塑膜，在第一半导体芯片的上表面的邻近第二半导体芯片的侧表面的部分上；热界面膜，设置在第二半导体芯片上；封装盖，与热界面膜接触并位于第一和第二半导体芯片上方；以及导电封装粘合图案，在通孔与封装盖的一部分之间。
附图说明
从以下参照附图的描述，本发明构思的实施例将变得明显，其中相似的附图标记可以在不同的附图中始终指代相似的部件，在附图中：
图1是根据本发明构思的实施例的半导体封装的截面图。
图2是用于描述图1的半导体封装中的热传输的示图。
图3是示出施加到图1的半导体封装的电压的示图。
图4至图13是用于描述根据本发明构思的实施例制造半导体封装的方法的截面图。
图14是根据本发明构思的实施例的半导体封装的截面图。
图15是根据本发明构思的实施例的半导体封装的截面图。
图16是根据本发明构思的实施例的半导体封装的截面图。
图17是根据本发明构思的实施例的半导体封装的截面图。
图18是根据本发明构思的实施例的半导体封装的截面图。
图19是根据本发明构思的实施例的半导体封装的截面图。
图20是根据本发明构思的实施例的半导体封装的截面图。
图21是示出图20的半导体封装中的热传输的示图。
图22是示出根据本发明构思的实施例的半导体模块的方框图。
图23是示出根据本发明构思的实施例的半导体模块的方框图。
图24是示出根据本发明构思的实施例的半导体模块的方框图。
图25是示出包括根据本发明构思的示范性实施例的半导体封装的电子设备的方框图。
具体实施方式
在下文参照附图更全面地描述本发明构思，附图中示出了本发明构思的实施例。然而，本发明构思可以以多种不同的形式实施，而不应被解释为限于这里阐述的实施例。在附图中，为清晰起见，层和区域的尺寸和相对尺寸可以被夸大。相似的附图标记可以始终指代相似的元件。
如此处所用的，术语“和/或”包括一个或多个相关所列项目的任何及所有组合。
应当理解，当称一个元件或层在另一元件或层“上”、“连接到”、“耦接到”或“邻近”另一元件或层时，它可以直接在另一元件或层上、直接连接到或耦接到另一元件或层或者直接邻近另一元件或层，或者可以存在居间的元件或层。图1是根据本发明构思的实施例的半导体封装的截面图。
参照图1，半导体封装500包括安装在封装基板200上的第一半导体芯片100和第二半导体芯片120。封装盖300形成在封装基板200上并覆盖第一和第二半导体芯片100和120。
根据实施例，封装基板200是多层印刷电路板。封装基板200包括多个绝缘膜202。第一信号图案204s、204c和204d设置在绝缘膜202当中处于最下层的绝缘膜上。根据实施例，第一信号图案204s、204c和204d包括第一封装盖互连信号图案204s、第一芯片接地电压信号图案204c和第一电源电压信号图案204d。第二信号图案212s、212c和212d设置在绝缘膜202当中处于最上层的绝缘膜上。第二信号图案212s、212c和212d包括第二封装盖互连信号图案212s、第二芯片接地电压信号图案212c和第二电源电压信号图案212d。根据实施例，封装电力层206和封装接地层210设置在处于彼此不同层的绝缘膜202中。第三信号图案208也设置在一个或多个绝缘膜202中。第一信号图案204s、204c和204d、第二信号图案212s、212c和212d、封装电力层206、第三信号图案208和封装接地层210由导电膜形成。封装基板200包括贯穿绝缘膜202的多个封装基板通孔220s、220c和220d。封装基板通孔220s、220c和220d包括封装盖互连通孔220s、芯片接地电压通孔220c和电源电压通孔220d。封装盖互连通孔220s设置为邻近封装基板200的边缘。
封装盖互连通孔220s连接第一封装盖互连信号图案204s和第二封装盖互连信号图案212s而没有被连接到封装电力层206和封装接地层210。芯片接地电压通孔220c连接第一芯片接地电压信号图案204c和第二芯片接地电压信号图案212c并与封装接地层210连接。电源电压通孔220d连接第一电源电压信号图案204d和第二电源电压信号图案212d并连接到封装电力层206。
外部焊球230s、230c和230d分别附接在第一信号图案204s、204c和204d的下部处。外部焊球230s、230c和230d包括封装盖互连外部焊球230s、芯片接地电压外部焊球230c和电源电压外部焊球230d。
第二半导体芯片120的宽度小于第一半导体芯片100的宽度。例如，根据实施例，第一半导体芯片100是逻辑芯片，第二半导体芯片120是存储器芯片。第一半导体芯片100包括半导体基板1、贯穿半导体基板1的芯片通孔5以及与芯片通孔5电连接的芯片球焊盘13。根据实施例，第一半导体芯片100以倒装芯片接合方式安装在封装基板200上。第二半导体芯片120以倒装芯片接合方式安装在第一半导体芯片100上。第一半导体芯片100的芯片球焊盘13通过第一内部焊球19与第二信号图案212c和212d电连接。第一和第二半导体芯片100和120通过第二内部焊球124电连接到彼此。障碍物140设置为邻近封装基板200的边缘。第二内部焊球124之间和周围的空间用第一底填充树脂膜126填充。第一内部焊球19之间和周围的空间用第二底填充树脂膜142填充。
模塑膜131定位为覆盖第一半导体芯片100的上表面的一部分以及第二半导体芯片120的侧表面。根据实施例，第二半导体芯片120的上表面可以与模塑膜131的上表面在高度上相平。模塑膜131由例如环氧树脂系列形成。
在示范性实施例中，热界面膜132插置在封装盖300与第二半导体芯片120之间以及封装盖300与模塑膜131之间。热界面膜132包括例如热油脂、环氧材料或与热油脂和环氧材料混合的金属固体颗粒诸如铟。热界面膜132在低温保持为固态，而在高温转变为液态。根据实施例，热界面膜132具有粘合功能和/或是导电的。
根据实施例，封装盖300由金属材料形成。封装粘合图案310位于封装盖300的下部与封装基板200的边缘之间。封装粘合图案310用于将封装盖300粘合并固定到封装基板200。在示范性实施例中，封装粘合图案310是导电的。根据实施例，封装粘合图案310邻近第二封装盖互连信号图案212s。此外，根据实施例，封装粘合图案310与封装盖互连通孔220s交叠。根据实施例，由于封装盖300固定到封装基板200并且位于封装基板200上的封装粘合图案310热连接且电连接到封装基板200，所以不需要在封装基板、模块基板或母基板处形成用于屏蔽罐(shield can)或热沉板的孔。因而，不需要由于形成孔而改变封装基板、模块基板或母基板的设计。
图2是用于描述图1的半导体封装中的热传输的示图。
参照图2，由第一和第二半导体芯片100和120产生的热根据箭头方向400流动。由第二半导体芯片120产生的热通过热界面材料膜132传输到具有高热导率的封装盖300，封装盖300中的热在被传输到第二封装盖互连信号图案212s、封装盖互连通孔220s和第一封装盖互连信号图案204s之前在封装盖300的区域上扩散。由第一半导体芯片100(半导体芯片100和120中最下面的一个)产生的热通过第二半导体芯片120扩散，并通过第二半导体芯片120、模塑膜131和热界面膜132传输到封装盖300。封装盖300用作散热器或热沉，其将来自第一和第二半导体芯片100和120的热排出。因而，由于封装盖300排出所产生的热，所以可以防止半导体芯片100和120由于高温引起的故障。因而，改善了半导体封装500的可靠性。
根据实施例，模塑膜131由环氧系列材料形成，其具有约0.30W/(m·K)至约7W/(m·K)的热导率。例如，在模塑膜131由热环氧树脂形成时，其热导率为约1W/(m·K)至7W/(m·K)，高于空气的热导率0.025W/(m·K)。因而，如果模塑膜131位于热界面材料膜132与第一半导体芯片100之间，与当空气而不是模塑膜131位于热界面材料膜132与第一半导体芯片100之间的情形相比，可以更有效地排出热。也就是，通过将模塑膜131置于热界面材料膜132与第一半导体芯片100之间，可以增大由第一半导体芯片100产生的热的排出。在模塑膜131由例如热环氧树脂形成的情形下，可以改善热扩散或热沉效果。
图3是示出施加到图1的半导体封装的电压的示图。
参照图3，盖接地电压VSS_S施加到封装盖互连外部焊球230s。盖接地电压VSS_S从外部源通过封装盖互连外部焊球230s、第一封装盖互连信号图案204s、封装盖互连通孔220s、第二封装盖互连信号图案212s和封装粘合图案310施加到封装盖300。盖接地电压VSS_S是接地电压。芯片接地电压VSS_C施加到芯片接地电压外部焊球230c。芯片接地电压VSS_C从外部源通过芯片接地电压外部焊球230c、第一芯片接地电压信号图案204c、芯片接地电压通孔220c和第二芯片接地电压信号图案212c施加到第一半导体芯片100。电源电压VDD施加到电源电压外部焊球230d。电源电压VDD从外部源通过电源电压外部焊球230d、第一电源电压信号图案204d、电源电压通孔220d和第二电源电压信号图案212d施加到第一半导体芯片100。由于封装盖300通过不同于半导体芯片100和120的路径接地，所以静电放电(ESD)噪声被更有效地减少。
如图3所示，第一和第二半导体芯片100和120被施加有相同的芯片接地电压VSS_C和电源电压VDD。在一些实施例中，第一和第二半导体芯片100和120形成为接收不同的芯片接地电压VSS_C和电源电压VDD。例如，通过第一路径供应到第一半导体芯片100的芯片接地电压VSS_C和电源电压VDD不同于通过第二路径(不同于第一路径)供应到第二半导体芯片120的芯片接地电压VSS_C和电源电压VDD。
在一些实施例中，封装盖互连通孔220s由绝缘膜形成。根据本实施例，封装盖300执行散热功能。
图4至图13是用于描述根据本发明的实施例制造半导体封装的方法的截面图。
参照图4，描述制作第一半导体芯片100的工艺。多个芯片通孔5形成在半导体基板(或晶片)1中，该半导体基板1包括第一表面1a和第二表面1b以及多个芯片区域A和B。第一表面1a与第二表面1b相反地设置。阻挡膜3形成在芯片通孔5与半导体基板1之间。多个导电图案7和11形成在半导体基板1的第一表面1a上并与层间绝缘膜9和芯片通孔5电连接。第一芯片球焊盘13和包括部分暴露第一芯片球焊盘13的第一芯片钝化膜15形成在层间绝缘膜9上。第一内部焊球19附接到芯片球焊盘13。
参照图5，承载基板21附接在半导体基板1的第一表面1a上，而使粘合膜23插设在第一表面1a与承载基板21之间。
参照图6，芯片通孔5的下表面通过抛光邻近第二表面1b的半导体基板1以从第二表面1b去除部分半导体基板而暴露。
参照图7，半导体基板1被翻转过来使得第二基板1b朝上放置。通过执行再布线工艺，第二芯片球焊盘25和第二芯片钝化膜27形成在半导体基板1的第二表面1b上。所得结构包括第一半导体芯片100，在将半导体芯片100分离成单元芯片之前，第一半导体芯片100彼此电连接。
参照图8，第二半导体芯片120分别安装在单元芯片区域A和B上。根据实施例，第二半导体芯片120以倒装芯片接合方式安装在第一半导体芯片100上，其中第二内部焊球124位于第一和第二半导体芯片100和120之间。第一底填充树脂膜126形成为填充第二内部焊球124之间和周围的空间。
参照图9，模塑膜130通过模塑工艺形成在第一半导体芯片100上。模塑膜130覆盖第二半导体芯片120的上表面。
参照图10，模塑膜130被研磨以暴露第二半导体芯片120的上表面。
在示范性实施例中，模塑膜130覆盖第二半导体芯片120的侧表面，第二半导体芯片120的上表面被暴露。
参照图11，热界面膜132形成为覆盖第二半导体芯片120的上表面和模塑膜130的上表面。根据实施例，热界面膜132使用粘贴、喷墨印刷或旋涂工艺形成。第一内部焊球19通过去除承载基板21和粘合膜23而暴露。
参照图12，进行切割工艺以将晶片1切割成单元芯片，晶片1包括具有嵌入在其中的第二半导体芯片120的第一半导体芯片100。
参照图13，制备封装基板200。封装基板200由多层印刷电路板形成并包括堆叠为多层的多个绝缘膜202、第一信号图案204s、204c和204d、第二信号图案212s、212c和212d、封装电力层206、封装接地层210、第三信号图案208以及封装基板通孔220s、220c和220d。障碍物140形成在封装基板200上。第一半导体芯片100安装在封装基板200上使得第二信号图案212c和212d与第一内部焊球19接触。第二底填充树脂膜142形成为填充第一内部焊球19之间和周围的空间。障碍物140防止用于第二底填充树脂膜142的液体底填充树脂扩散到禁止区域中。外部焊球230s、230c和230d附接到封装基板200的下部。
返回到图1，封装粘合图案310形成在封装基板200的被暴露的封装盖互连信号图案212s上。封装粘合图案310可以通过粘贴或喷墨导电的粘合剂而形成。封装盖300覆盖第一和第二半导体芯片100和120，并接触封装粘合图案310。封装盖300接触热界面膜132。热界面膜132能够在图11描述的工艺期间之前或刚好在施加封装盖300之前而形成。可替代地，外部焊球230s、230c和230d能够在施加封装盖300之后被附接。从而，制造图1所示的半导体封装500。
在示范性实施例中，封装盖300防止封装基板200翘曲或扭曲。半导体封装500具有辐射和电磁波屏蔽功能。这表示在半导体模块级别或母基板级别不需要用于电磁波屏蔽和辐射的工艺。因而，可以简化后续的组装工艺。
图14是根据本发明构思实施例的半导体封装的截面图。
参照图14，根据本发明构思的实施例的半导体封装501包括与封装接地层210接触的封装盖互连通孔220s。此外，芯片接地电压通孔220c与封装接地层210接触。这表示，封装盖300以及第一和第二半导体芯片100和120通过相同的路径被供应接地电压VSS。也就是，封装盖300以及第一和第二半导体芯片100和120经由相同的路径接地。因而，可以有效地减小EMI。图14中的半导体封装501具有与参照图1至图13描述的实施例类似的制造工艺和构造，除了上述差异之外。
图15是根据本发明构思的实施例的半导体封装的截面图。
参照图15，根据本发明构思的实施例的半导体封装502包括由多个子通孔240形成的封装盖互连通孔220s。子通孔240在垂直方向上彼此不交叠。根据实施例，子通孔240以上下Z字形的构造来设置。图15的半导体封装502具有与结合图1至图13描述的实施例类似的制造工艺和构造，除了上述差异之外。
图16是根据本发明构思的实施例的半导体封装的截面图。
参照图16，根据本发明构思的实施例的半导体封装503包括模塑膜131，模塑膜131的上表面比第二半导体芯片120的上表面高。模塑膜131的上表面置于与热界面膜132的上表面相同的高度。模塑膜131的上表面接触封装盖300。热界面膜132在半导体封装制造工艺期间的高温下转变为液态。在此情形下，由于模塑膜131的上表面在高度上高于第二半导体芯片120的上表面，所以模塑膜131容纳液态热界面膜132。图16中的半导体封装503具有与结合图1至图13描述的实施例类似的制造工艺和构造，除了上述差异之外。
图17是根据本发明构思的实施例的半导体封装的截面图。
参照图17，根据本发明构思的实施例的半导体封装504包括第一和第二半导体芯片101和121。第一半导体芯片101的宽度比第二半导体芯片121的宽度窄。半导体封装504不包括模塑膜。图17中的半导体封装504具有与结合图1至图13描述的实施例类似的制造工艺和构造，除了上述差异之外。
图18是根据本发明构思的实施例的半导体封装的截面图。
参照图18，根据本发明构思的实施例的半导体封装505包括安装在封装基板200上的一个半导体芯片122，但不包括半导体芯片100。半导体封装505也不包括模塑膜。图18的半导体封装505具有与结合图1至图13描述的实施例相似的制造工艺和构造，除了上述差异之外。
图19是根据本发明构思的实施例的半导体封装的截面图。
参照图19，根据本发明构思的实施例的半导体封装506包括在远离半导体封装506的方向上从封装盖301突出的多个销(pin)302。该结构能够增加热辐射功能。图19的半导体封装506具有与结合图1至图13描述的实施例类似的制造工艺和构造，除了上述差异之外。
图20是根据本发明构思的实施例的半导体封装的截面图。
参照图20，根据本发明构思的实施例的半导体封装600包括安装在模块基板530上的图1的半导体封装500以及覆盖半导体封装500的模块盖510。模块盖510通过模块粘合图案520粘合到模块基板530从而被固定。模块热界面膜512插设在模块盖510与半导体封装500的封装盖300的上表面之间。
根据实施例，模块基板530是多层印刷电路板，该多层印刷电路板包括嵌入在其中的第一模块接地层540、第二模块接地层542和模块电力层544。第一模块接地层540与封装盖300电连接并被供应有盖接地电压VSS_S。在示范性实施例中，模块盖510与第一模块接地层540电连接并被供应有盖接地电压VSS_S。第二模块接地层542与第一和第二半导体芯片100和120电连接并被供应有芯片接地电压VSS_C。模块电力层544与第一和第二半导体芯片100和120电连接并被供应有电源电压VDD。
在示范性实施例中，模块盖510和封装盖300共用到第一模块接地层540的公共电连接。可替代地，模块盖510和封装盖300单独地与不同的层电连接。根据实施例，接地电压通过不同的路径施加到模块盖510和封装盖300。
图21是示出图20的半导体封装中的热传输的示图。
参照图21，由第一和第二半导体芯片100和120产生的热主要沿箭头方向401传输。由第二半导体芯片120产生的热通过形成在第二半导体芯片120上的封装热界面膜132、封装盖300、模块热界面膜512和模块盖510排出到模块基板530。模块盖510使得热辐射效果和电磁屏蔽效果增加。
根据本发明构思的示范性实施例的半导体封装可以应用到半导体模块。这参照图22至图24更全面地描述。
图22是示出包括根据本发明构思的示范性实施例的半导体封装的半导体模块的实施例的方框图。
参照图22，根据本发明构思的实施例的半导体模块601包括安装在模块基板530上的半导体封装500和电力管理单元550。半导体封装500包括封装盖互连焊球230s、芯片接地电压焊球230c和电源电压焊球230d。在示范性实施例中，封装盖互连焊球230s被接地而不经过电力管理单元550。电源电压VDD通过电力管理单元550的第一端子562供应到电源电压焊球230d。芯片接地电压VSS_C通过电力管理单元550的第二端子564供应到芯片接地电压焊球230c。
半导体封装500可以与图1示出的半导体封装相同。半导体模块601可以应用到有线电子设备，诸如电视机。
图23是示出包括根据本发明构思的示范性实施例的半导体封装的半导体模块的实施例的方框图。
参照图23，根据本发明构思的实施例的半导体模块602包括安装在模块基板530上的半导体封装500和电力管理单元550。半导体封装500包括封装盖互连焊球230s、芯片接地电压焊球230c和电源电压焊球230d。电力管理单元550包括第一端子562、第二端子564和第三端子566。在示范性实施例中，电源电压VDD通过电力管理单元550的第一端子562供应到电源电压焊球230d。芯片接地电压VSS_C通过电力管理单元550的第二端子564供应到芯片接地电压焊球230c。盖接地电压VSS_S通过电力管理单元550的第三端子566施加到封装盖互连焊球230s。
半导体封装500可以与图1所示的半导体封装相同。半导体模块602可以应用到有线电子设备，诸如电视机。
图24是示出包括根据本发明构思的示范性实施例的半导体封装的半导体模块的实施例的方框图。
参照图24，根据本发明构思的实施例的半导体模块603包括安装在模块基板530上的半导体封装501和电力管理单元550。半导体封装501包括封装盖互连焊球230s、芯片接地电压焊球230c和电源电压焊球230d。电力管理单元550包括第一端子562和第二端子564。在示范性实施例中，电源电压VDD通过电力管理单元550的第一端子562施加到电源电压焊球230d。接地电压VSS通过电力管理单元550的第二端子564供应到封装盖互连焊球230s和芯片接地电压焊球230c。
半导体封装501可以与图14所示的半导体封装相同。半导体模块603可以应用到无线电子设备，诸如蜂窝电话。
上述封装技术可以应用到电子设备(或电子系统)。
图25是示出包括根据本发明构思的示范性实施例的半导体封装的电子设备的方框图。
参照图25，电子设备1300包括控制器1310、输入/输出单元1320和存储器件1330，它们经由作为数据通路的总线1350互连。控制器1310可以包括以下中的任何一个：至少一个微处理器、数字信号处理器、微控制器以及能够执行与该至少一个微处理器、数字信号处理器、微控制器相同功能的逻辑元件。控制器1310和存储器件1330包括根据本发明构思的示范性实施例的半导体封装。输入/输出单元1320可以包括键区、键盘、显示器件等中的至少一个。存储器件1330是用于存储数据的器件。存储器件1330存储由控制器1310执行的数据和/或命令。存储器件1330可以包括易失性存储器件和/或非易失性存储器件。可替代地，存储器件1330可以包括快闪存储器。例如，诸如移动设备或桌上型计算机的信息处理系统包括应用本发明构思实施例的快闪存储器。快闪存储器可以由固态盘器件形成。在此情形下，电子设备1300可以将大量数据稳定地存储在闪速存储器中。
根据实施例，电子设备1300还包括接口1340，该接口1340配置为传输数据到通讯网络和/或从通讯网络接收数据。接口1340可以形成为以有线和无线的方式操作。例如，接口1340包括天线和/或有线/无线收发器。尽管没有在图25中示出，但是电子设备1300还可以包括应用芯片组、照相机图像处理器(CIS)等。
电子设备1300可以通过执行各种功能的移动系统、个人计算机、工业个人计算机或逻辑系统实现。例如，移动系统可以是个人数字助理、便携式计算机、上网本、移动电话、无线电话、膝上型计算机、存储卡、数字音乐系统和/或信息发送/接收系统。如果电子设备1300执行无线通讯，它可以使用通讯接口协议，该通讯接口协议应用到3G通讯系统诸如CDMA、GSM、NADC、E-TDMA、WCDMA和CDMA200或其它通讯系统。
根据本发明构思的示范性实施例的半导体封装包括能够辐射高温并起到用于防止电磁波的传输的屏蔽功能的封装盖。这能够防止芯片故障并改善器件的可靠性。封装盖还防止封装基板翘曲或扭曲。由于半导体封装的辐射和电磁波屏蔽功能，在半导体模块级别或母基板级别不需要用于电磁波屏蔽和辐射的工艺。因而，可以简化后续的组装工艺。
根据示范性实施例的半导体封装包括通过设置在封装基板上的粘合图案固定且连接到封装基板的封装盖。因而，在封装基板、模块基板或母基板处不需要形成用于屏蔽罐或热沉板的孔。因而，不需要改变封装、模块或母基板的设计以允许热辐射和电磁波的屏蔽。
在根据本发明构思另一实施例的半导体封装中，堆叠在第一半导体芯片上的第二半导体芯片的宽度比第一半导体芯片的宽度窄，第一和第二半导体芯片被封装盖覆盖。模塑膜插置在第一半导体芯片与封装盖之间。与模塑膜没有插置在第一半导体芯片与封装盖之间(例如，仅空气在第一半导体芯片与封装盖之间)的情形相比，模塑膜具有比空气高的热导率，使得可以更有效地辐射在堆叠的半导体芯片结构中最下面的半导体芯片所产生的热。
通过根据本发明构思的另一实施例的半导体封装，热界面膜设置在第二半导体芯片与封装盖之间，模塑膜的上表面高于第二半导体芯片的上表面。热界面膜在封装制造工艺期间的高温下转变为液态。由于模塑膜的上表面高于第二半导体芯片的上表面，所以模塑膜容纳处于液态的热界面膜。
通过根据本发明构思的另一实施例的半导体封装，包括嵌入的半导体芯片的封装基板可以包括封装盖互连通孔和嵌入的接地层。封装盖互连通孔不与接地层连接。也就是，封装盖可以通过与半导体芯片不同的路径来接地。在此情形下，可以更有效地减少ESD噪声。
在一些实施例中，封装盖互连通孔与接地层连接。也就是，封装盖经由与半导体芯片相同的路径接地。在此情形下，可以更有效地减少EMI。
尽管已经结合在附图中示出的本发明构思的实施例描述了本发明构思，但是本发明构思不限于此。对于本领域技术人员将明显的是，可以对其进行各种替换、修改和改变而不背离本发明构思的范围和精神。
本申请要求于2010年11月17日提交的韩国专利申请No.10-2010-0114550的优先权，其全部内容通过引用结合于此。

Claims (21)

1.一种半导体封装，包括：
封装基板，包括邻近所述封装基板的边缘的通孔；
第一半导体芯片，堆叠在所述封装基板上；
至少一个第二半导体芯片，堆叠在所述第一半导体芯片上并具有比所述第一半导体芯片的宽度窄的宽度；
模塑膜，覆盖所述第一半导体芯片的上表面的邻近所述第二半导体芯片的侧表面的一部分，并覆盖所述第二半导体芯片的所述侧表面；
热界面膜，设置在所述第二半导体芯片上；
封装盖，与所述热界面膜接触并覆盖所述第一半导体芯片和所述第二半导体芯片；以及
封装粘合图案，在所述通孔与所述封装盖的一部分之间。
2.如权利要求1所述的半导体封装，其中所述模塑膜的上表面位于与所述第二半导体芯片的上表面相同的高度，所述热界面膜位于所述模塑膜与所述封装盖之间。
3.如权利要求1所述的半导体封装，其中所述模塑膜的上表面高于所述第二半导体芯片的上表面。
4.如权利要求1所述的半导体封装，其中所述封装基板还包括接地层，所述通孔与所述接地层接触。
5.如权利要求1所述的半导体封装，其中所述封装基板还包括接地层，所述通孔不与所述接地层接触。
6.如权利要求1所述的半导体封装，其中所述通孔包括导电膜。
7.如权利要求1所述的半导体封装，其中所述通孔包括绝缘膜。
8.如权利要求1所述的半导体封装，其中所述封装粘合图案是导电的。
9.如权利要求1所述的半导体封装，其中所述封装盖包括从所述封装盖突出的部分。
10.如权利要求1所述的半导体封装，其中所述封装基板还包括以多层结构堆叠的导电层和多个绝缘膜，所述通孔包括在所述绝缘膜中且设置在彼此不同层处的多个子通孔，并且其中在垂直方向上的相邻子通孔彼此偏离。
11.如权利要求1所述的半导体封装，其中所述封装基板还包括电力层，所述通孔不与所述电力层连接。
12.如权利要求1所述的半导体封装，其中所述模塑膜包括热环氧树脂。
13.如权利要求1所述的半导体封装，其中所述热界面膜包括热油脂、环氧材料或包括在环氧材料中的金属固体颗粒。
14.一种半导体模块，包括：
模块基板；和
半导体封装，安装在所述模块基板上，
其中所述半导体封装包括：
封装基板，包括邻近所述封装基板的边缘的通孔；
第一半导体芯片，堆叠在所述封装基板上；
至少一个第二半导体芯片，堆叠在所述第一半导体芯片上并具有比所述第一半导体芯片的宽度窄的宽度；
模塑膜，覆盖所述第一半导体芯片的上表面的邻近所述第二半导体芯片的侧表面的一部分，并覆盖所述第二半导体芯片的所述侧表面；
热界面膜，设置在所述第二半导体芯片上；
封装盖，与所述热界面膜接触并覆盖所述第一半导体芯片和所述第二半导体芯片；以及
封装粘合图案，在所述通孔与所述封装盖的一部分之间。
15.如权利要求14所述的半导体模块，还包括：
模块盖，覆盖所述半导体封装并位于所述模块基板上；和
模块粘合图案，在所述模块盖与所述模块基板之间。
16.如权利要求14所述的半导体模块，还包括：
电力管理单元，安装在所述模块基板上并供应盖接地电压到所述封装盖以及供应芯片接地电压到所述第一半导体芯片和所述第二半导体芯片中的一个。
17.如权利要求14所述的半导体模块，还包括：
电力管理单元，安装在所述模块基板上并供应芯片接地电压到所述第一半导体芯片和所述第二半导体芯片中的一个，所述封装盖具有不经过所述电力管理单元而接地的连接。
18.一种电子设备，包括：
半导体模块，包括模块基板和安装在所述模块基板上的半导体封装；和
输入/输出单元，从所述半导体模块接收信号以及传输信号到所述半导体模块，
其中所述半导体封装包括：
封装基板，包括邻近所述封装基板的边缘的通孔；
第一半导体芯片，堆叠在所述封装基板上；
至少一个第二半导体芯片，堆叠在所述第一半导体芯片上并具有比所述第一半导体芯片的宽度窄的宽度；
模塑膜，覆盖所述第一半导体芯片的上表面的邻近所述第二半导体芯片的侧表面的一部分，并覆盖所述第二半导体芯片的所述侧表面；
热界面膜，设置在所述第二半导体芯片上；
封装盖，与所述热界面膜接触并覆盖所述第一半导体芯片和所述第二半导体芯片；以及
封装粘合图案，在所述通孔与所述封装盖的一部分之间。
19.一种制造半导体封装的方法，包括：
提供包括多个第一半导体芯片的晶片；
将多个第二半导体芯片安装在所述晶片上，所述多个第二半导体芯片的每个分别与所述多个第一半导体芯片中的一第一半导体芯片交叠；
形成覆盖所述第二半导体芯片的模塑膜；
去除部分所述模塑膜以暴露所述第二半导体芯片的上表面；
将所述晶片分离为具有堆叠在第一半导体芯片上的第二半导体芯片的单元部分；
将单元部分的第一半导体芯片安装在封装基板上；以及
用封装盖覆盖所述单元部分的第一半导体芯片和第二半导体芯片，其中热界面膜位于封装盖与单元部分的第二半导体芯片之间。
20.如权利要求19所述的方法，还包括用位于所述封装盖与所述封装基板之间的粘合图案来固定所述封装盖。
21.一种半导体封装，包括：
封装基板，包括通孔；
第一半导体芯片，堆叠在所述封装基板上；
至少一个第二半导体芯片，堆叠在所述第一半导体芯片上并具有比所述第一半导体芯片的宽度窄的宽度；
模塑膜，在所述第一半导体芯片的上表面的邻近所述第二半导体芯片的侧表面的部分上；
热界面膜，设置在所述第二半导体芯片上；
封装盖，与所述热界面膜接触并位于所述第一半导体芯片和所述第二半导体芯片上方；以及
导电封装粘合图案，在所述通孔与所述封装盖的一部分之间。
CN2011103651443A 2010-11-17 2011-11-17 半导体封装及其形成方法 Pending CN102573279A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100114550A KR20120053332A (ko) 2010-11-17 2010-11-17 반도체 패키지 및 이의 제조 방법
KR10-2010-0114550 2010-11-17

Publications (1)

Publication Number Publication Date
CN102573279A true CN102573279A (zh) 2012-07-11

Family

ID=46021499

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011103651443A Pending CN102573279A (zh) 2010-11-17 2011-11-17 半导体封装及其形成方法

Country Status (6)

Country Link
US (1) US20120119346A1 (zh)
JP (1) JP2012109572A (zh)
KR (1) KR20120053332A (zh)
CN (1) CN102573279A (zh)
DE (1) DE102011086473A1 (zh)
TW (1) TW201234542A (zh)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000539A (zh) * 2012-11-16 2013-03-27 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103560117A (zh) * 2013-10-31 2014-02-05 中国科学院微电子研究所 一种用于PoP封装的散热结构
CN103560090A (zh) * 2013-10-31 2014-02-05 中国科学院微电子研究所 一种用于PoP封装的散热结构的制作方法
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
CN103915408A (zh) * 2013-01-03 2014-07-09 矽品精密工业股份有限公司 半导体封装件及其制法
CN103943610A (zh) * 2014-04-16 2014-07-23 华为技术有限公司 一种电子元件封装结构及电子设备
CN104377192A (zh) * 2013-08-13 2015-02-25 台湾积体电路制造股份有限公司 多芯片结构及其形成方法
CN104409447A (zh) * 2014-12-03 2015-03-11 三星半导体(中国)研究开发有限公司 包含嵌入式电容器的半导体封装件及其制备方法
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
CN105702664A (zh) * 2012-11-16 2016-06-22 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN106409774A (zh) * 2015-07-31 2017-02-15 富葵精密组件(深圳)有限公司 屏蔽罩、封装结构及封装结构制作方法
CN107230665A (zh) * 2016-03-24 2017-10-03 颀邦科技股份有限公司 微间距封装结构
CN107863326A (zh) * 2016-09-20 2018-03-30 联发科技股份有限公司 半导体封装结构及其形成方法
CN107887363A (zh) * 2016-09-29 2018-04-06 矽品精密工业股份有限公司 电子封装件及其制法
US10116555B2 (en) 2014-06-30 2018-10-30 Huawei Technologies Co., Ltd. Switch mode switching method, device, and system
CN109712946A (zh) * 2013-03-29 2019-05-03 日月光半导体制造股份有限公司 半导体封装件
CN110085523A (zh) * 2012-11-09 2019-08-02 安默克技术股份公司 半导体器件以及其制造方法
WO2019232749A1 (zh) * 2018-06-07 2019-12-12 华为技术有限公司 一种集成电路
CN111785715A (zh) * 2020-07-20 2020-10-16 潍坊歌尔微电子有限公司 一种芯片组件、芯片封装结构及电子设备
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
WO2021253912A1 (zh) * 2020-06-18 2021-12-23 华为技术有限公司 芯片封装器件及电子设备

Families Citing this family (136)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI452665B (zh) * 2010-11-26 2014-09-11 矽品精密工業股份有限公司 具防靜電破壞及防電磁波干擾之封裝件及其製法
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9679869B2 (en) 2011-09-02 2017-06-13 Skyworks Solutions, Inc. Transmission line for high performance radio frequency applications
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
US8948712B2 (en) 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
TW201351599A (zh) * 2012-06-04 2013-12-16 矽品精密工業股份有限公司 半導體封裝件及其製法
CN104410373B (zh) 2012-06-14 2016-03-09 西凯渥资讯处理科技公司 包含相关系统、装置及方法的功率放大器模块
US9295157B2 (en) 2012-07-13 2016-03-22 Skyworks Solutions, Inc. Racetrack design in radio frequency shielding applications
JP5928222B2 (ja) * 2012-07-30 2016-06-01 株式会社ソシオネクスト 半導体装置および半導体装置の製造方法
TWI487921B (zh) * 2012-11-05 2015-06-11 矽品精密工業股份有限公司 半導體封裝件之測試方法
US10714378B2 (en) 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
US9136159B2 (en) * 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR102107038B1 (ko) * 2012-12-11 2020-05-07 삼성전기주식회사 칩 내장형 인쇄회로기판과 그를 이용한 반도체 패키지 및 칩 내장형 인쇄회로기판의 제조방법
TWI508238B (zh) 2012-12-17 2015-11-11 Princo Corp 晶片散熱系統
KR102038488B1 (ko) 2013-02-26 2019-10-30 삼성전자 주식회사 반도체 패키지의 제조 방법
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9287194B2 (en) * 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
CA2809725A1 (en) * 2013-03-11 2014-09-11 Sureshchandra B. Patel Multiprocessor computing apparatus with wireless interconnect for communication among its components
TWI528517B (zh) 2013-03-26 2016-04-01 威盛電子股份有限公司 線路基板、半導體封裝結構及線路基板製程
KR101450761B1 (ko) 2013-04-29 2014-10-16 에스티에스반도체통신 주식회사 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법
KR20140130920A (ko) * 2013-05-02 2014-11-12 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
KR102041265B1 (ko) 2013-05-02 2019-11-27 삼성전자주식회사 Ｅｍｉ 차폐기능과 방열 기능을 가지는 반도체 패키지
WO2014184846A1 (ja) * 2013-05-13 2014-11-20 新電元工業株式会社 電子モジュールおよびその製造方法
KR102103375B1 (ko) * 2013-06-18 2020-04-22 삼성전자주식회사 반도체 패키지
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
US20140374901A1 (en) * 2013-06-21 2014-12-25 Samsung Electronics Co., Ltd Semiconductor package and method of fabricating the same
KR102116962B1 (ko) * 2013-06-25 2020-05-29 삼성전자주식회사 반도체 패키지
KR101504010B1 (ko) * 2013-06-26 2015-03-18 (주)인터플렉스 직접회로소자 패키지 제조방법
KR101504011B1 (ko) * 2013-06-26 2015-03-18 (주)인터플렉스 복합 직접회로소자 패키지 제조방법
CN104254223A (zh) * 2013-06-28 2014-12-31 深圳富泰宏精密工业有限公司 开关结构及具有该开关结构的电子装置
US9607951B2 (en) 2013-08-05 2017-03-28 Mediatek Singapore Pte. Ltd. Chip package
US9209046B2 (en) * 2013-10-02 2015-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
TWI511245B (zh) * 2013-10-04 2015-12-01 Azurewave Technologies Inc 用於提升散熱效能的模組積體電路封裝結構及其製作方法
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9287240B2 (en) * 2013-12-13 2016-03-15 Micron Technology, Inc. Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
US9793242B2 (en) * 2013-12-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with die stack including exposed molding underfill
US9209048B2 (en) * 2013-12-30 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Two step molding grinding for packaging applications
US9406650B2 (en) * 2014-01-31 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
JP6347618B2 (ja) * 2014-02-07 2018-06-27 日本特殊陶業株式会社 ガス検出器
US10020236B2 (en) * 2014-03-14 2018-07-10 Taiwan Semiconductar Manufacturing Campany Dam for three-dimensional integrated circuit
US9269700B2 (en) 2014-03-31 2016-02-23 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
JP6438225B2 (ja) * 2014-07-24 2018-12-12 株式会社ジェイデバイス 半導体パッケージ
US10729001B2 (en) 2014-08-31 2020-07-28 Skyworks Solutions, Inc. Devices and methods related to metallization of ceramic substrates for shielding applications
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
JP5933047B2 (ja) * 2015-01-13 2016-06-08 株式会社東芝 半導体装置の製造方法、半導体装置の検査方法、および半導体装置
US20180157246A1 (en) * 2015-01-30 2018-06-07 Arima Communications Corp. Automated production system for mobile phone
TWM505131U (zh) * 2015-01-30 2015-07-11 Arima Communication Corp 手機自動化生產系統
TWI555147B (zh) * 2015-03-20 2016-10-21 矽品精密工業股份有限公司 散熱型封裝結構及其散熱件
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9960145B2 (en) * 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
KR101646501B1 (ko) * 2015-03-30 2016-08-08 앰코 테크놀로지 코리아 주식회사 리드를 갖는 반도체 패키지
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
KR101734382B1 (ko) * 2015-09-24 2017-05-12 주식회사 에스에프에이반도체 히트 스프레더가 부착된 웨이퍼 레벨의 팬 아웃 패키지 및 그 제조 방법
US9905436B2 (en) * 2015-09-24 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Wafer level fan-out package and method for manufacturing the same
WO2017098689A1 (ja) 2015-12-09 2017-06-15 パナソニック株式会社 半導体発光装置
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10204883B2 (en) * 2016-02-02 2019-02-12 Taiwan Semidonductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US11329026B2 (en) * 2016-02-17 2022-05-10 Micron Technology, Inc. Apparatuses and methods for internal heat spreading for packaged semiconductor die
US10229887B2 (en) * 2016-03-31 2019-03-12 Intel Corporation Systems and methods for electromagnetic interference shielding
KR101837511B1 (ko) * 2016-04-04 2018-03-14 주식회사 네패스 반도체 패키지 및 그 제조방법
US10062583B2 (en) 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
WO2018031995A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
CN106356341A (zh) * 2016-08-31 2017-01-25 华为技术有限公司 一种半导体装置及制造方法
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US9900976B1 (en) * 2016-12-12 2018-02-20 Intel Corporation Integrated circuit package including floating package stiffener
EP3364181B1 (de) * 2017-02-21 2019-04-10 E+E Elektronik Ges.M.B.H. Feuchtesensoranordnung mit esd-schutz
JP7053579B2 (ja) * 2017-03-29 2022-04-12 デンカ株式会社 伝熱部材及びこれを含む放熱構造体
US10770405B2 (en) 2017-05-31 2020-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
US11121050B2 (en) * 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
DE102018106434B4 (de) 2017-06-30 2023-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleiter-Bauelement und Verfahren zu dessen Herstellung
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
WO2019014439A1 (en) * 2017-07-12 2019-01-17 Laird Technologies, Inc. ASSEMBLIES COMPRISING CARD LEVEL PROTECTIONS AND THERMAL INTERFACE MATERIALS
TW201911979A (zh) 2017-07-28 2019-03-16 晨星半導體股份有限公司 電路板以及封裝後晶片
US10410971B2 (en) * 2017-08-29 2019-09-10 Qualcomm Incorporated Thermal and electromagnetic interference shielding for die embedded in package substrate
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
JP6812951B2 (ja) * 2017-11-15 2021-01-13 オムロン株式会社 電子装置およびその製造方法
KR102086364B1 (ko) * 2018-03-05 2020-03-09 삼성전자주식회사 반도체 패키지
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US11282717B2 (en) 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10629512B2 (en) * 2018-06-29 2020-04-21 Xilinx, Inc. Integrated circuit die with in-chip heat sink
CN109065504B (zh) * 2018-06-29 2020-09-04 北京比特大陆科技有限公司 一种芯片防尘结构及计算设备、矿机
US11075133B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill structure for semiconductor packages and methods of forming the same
CN118213279A (zh) 2018-07-02 2024-06-18 Qorvo美国公司 Rf半导体装置及其制造方法
KR102566974B1 (ko) * 2018-07-11 2023-08-16 삼성전자주식회사 반도체 패키지
US10734301B2 (en) * 2018-09-10 2020-08-04 Qorvo Us, Inc. Semiconductor package with floating heat spreader and process for making the same
US11107747B2 (en) * 2018-09-19 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with composite thermal interface material structure and method of forming the same
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11594463B2 (en) * 2018-10-11 2023-02-28 Intel Corporation Substrate thermal layer for heat spreader connection
TWI708337B (zh) * 2018-11-22 2020-10-21 矽品精密工業股份有限公司 電子封裝件及其製法與散熱件
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
KR102654893B1 (ko) * 2019-01-17 2024-04-08 삼성전자주식회사 반도체 패키지 시스템
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
KR102677834B1 (ko) 2019-03-26 2024-06-21 삼성전자주식회사 반도체 패키지
KR102677777B1 (ko) 2019-04-01 2024-06-25 삼성전자주식회사 반도체 패키지
KR102562315B1 (ko) * 2019-10-14 2023-08-01 삼성전자주식회사 반도체 패키지
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US20230005976A1 (en) * 2020-01-22 2023-01-05 Hitachi Astemo, Ltd. Imaging device
US11342277B2 (en) * 2020-06-10 2022-05-24 Micron Technology, Inc. Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same
US11574853B2 (en) * 2020-06-30 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
US11705378B2 (en) * 2020-07-20 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US11676879B2 (en) * 2020-09-28 2023-06-13 Infineon Technologies Ag Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier
US11984392B2 (en) * 2020-09-28 2024-05-14 Infineon Technologies Ag Semiconductor package having a chip carrier with a pad offset feature
US12040315B2 (en) * 2020-10-20 2024-07-16 Innolux Corporation Electronic device
US11521905B2 (en) * 2020-10-21 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US20230119181A1 (en) * 2021-10-18 2023-04-20 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming RDL Hybrid Interposer Substrate
FR3128815B1 (fr) * 2021-10-29 2024-09-13 Stmicroelectronics Grenoble 2 Sas Refroidissement d'un dispositif électronique

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111322A (en) * 1996-05-20 2000-08-29 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
CN1433256A (zh) * 2002-01-18 2003-07-30 富士通株式会社 印刷电路板及其制造方法
US6919631B1 (en) * 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US20050224954A1 (en) * 2004-04-08 2005-10-13 Kelly Michael G Thermal dissipation in integrated circuit systems
CN1747158A (zh) * 2004-09-10 2006-03-15 株式会社东芝 半导体器件
US20060157847A1 (en) * 2005-01-19 2006-07-20 Chi-Hsing Hsu Chip package
US20070034998A1 (en) * 2004-03-11 2007-02-15 Siliconware Precision Industries Co., Ltd. Method for fabricating wafer level semiconductor package with build-up layer
US20080211081A1 (en) * 2006-12-05 2008-09-04 Samsung Electronics Co., Ltd. Planar multi semiconductor chip package and method of manufacturing the same
US20090289352A1 (en) * 2008-05-26 2009-11-26 Nec Electronics Corporation Semiconductor device and a method for manufacturing the semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479695B2 (en) * 2006-03-14 2009-01-20 Agere Systems Inc. Low thermal resistance assembly for flip chip applications
US8236617B2 (en) * 2010-06-04 2012-08-07 Stats Chippac, Ltd. Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111322A (en) * 1996-05-20 2000-08-29 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
US6919631B1 (en) * 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
CN1433256A (zh) * 2002-01-18 2003-07-30 富士通株式会社 印刷电路板及其制造方法
US20070034998A1 (en) * 2004-03-11 2007-02-15 Siliconware Precision Industries Co., Ltd. Method for fabricating wafer level semiconductor package with build-up layer
US20050224954A1 (en) * 2004-04-08 2005-10-13 Kelly Michael G Thermal dissipation in integrated circuit systems
CN1747158A (zh) * 2004-09-10 2006-03-15 株式会社东芝 半导体器件
US20060157847A1 (en) * 2005-01-19 2006-07-20 Chi-Hsing Hsu Chip package
US20080211081A1 (en) * 2006-12-05 2008-09-04 Samsung Electronics Co., Ltd. Planar multi semiconductor chip package and method of manufacturing the same
US20090289352A1 (en) * 2008-05-26 2009-11-26 Nec Electronics Corporation Semiconductor device and a method for manufacturing the semiconductor device

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579197A (zh) * 2012-07-19 2014-02-12 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
CN103579197B (zh) * 2012-07-19 2016-09-07 矽品精密工业股份有限公司 具有防电磁波干扰的半导体组件
CN110085523A (zh) * 2012-11-09 2019-08-02 安默克技术股份公司 半导体器件以及其制造方法
CN110085523B (zh) * 2012-11-09 2024-04-12 安默克技术股份公司 半导体器件以及其制造方法
CN105702664A (zh) * 2012-11-16 2016-06-22 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103000539A (zh) * 2012-11-16 2013-03-27 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103000539B (zh) * 2012-11-16 2016-05-18 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
CN103915408A (zh) * 2013-01-03 2014-07-09 矽品精密工业股份有限公司 半导体封装件及其制法
CN109712946A (zh) * 2013-03-29 2019-05-03 日月光半导体制造股份有限公司 半导体封装件
CN109712946B (zh) * 2013-03-29 2021-01-19 日月光半导体制造股份有限公司 半导体封装件
US10665468B2 (en) 2013-08-13 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
US10971371B2 (en) 2013-08-13 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
CN104377192A (zh) * 2013-08-13 2015-02-25 台湾积体电路制造股份有限公司 多芯片结构及其形成方法
US10037892B2 (en) 2013-08-13 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
US9653433B2 (en) 2013-08-13 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip structure and method of forming same
CN104377192B (zh) * 2013-08-13 2017-12-19 台湾积体电路制造股份有限公司 多芯片结构及其形成方法
CN103560090B (zh) * 2013-10-31 2016-06-15 中国科学院微电子研究所 一种用于PoP封装的散热结构的制作方法
CN103560117B (zh) * 2013-10-31 2016-09-14 中国科学院微电子研究所 一种用于PoP封装的散热结构
CN103560090A (zh) * 2013-10-31 2014-02-05 中国科学院微电子研究所 一种用于PoP封装的散热结构的制作方法
CN103560117A (zh) * 2013-10-31 2014-02-05 中国科学院微电子研究所 一种用于PoP封装的散热结构
US10771101B2 (en) 2013-11-05 2020-09-08 Skyworks Solutions, Inc. Devices and methods related to packaging of radio-frequency devices on ceramic substrates
CN104617053A (zh) * 2013-11-05 2015-05-13 天工方案公司 涉及陶瓷基板上射频装置封装的装置和方法
US9839167B2 (en) 2014-04-16 2017-12-05 Huawei Technologies Co., Ltd. Electronic component package structure and electronic device
CN103943610A (zh) * 2014-04-16 2014-07-23 华为技术有限公司 一种电子元件封装结构及电子设备
CN103943610B (zh) * 2014-04-16 2016-12-07 华为技术有限公司 一种电子元件封装结构及电子设备
US10091915B2 (en) 2014-04-16 2018-10-02 Huawei Technologies Co., Ltd. Electronic component package structure and electronic device
US10116555B2 (en) 2014-06-30 2018-10-30 Huawei Technologies Co., Ltd. Switch mode switching method, device, and system
CN104409447A (zh) * 2014-12-03 2015-03-11 三星半导体(中国)研究开发有限公司 包含嵌入式电容器的半导体封装件及其制备方法
CN106409774A (zh) * 2015-07-31 2017-02-15 富葵精密组件(深圳)有限公司 屏蔽罩、封装结构及封装结构制作方法
CN107230665A (zh) * 2016-03-24 2017-10-03 颀邦科技股份有限公司 微间距封装结构
US10515887B2 (en) 2016-09-20 2019-12-24 Mediatek Inc. Fan-out package structure having stacked carrier substrates and method for forming the same
CN107863326A (zh) * 2016-09-20 2018-03-30 联发科技股份有限公司 半导体封装结构及其形成方法
CN107887363A (zh) * 2016-09-29 2018-04-06 矽品精密工业股份有限公司 电子封装件及其制法
WO2019232749A1 (zh) * 2018-06-07 2019-12-12 华为技术有限公司 一种集成电路
CN112292916A (zh) * 2018-06-07 2021-01-29 华为技术有限公司 一种集成电路
CN112292916B (zh) * 2018-06-07 2022-02-11 华为技术有限公司 一种集成电路
CN112185911A (zh) * 2019-07-03 2021-01-05 美光科技公司 包含垂直集成电路的半导体组合件及其制造方法
US11664291B2 (en) 2019-07-03 2023-05-30 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
WO2021253912A1 (zh) * 2020-06-18 2021-12-23 华为技术有限公司 芯片封装器件及电子设备
CN111785715A (zh) * 2020-07-20 2020-10-16 潍坊歌尔微电子有限公司 一种芯片组件、芯片封装结构及电子设备

Also Published As

Publication number Publication date
DE102011086473A1 (de) 2012-05-24
JP2012109572A (ja) 2012-06-07
TW201234542A (en) 2012-08-16
US20120119346A1 (en) 2012-05-17
KR20120053332A (ko) 2012-05-25

Similar Documents

Publication Publication Date Title
CN102573279A (zh) 半导体封装及其形成方法
US9583430B2 (en) Package-on-package device
CN104637908B (zh) 半导体封装件和制造半导体封装件的方法
US10192855B2 (en) Semiconductor package and electronic device having heat dissipation pattern and/or heat conducting line
KR102214512B1 (ko) 인쇄회로기판 및 이를 이용한 반도체 패키지
US20140124907A1 (en) Semiconductor packages
US11004837B2 (en) Semiconductor device with improved heat dissipation
US20140124906A1 (en) Semiconductor package and method of manufacturing the same
US9147643B2 (en) Semiconductor package
US20130093073A1 (en) High thermal performance 3d package on package structure
US9356002B2 (en) Semiconductor package and method for manufacturing the same
US20070045804A1 (en) Printed circuit board for thermal dissipation and electronic device using the same
KR20120016925A (ko) 반도체 패키지 및 그 제조방법
KR100973722B1 (ko) 방열기를 가지는 전자 모듈 어셈블리
US7180166B2 (en) Stacked multi-chip package
CN102810527A (zh) 半导体封装件及其制造方法
KR20110099555A (ko) 적층형 반도체 패키지
CN108231711A (zh) 半导体存储器件以及具有其的芯片堆叠封装
US7525182B2 (en) Multi-package module and electronic device using the same
US7884465B2 (en) Semiconductor package with passive elements embedded within a semiconductor chip
US8692133B2 (en) Semiconductor package
US9236337B2 (en) Semiconductor package including a substrate having a vent hole
CN220474621U (zh) 线路载板及电子封装体
US11923264B2 (en) Semiconductor apparatus for discharging heat
CN116711068A (zh) 存储装置及存储装置模块

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120711