CN103579197A - 具有防电磁波干扰的半导体组件 - Google Patents

具有防电磁波干扰的半导体组件 Download PDF

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CN103579197A
CN103579197A CN201210264661.6A CN201210264661A CN103579197A CN 103579197 A CN103579197 A CN 103579197A CN 201210264661 A CN201210264661 A CN 201210264661A CN 103579197 A CN103579197 A CN 103579197A
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semiconductor subassembly
electromagnetic wave
layer
semiconductor
anti electromagnetic
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CN103579197B (zh
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宋泽世
江文荣
李信宏
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种具有防电磁波干扰的半导体组件，包括：基材，其具有贯穿的第一与第二导电穿孔；线路重布层，其形成于该基材上且具有电性连接垫；以及金属层，其形成于该线路重布层上且具有开口，以令该些电性连接垫位于该开口内而未电性连接该金属层，而令该第二导电穿孔与该金属层构成屏蔽结构，以避免电磁波由该线路重布层或该半导体组件的侧面进出而发生EMI现象。

Description

具有防电磁波干扰的半导体组件
技术领域
本发明涉及一种半导体组件，尤指一种具有防电磁波干扰的半导体组件。
背景技术
近年来，随着消费者对于电子产品功能多样化与体积轻薄化的需求与日俱增，在一定面积上整合更多芯片与功能遂成为封装技术的趋势，致使表面置放式的封装件已不符合半导体封装件微型化（miniaturization）的封装需求，所以遂发展出三维(3D)芯片堆栈技术。
所述的三维芯片结构是芯片立体堆栈化的整合，而目前三维芯片（3D IC）技术系将不同功能、性质或基板的芯片，各自采用最合适的工艺分别制作后，再利用硅穿孔（Through-Silicon Via,TSV）技术进行立体堆栈整合，以有效缩短线路传导路径的长度，因而能降低导通电阻，且能减少芯片面积，进而具有体积小、高整合度、高效率、降低耗电量等优点，并同时符合数字电子轻薄短小的需求。然而，堆栈的芯片间容易互相电磁波干扰（Electromagnetic Interference,EMI），所以各该芯片之间的EMI问题更显重要。
如图1所示，其提供一种3D芯片堆栈的半导体封装件1，通过于一承载件10上堆栈两具有导电硅穿孔110a,110b的芯片11a,11b，该两芯片11a,11b间借由一绝缘层14相结合，且该下层芯片11b与承载件10之间系填充底胶16，并以封装胶体13封装该些芯片11a,11b。
现有具有导电硅穿孔110a,110b的芯片11a,11b通过于其中一侧形成线路重布层（Redistribution layer,RDL）（图略），以结合导电组件15,111，以供堆栈其它半导体组件。
然而，现有半导体封装件1中，该些芯片11a,11b之间仅具有绝缘层14，而并无任何屏蔽结构，所以当该些芯片11a,11b在高速高频运作时，会产生较强的电磁辐射，而影响该两芯片11a,11b上的信号，即发生EMI现象，因而造成该半导体封装件1操作不良。
因此，如何克服上述现有技术的半导体封装件内部芯片发生EMI现象的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种不足，本发明的主要目的在于提供一种具有防电磁波干扰的半导体组件，以避免电磁波由该线路重布层或该半导体组件的侧面进出而发生EMI现象。
本发明的具有防电磁波干扰的半导体组件，包括：一基材，其具有相对的第一表面与第二表面，且该基材中具有连通该第一及第二表面的多个第一导电穿孔与多个第二导电穿孔；一线路重布层，其形成于该基材的第一表面上，且具有多个电性连接垫，该电性连接垫电性导通该第一导电穿孔；以及一第一金属层，其形成于该线路重布层上且电性导通该第二导电穿孔，使该第二导电穿孔与该第一金属层构成屏蔽结构，且该第一金属层具有多个第一开口，以令该电性连接垫位于该第一开口内而未电性连接该第一金属层。
前述的半导体组件中，该些电性连接垫接置至少一电子组件。其中，该电子组件为主动组件、被动组件或中介板。
本发明还提供一种半导体堆栈结构，包括：前述的具有防电磁波干扰的半导体组件，其作为第一半导体组件；以及第二半导体组件，其与该第一半导体组件的结构相同，且该第二半导体组件以其基材的第二表面的一侧接置于该第一半导体组件具该第一金属层的一侧上。
前述的半导体堆栈结构及其半导体组件中，该些第二导电穿孔排列成环形，以包围该些第一导电穿孔。
前述的半导体堆栈结构及其半导体组件中，还包括一绝缘保护层，其形成于该线路重布层与该第一金属层上，且外露该些电性连接垫。其中，该绝缘保护层还外露该第一金属层的部分表面。
前述的半导体堆栈结构及其半导体组件中，还包括一线路增层结构，其形成于该基材的第二表面上，且具有多个电性接触垫，该电性接触垫电性导通该第一导电穿孔。还包括一第二金属层，其形成于该线路增层结构上且电性导通该第二导电穿孔，使该屏蔽结构还具有该第二金属层，且该第二金属层具有多个第二开口，以令该电性接触垫位于该第二开口内而未连接该第二金属层。另包括一绝缘保护层，其形成于该线路增层结构与该第二金属层上，且外露该些电性接触垫。其中，该绝缘保护层还外露该第二金属层的部分表面。
由上可知，本发明的半导体堆栈结构及其具有防电磁波干扰的半导体组件，其借由第一金属层与第二导电穿孔作为屏蔽结构，以避免电磁波由该RDL或该具有防电磁波干扰的半导体组件的侧面进出，所以能避免该具有防电磁波干扰的半导体组件与其它邻近的电子组件（或第二半导体组件）发生EMI现象。
附图说明
图1为现有3D芯片堆栈的半导体封装件的剖视示意图；
图2A为本发明的具有防电磁波干扰的半导体组件的第一实施例的剖视示意图；
图2A’为图2A（省略绝缘保护层）的下视示意图；
图2B为图2A’（省略绝缘保护层）的另一实施例的下视示意图；
图3A为本发明的具有防电磁波干扰的半导体组件的第二实施例的剖视示意图；
图3B为图3A进行封装工艺后的封装件的剖视示意图；以及
图4为本发明的半导体堆栈结构的剖视示意图。
主要组件符号说明
1                 半导体封装件
10                承载件
100               导电通孔
11a,11b,4         芯片
110a,110b         导电硅穿孔
111,15,40,50,60   导电组件
13,6              封装胶体
14                绝缘层
16                底胶
2,2’               半导体组件
2a,2a’             屏蔽结构
20,30               基材
20a                 第一表面
20b,30b             第二表面
200a                第一导电穿孔
200b                第二导电穿孔
21                  线路重布层
210,240             介电层
211,241             线路层
212,242             导电盲孔
213                 电性连接垫
22                  第一金属层
220                 第一开口
221,221’,251,351   接地垫
222                 线路
23,26               绝缘保护层
230,260             开孔
24                  线路增层结构
243,343             电性接触垫
25                  第二金属层
250                 第二开口
3                   半导体堆栈结构
3a                  第二半导体组件
5                   电路板
L                   假想线。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“底”、“顶”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A、图2A’及图2B为本发明的具有防电磁波干扰的半导体组件2的第一实施例的剖面与下视示意图。如图2A所示，所述的半导体组件2包括：一基材20、一线路重布层（Redistribution layer,RDL）21、一第一金属层22以及一绝缘保护层23。
所述的基材20为中介板（interposer）、芯片或晶圆，且具有相对的第一表面20a（于本实施例中为底面）与第二表面20b（于本实施例中为顶面），且该基材20中具有连通该第一及第二表面20a,20b的多个第一导电穿孔200a与多个第二导电穿孔200b。
于本实施例中，该些第二导电穿孔200b排列成环形，以包围该些第一导电穿孔200a，如图2A’所示。
于另一实施例中，可设置多个电子组件（图略）于该第二表面20b上。
所述的线路重布层21通过线路增层工艺而形成于该基材20的第一表面20a上，且具有多个电性连接垫213，该些电性连接垫213电性导通该些第一导电穿孔200a。
于本实施例中，该线路重布层21具有至少一介电层210、形成于该介电层210上的线路层211及形成于该介电层210中的多个导电盲孔212，该些导电盲孔212电性连接该线路层211、第一与第二导电穿孔200a,200b，且该最外层的线路层211上具有该些电性连接垫213。
此外，该线路重布层21中可嵌埋被动组件，例如电容、电感、电阻等，且嵌埋的方式繁多，并无特别限制。
所述的第一金属层22形成于该线路重布层21的最外层的介电层210上，也就是该第一金属层22与该电性连接垫213位于同一层，且该第一金属层22电性导通该些第二导电穿孔200b，以令该些第二导电穿孔200b与该第一金属层22构成屏蔽结构2a。此外该第一金属层22具有多个第一开口220，以令该些电性连接垫213对应位于该些第一开口220内而未电性连接该第一金属层22，如图2A’所示。
于本实施例中，该第一金属层22可与该些电性连接垫213一同以图案化工艺完成。
所述的绝缘保护层23形成于该线路重布层21与该第一金属层22上，且外露该些电性连接垫213与该第一金属层22的部分表面（作为接地垫221之用，以供外接的电子组件进行接地）。
于本实施例中，该绝缘保护层23具有多个开孔230，以对应外露该些电性连接垫213与该接地垫221。
此外，该接地垫221可借由该绝缘保护层23的开孔230定义，如图2A’所示的假想线L，所以制作该些电性连接垫213时，不需制作该接地垫221。
另外，于另一实施例中，该接地垫221’可由该第一开口220定义出其形状，如图2B所示，也就是该接地垫221’与该些电性连接垫213一同制作，且借由线路222电性导通该接地垫221’与该第一金属层22。
本发明借由该第一金属层22作为屏蔽结构2a，可防止电磁辐射由该半导体组件2的底侧（即该线路重布层21）进出，以避免该半导体组件2与其它电子组件相互影响而发生EMI现象。
此外，借由该些第二导电穿孔200b作为屏蔽结构2a，可防止电磁辐射由该半导体组件2的侧面进出，以避免该半导体组件2与其它电子组件相互影响而发生EMI现象。当该些第二导电穿孔200b包围该些第一导电穿孔200a时，其防止EMI发生的功效更佳。
图3A及图3B为本发明的具有防电磁波干扰的半导体组件2’的第二实施例的剖面示意图。于第二实施例中，该基材20的第一表面20a为顶面，该第二表面20b为底面。
如图3A所示，所述的半导体组件2’还包括：一线路增层结构24及一第二金属层25。
所述的线路增层结构24形成于该基材20的第二表面20b上，且具有多个电性接触垫243，该些电性接触垫243系电性导通该第一导电穿孔200a。
于第二实施例中，该线路增层结构24与该线路重布层21的工艺及结构均大致相同，且该线路增层结构24的最外层的介电层240上具有该些电性接触垫243。
所述的第二金属层25形成于该线路增层结构24的最外层的介电层240上，也就是该第二金属层25与该电性接触垫243位于同一层，且该第二金属层25电性导通该第二导电穿孔200b，使该第二导电穿孔200b、该第一金属层22与该第二金属层25构成屏蔽结构2a’。此外该第二金属层25具有一第二开口250，以令该些电性接触垫243位于该第二开口250内而未连接该第二金属层25。
于第二实施例中，该第二金属层25借由该线路增层结构24的导电盲孔242电性导通该第二导电穿孔200b，且该第二金属层25可与该些电性接触垫243一同以图案化工艺完成。
此外，该半导体组件2’还包括一绝缘保护层26，其形成于该线路增层结构24与该第二金属层25上，且该绝缘保护层26具有多个开孔260，以对应外露该些电性接触垫243及该第二金属层25的部分表面（作为接地垫251之用）。
另外，于后续封装工艺中，如图3B所示，该电性连接垫213与该接地垫221可借由如焊球的导电组件40接置如主动组件、芯片4、晶圆、中介板或其它半导体组件结构的电子组件；该电性接触垫243与该接地垫251也可借由如焊球的导电组件50接置如封装基板或电路板5的电子装置。之后，形成封装胶体6以包覆该半导体组件2’与芯片4。
本发明借由该第一金属层22作为屏蔽结构2a’，可防止电磁辐射由该半导体组件2’的线路重布层21进出，以避免该半导体组件2’与芯片4相互影响而发生EMI现象。
此外，借由该第二金属层25作为屏蔽结构，可防止电磁辐射由该半导体组件2’的线路增层结构24进出，以避免该半导体组件2’与电路板5相互影响而发生EMI现象。
另外，制作该线路重布层21与该线路增层结构24时，一并完成该第一与第二金属层22,25的制作，所以于封装工艺后，不需于该封装胶体6上制作屏蔽层，不仅可简化工艺而降低成本，且可确保封装件内的各电子组件间的信号不会相互影响。
图4为应用第二实施例的半导体组件2’的剖面示意图。如图4所示，其提供一种半导体堆栈结构3，包括：第二实施例所述的半导体组件2’（用以作为第一半导体组件）以及另一半导体组件（用以作为第二半导体组件3a）。
该半导体组件2’设于该第二半导体组件3a上方。
所述的第二半导体组件3a与该半导体组件2’的结构相同，且该第二半导体组件3a以其基材30的第二表面30b的一侧接置于该半导体组件2’具该第一金属层22的一侧上，例如，借如焊球的导电组件60结合该第二半导体组件3a的该电性接触垫343及接地垫351与该半导体组件2’的电性连接垫213及接地垫221。
此外，于该半导体组件2’的线路增层结构24上可接置一主动组件，例如芯片。于另一实施例中，该第二半导体组件3a的基材30的第二表面30b具有多个主动组件设置于其上。另一半导体组件2’的结构大致与第二半导体组件3a相同，并堆栈于其上。
于该半导体堆栈结构3中，其借由该第一金属层22作为屏蔽结构2a，可防止电磁辐射由该半导体组件2’的线路重布层21进出，以避免该半导体组件2’与该第二半导体组件3a相互影响而发生EMI现象。
此外，可依此堆栈方式，堆栈多个第一实施例所述的半导体组件2或多个第二实施例所述的半导体组件2’。
综上所述，本发明的具有防电磁波干扰的半导体组件及其半导体堆栈结构，主要借由第一与第二金属层作为防止纵向EMI发生的屏蔽结构，而借由第二导电穿孔作为防止横向EMI发生的屏蔽结构，以避免于单一封装件中，内部各电子组件的信号相互影响，所以能有效避免于封装件内部发生EMI现象。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种具有防电磁波干扰的半导体组件，其包括：
一基材，其具有相对的第一表面与第二表面，且该基材中具有连通该第一及第二表面的多个第一导电穿孔与多个第二导电穿孔；
一线路重布层，其形成于该基材的第一表面上，且具有多个电性连接垫，该电性连接垫电性导通该第一导电穿孔；以及
一第一金属层，其形成于该线路重布层上且电性导通该第二导电穿孔，使该第二导电穿孔与该第一金属层构成屏蔽结构，且该第一金属层具有多个第一开口，以令该电性连接垫位于该第一开口内而未电性连接该第一金属层。
2.根据权利要求1所述的具有防电磁波干扰的半导体组件，其特征在于，该半导体组件作为第一半导体组件，且还包括与该第一半导体组件的结构相同的第二半导体组件，该第二半导体组件以其基材的第二表面的一侧接置于该第一半导体组件具该第一金属层的一侧上，以成为一半导体堆栈结构。
3.根据权利要求1所述的具有防电磁波干扰的半导体组件，其特征在于，该些电性连接垫接置至少一电子组件。
4.根据权利要求3所述的具有防电磁波干扰的半导体组件，其特征在于，该电子组件为主动组件、被动组件或中介板。
5.根据权利要求1、2或3所述的具有防电磁波干扰的半导体组件，其特征在于，该些第二导电穿孔排列成环形，以包围该些第一导电穿孔。
6.根据权利要求1、2或3所述的具有防电磁波干扰的半导体组件，其特征在于，该半导体组件还包括一绝缘保护层，其形成于该线路重布层与该第一金属层上，且外露该些电性连接垫。
7.根据权利要求6所述的具有防电磁波干扰的半导体组件，其特征在于，该绝缘保护层外露该第一金属层的部分表面。
8.根据权利要求1、2或3所述的具有防电磁波干扰的半导体组件，其特征在于，该半导体组件还包括一线路增层结构，其形成于该基材的第二表面上，且具有多个电性接触垫，该电性接触垫电性导通该第一导电穿孔。
9.根据权利要求8所述的具有防电磁波干扰的半导体组件，其特征在于，该半导体组件还包括一第二金属层，其形成于该线路增层结构上且电性导通该第二导电穿孔，使该屏蔽结构还具有该第二金属层，且该第二金属层具有多个第二开口，以令该电性接触垫位于该第二开口内而未连接该第二金属层。
10.根据权利要求9所述的具有防电磁波干扰的半导体组件，其特征在于，该半导体组件还包括一绝缘保护层，其形成于该线路增层结构与该第二金属层上，且外露该些电性接触垫。
11.根据权利要求10所述的具有防电磁波干扰的半导体组件，其特征在于，该绝缘保护层外露该第二金属层的部分表面。
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