CN1983533A - 用于封装半导体器件的方法 - Google Patents
用于封装半导体器件的方法 Download PDFInfo
- Publication number
- CN1983533A CN1983533A CNA2006101630757A CN200610163075A CN1983533A CN 1983533 A CN1983533 A CN 1983533A CN A2006101630757 A CNA2006101630757 A CN A2006101630757A CN 200610163075 A CN200610163075 A CN 200610163075A CN 1983533 A CN1983533 A CN 1983533A
- Authority
- CN
- China
- Prior art keywords
- stack assemblies
- semiconductor device
- encapsulate
- conductive
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 238000000429 assembly Methods 0.000 claims description 57
- 230000000712 assembly Effects 0.000 claims description 57
- 238000005538 encapsulation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 3
- 239000006071 cream Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 12
- 230000006870 function Effects 0.000 description 8
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000012812 sealant material Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 101001027796 Homo sapiens Male-specific lethal 1 homolog Proteins 0.000 description 1
- 101000639802 Homo sapiens U2 small nuclear ribonucleoprotein B'' Proteins 0.000 description 1
- 102100034461 U2 small nuclear ribonucleoprotein B'' Human genes 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
一种用于封装半导体器件的方法包括在基础衬底(10)中形成通孔(12)并且在所述基础衬底(10)的第一面(16)上沉积导电材料(14)来形成导电层(18)使得所述导电材料(14)填入所述通孔(12)。所述导电层(18)被图案化并蚀刻以便形成互连轨迹和焊盘(22)。在所述焊盘(22)上形成导电支柱(24)使得所述导电支柱(24)延伸通过各自的通孔(12)。
Description
技术领域
本发明总体上涉及半导体器件的封装,并且尤其涉及一种用于形成堆叠封装(stacked package)的方法。
背景技术
伴随电子设备变得复杂化,需要在较小的封装中实现较多的功能。堆叠小片和堆叠封装三维(3D)封装已经被开发出来用以满足此要求。典型情况下,通过将多个芯片相互堆叠来形成堆叠小片封装。堆叠小片封装中的芯片可以借助丝焊连接或倒装芯片连接来电耦合。另一方面,通过将多个封装相互堆叠来形成堆叠封装,其中每个封装包含单个芯片。
然而,形成堆叠小片封装存在多个问题。例如,当形成具有丝焊连接的堆叠封装时,通常上面的芯片最好小于下面的芯片一定量,以用于进行丝焊连接所要求的区域。因此,每个相继的上面芯片的安装区域最好逐渐变小,由此对可以堆叠的封装数目带来限制。
此外,通常并不依照阵列(MAP)格式来处理堆叠封装;通常使用圆顶封装(glob top encapsulation)或中心浇口制模来处理堆叠封装并且只在分离之后才进行堆叠。为此,要求较长的制造周期时间来形成堆叠封装。与形成堆叠封装相关联的其它问题包括在堆叠之前很难查明小片是否工作正常,以及对于相同数目的小片堆叠来说会带来较大的整体封装厚度。
考虑到上述情况,需要一种用于以低成本形成具有增加的功能的可靠的堆叠封装。因此,本发明的目的是提供一种用于制造可靠的、低成本、高功能的堆叠封装。
发明内容
为了实现上述目的和优点等,本发明提供了一种用于封装半导体器件的方法。所述方法包括步骤:在基础衬底中形成多个通孔并且在所述基础衬底的第一面上沉积导电材料以便形成导电层。导电材料填入多个通孔。导电层被图案化并蚀刻以便形成多个互连轨迹和多个焊盘(pad)。在多个焊盘上形成多个导电支柱(support)。导电支柱延伸到多个通孔中相应的通孔。
本发明还提供了一种用于封装半导体器件的方法,包括步骤:在基础衬底中形成多个通孔,在所述基础衬底的第一面上沉积导电材料以便形成导电层,并且图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘。导电材料至少部分填入所述多个通孔。在焊盘上形成多个导电支柱。所述导电支柱基本上彼此平行,基本上垂直于基础衬底,并且延伸到多个通孔中的相应通孔。至少一个半导体小片电耦合到所述互连轨迹和焊盘。
本发明进一步提供了一种用于封装半导体器件的方法,包括步骤:在基础衬底中形成多个通孔,在所述基础衬底的第一面上沉积导电材料以便形成导电层,其中所述导电材料填入所述通孔,并且图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘。在多个焊盘上形成多个基本上平行的导电支柱。所述导电支柱基本上垂直于基础衬底,并且延伸到多个通孔中相应的通孔。向互连轨迹、焊盘和导电支柱施加无电抛光(electroless finish)。多个小片电耦合到互连轨迹和焊盘,并且执行模制操作以便封装所述小片,其中露出每个导电支柱的至少一端。依照这种方式形成第一可堆叠组件。形成与第一可堆叠组件基本上类似的第二可堆叠组件。通过在第一可堆叠组件上堆叠第二可堆叠组件来形成堆叠组件。第一和第二可堆叠组件借助导电支柱相互电耦合。然后堆叠组件被切割或分离为多个堆叠封装。
附图说明
当结合附图阅读时可以更好地理解本发明优选实施例的以下详细说明。本发明以举例形式来说明并且不受附图的限制,其中相似的附图标记表示类似的部件。
图1到6是图示用于依照本发明实施例形成多个可堆叠半导体器件的方法的放大剖面图;
图7是图示用于依照本发明实施例堆叠多个半导体器件的方法的放大剖视图;和
图8是依照本发明实施例的堆叠半导体器件的放大剖视图。
具体实施方式
下面结合附图所阐明的详细说明意在为本发明优选实施例的描述,而并不意在表示可以实施本发明的唯一形式。应当理解,相同的或等同的功能可以由本发明的精神和范围内所包含的不同实施例来实现。
图1-8图示了用于依照本发明实施例来封装半导体器件的方法。现在参照图1,示出了厚度至少大约为1.0mil的基础衬底10。尽管在此特定的例子中指定了基础衬底10的厚度,然而应当理解,本发明并不受所述基础衬底10厚度的限制。如本领域技术人员所知,基础衬底10可以由聚酰亚胺(Polyimide PI)条带或其它非导电材料制成。
现在参照图2,示出在基础衬底10中形成多个通孔12。可以通过钻孔或本领域技术人员所知的其它适当方法来形成通孔12。通孔12的尺寸从大约200μm到大约600μm,并且所述通孔12位于或处于每个衬底10的周边。
图3示出了导电材料14,例如沉积在基础衬底10的第一面16上以用于形成导电层18的铜。如同所见,通孔12填充有导电材料14。在沉积导电材料14期间,优选地屏蔽基础衬底10的第二面20。在此特定的例子中,导电层18大约有5微米(μm)厚。然而应当理解,本发明并不受导电层18厚度的限制。
现在参照图4,导电层18被图案化并蚀刻以便形成多个互连轨迹和多个焊盘22。如同所示,在焊盘22上形成多个导电支柱24,每个导电支柱24延伸通过相应的通孔12。导电支柱24基本上彼此平行并且基本上垂直于基础衬底10。
导电支柱24由诸如铜之类的导电材料形成,并且可以通过诸如电镀之类的附加工艺形成。在此特定的例子中,每个导电支柱24具有大约200μm的宽度。然而应当理解,本发明并不受导电支柱24的宽度或材料类型或者用于形成所述导电支柱24的方法的限制。
使用在本领域中已知的标准平版印刷技术(例如光刻)来图案化并蚀刻互连轨迹和焊盘22。在焊盘22上形成导电支柱24之前使用抗蚀剂掩模来遮盖互连轨迹。这种抗蚀剂掩模在本领域中是已知的。此后从互连轨迹移除所述抗蚀剂掩模。
在一个实施例中,向互连轨迹、焊盘22和导电支柱24施加无电抛光以便防止氧化作用。镍、金或镍金合金可以用于无电抛光。然而应当理解,本发明并不受用于无电抛光的金属或金属合金类型的限制。
图5示出了电耦合到基础衬底10的至少一个小片26。所述小片26可以是诸如数字信号处理器(DSP)之类的处理器、诸如存储器地址发生器之类的特定功能电路或执行任何其它类型的功能。此外,所述小片26不局限于诸如CMOS之类的特定技术,或根据任何特定的晶片技术得出。此外,本领域技术人员可以理解,本发明可以适应各种小片尺寸。典型例子是具有大约为7mm×7mm的尺寸的逻辑小片。尽管图5只示出了三个小片,然而应当理解,根据衬底尺寸、小片的尺寸和所产生器件所要求的功能,可以把更多或更少的小片附着到所述衬底。在此特定的例子中,小片26经由多个倒装芯片凸点28耦合到衬底接合焊盘(bonding pad)22。然而应当理解,本发明不局限于倒装芯片应用。在替换实施例中,小片26例如可以经由丝焊电耦合到衬底接合焊盘22(参见图7)。
导电支柱24的目的是实现堆叠封装之间的电连接。如从图5中可以看出,每个导电支柱24的高度与小片26的高度和最终封装的高度相关。如果小片利用倒装芯片凸点28耦合到所述焊盘22,那么导电支柱24必须具有至少等于小片26的高度加上所述倒装芯片凸点28的高度再加上衬底10的高度的高度。尽管图5示出了导电支柱24延伸到小片26的顶部之外,然而导电支柱24可以与所述小片26的顶部齐平。如果小片26利用线路(参见图7中的线路27,下面将要描述)耦合到焊盘22,那么导电支柱的高度应当延伸到所述小片26的顶部之外略微超出线环的高度。在一个示例性实施例中,对于具有高度大约为200μm的小片26以及具有高度大约为100μm的倒装芯片凸点28来说,导电支柱24具有至少大约400μm的高度。
现在参照图6,如同所示,利用密封剂材料30来封装小片26以便形成第一可堆叠组件32。执行诸如过模制(over moulding)之类的模制操作来封装小片26,最好使每个导电支柱24的两端34暴露出来。密封剂材料30可以包括公知的可买到的模制材料,诸如塑料或环氧树脂。过模制消除了对未充满(under fill)工艺的需要,由此降低了处理成本。未充满的消除还在260℃把封装级别增加到湿度敏感性级别1(Moisture Sensitivity Level1 MSL1)。
现在参照图7,第一可堆叠组件40被堆叠在第二可堆叠组件42上并与其电耦合以便形成堆叠组件44。为了图示本发明的可堆叠组件的各种实施例,第一可堆叠组件40具有利用倒装芯片凸点28附着于焊盘22的小片26,并且导电支柱24具有与所述小片26的顶表面齐平的顶端。第二可堆叠组件42具有小片45和导电支柱48,所述小片45附着于所述衬底10并且经由线路46与焊盘22电耦合,并且所述导电支柱48延伸到所述小片45的顶表面之外。本领域技术人员应当理解,可以使用相同的工艺来形成可堆叠组件40和42(例如,都具有倒装芯片附着的小片)并且它们都具有相同的维数。
在此特定的例子中,第一和第二可堆叠组件40和42被对准,使得第一可堆叠组件40的导电支柱24与第二可堆叠组件42的导电支柱48对准,并且所述导电支柱24和48以及因而所述第一和第二可堆叠组件40和42与焊球50电连接。可以使用已知的焊球附着工艺来把焊球50固定到第一和第二可堆叠组件40和42。不过应当理解,本发明不局限于这种堆叠方法。也可以使用其它堆叠方法,诸如粘贴膏印刷和回流;非均匀性导电薄膜和聚合物导线粘贴。在替换实施例中,可以把由导电材料(例如铜)制成的第二导电层沉积在堆叠组件44的选择性部分上并且可以把分立的无源器件附着到所述第二导电层。尽管在此实施例中只图示了两个可堆叠组件40和42,然而应当理解,依照本发明可以把依照阵列(MAP)格式的多个可堆叠组件组装为一个在另一个上面。
图8示出了由两个可堆叠封装62形成的堆叠组件60。可堆叠封装62使用作为可堆叠封装阵列的一部分来形成、堆叠,继而堆叠阵列被分离或切割以便形成堆叠组件60。堆叠组件60可以被直接附着到诸如表面安装技术(Surface Mount Technology SMT)中的板衬底上。因为每个堆叠组件60包括多个小片26,所以在单个小片足迹(footprint)区域内实现了增加的功能。
本发明还提供了一种可堆叠组件,包括其中形成有多个通孔的基础衬底;至少在所述基础衬底的第一面上形成的导电材料,用于形成导电层,其中所述导电材料至少部分地填充所述多个通孔并且作为图案化和蚀刻层以用于形成多个互连轨迹和多个焊盘;和在所述多个焊盘上形成的多个导电支柱,其中所述多个导电支柱延伸通过多个通孔中相应的通孔。可堆叠组件可以进一步包括半导体集成电路(IC),所述半导体集成电路诸如经由倒装芯片凸点、丝焊或直接芯片附着而附着于焊盘,还包括用于覆盖所述IC和焊盘的密封剂,同时优选使导电支柱的端部露出。然后,可以堆叠附加的可堆叠组件,一个在另一个上面,其中通过导电支柱来电耦合所述可堆叠组件。
如从上述显然可以看出,本发明提供了一种用于封装半导体器件的方法,所述方法与现有工艺相比更有益处。作为一个例子,可以依照MAP格式来进行依照本发明的半导体器件的封装,由此实现了高生产量。另外,依照本发明,因为可以在凸点形成之后并且在封装之前测试小片,所以可以把已知良好的小片用于封装半导体器件。另外,通过直接地探测导电支柱的暴露端还可以在不损坏小片的情况下实施对每个封装的最后测试。此外,由于在本发明中不要求上面的封装一定小于下面的封装,所以不会限制可以堆叠的封装数目。此外,利用本发明可以制作薄的可堆叠组件。
由于只使用单层基础衬底,不要求未充满,并且可以使用现有设备和工艺来实现本发明,所以利用本发明可以实现低制造成本。因为互连轨迹位于基础衬底上,允许多功能硅小片处于堆叠中,所以本发明还实现了高功能。利用本发明可实现的其它优点包括高密度的输入和输出(IO)堆叠因为在基础衬底上迂回的细线延伸到非常高密度的封装,由于消除了硅对印刷电路板(PCB)的热失配而增加了可靠性,以及所使用的焊料和基础衬底类型的灵活性。
因而,依照本发明很明显提供了一种用于封装半导体器件的方法,其完全满足先前所阐述的优点。尽管已经参考其具体实施例描述并图示了本发明,然而并不意在将本发明限于这些说明性实施例。本领域技术人员认识到在不脱离本发明精神的情况下可以进行修改和变化。例如,导电层和导电支柱不局限于铜,而是可以由在本领域中所使用的任何导电材料制成。如先前所阐述,本发明不受基础衬底维数、导电层、导电支柱或小片尺寸的限制。器件配置也不限于倒装芯片和丝焊应用。应当理解,本发明可以应用于封装中的系统(System InPackage SIP)技术。此外,本发明不局限于这里所描述或图示的那些半导体小片类型。因此,本发明意在包含属于所附权利要求范围内的所有这些变化和修改。
Claims (20)
1.一种用于封装可堆叠半导体器件的方法,包括步骤:
在基础衬底中形成多个通孔;
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层,其中所述导电材料至少部分填充所述多个通孔;
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘;以及
在所述多个焊盘上形成多个导电支柱,其中所述多个导电支柱延伸通过所述多个通孔中的相应通孔。
2.如权利要求1所述的用于封装可堆叠半导体器件的方法,还包括把所述基础衬底的第二面与所述导电材料相屏蔽。
3.如权利要求1所述的用于封装可堆叠半导体器件的方法,其中所述导电层大约为5微米厚。
4.如权利要求1所述的用于封装可堆叠半导体器件的方法,其中所述导电材料为铜。
5.如权利要求4所述的用于封装可堆叠半导体器件的方法,其中所述多个导电支柱用铜制成。
6.如权利要求1所述的用于封装可堆叠半导体器件的方法,还包括向所述多个互连轨迹、多个焊盘和多个导电支柱施加无电抛光。
7.如权利要求6所述的用于封装可堆叠半导体器件的方法,其中所述无电抛光包括镍、金和镍金合金之一。
8.如权利要求1所述的用于封装可堆叠半导体器件的方法,其中每个导电支柱具有大约200微米的宽度。
9.如权利要求8所述的用于封装可堆叠半导体器件的方法,其中所述多个导电支柱基本上彼此平行。
10.如权利要求9所述的用于封装可堆叠半导体器件的方法,其中所述多个导电支柱基本上垂直于所述基础衬底。
11.如权利要求1所述的用于封装可堆叠半导体器件的方法,还包括把至少一个小片电耦合到所述多个焊盘。
12.如权利要求11所述的用于封装可堆叠半导体器件的方法,其中所述小片经由丝焊电耦合到衬底接合焊盘。
13.如权利要求11所述的用于封装可堆叠半导体器件的方法,其中所述小片经由倒装芯片凸点电耦合到衬底接合焊盘。
14.如权利要求11所述的用于封装可堆叠半导体器件的方法,还包括执行用于封装所述小片的模制操作,其中露出每个导电支柱的至少一端。
15.如权利要求14所述的用于封装可堆叠半导体器件的方法,其中多个小片被电耦合到所述互连轨迹和焊盘并且封装在其上,由此形成第一可堆叠组件,所述方法还包括:
在所述第一可堆叠组件上堆叠第二可堆叠组件,其中所述第一和第二可堆叠组件彼此电耦合以便形成堆叠组件;以及
把所述堆叠组件分离为多个堆叠封装。
16.如权利要求15所述的用于封装可堆叠半导体器件的方法,还包括在所述堆叠组件上沉积第二导电层,并且在所述第二导电层上附着分立的无源器件。
17.如权利要求15所述的用于封装可堆叠半导体器件的方法,其中使用焊球附着、粘贴膏印刷和回流、非均匀性导电薄膜和聚合物导体粘贴之一来堆叠多个可堆叠组件。
18.一种用于封装半导体器件的方法,包括步骤:
在基础衬底中形成多个通孔;
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层,其中所述导电材料至少部分填充所述多个通孔;
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘;
在所述多个焊盘上形成多个基本上平行的导电支柱,其中所述多个导电支柱基本上垂直于所述基础衬底并且延伸通过多个通孔中相应的通孔;以及
把至少一个小片电耦合到所述互连轨迹和焊盘。
19.如权利要求18所述的用于封装可堆叠半导体器件的方法,其中多个小片被电耦合到所述互连轨迹和焊盘,所述方法还包括:
封装所述多个小片和导电支柱,其中露出所述导电支柱的至少一端,由此形成第一可堆叠组件;
形成基本上类似于所述第一可堆叠组件的第二可堆叠组件;
通过在所述第一可堆叠组件上形成第二可堆叠组件来形成堆叠组件,其中所述第一和第二可堆叠组件通过所述导电支柱彼此电耦合;并且
把所述堆叠组件分离为多个堆叠封装。
20.一种用于封装半导体器件的方法,包括步骤:
在基础衬底中形成多个通孔;
至少在所述基础衬底的第一面上沉积导电材料以便形成导电层,其中所述导电材料至少部分填充所述多个通孔;
图案化并蚀刻所述导电层以便形成多个互连轨迹和多个焊盘;
在所述多个焊盘上形成多个基本上平行的导电支柱,其中所述多个导电支柱基本上垂直于所述基础衬底并且延伸通过多个通孔中相应的通孔;
向所述多个互连轨迹、多个焊盘和多个导电支柱施加无电抛光;
把多个小片电耦合到所述互连轨迹和焊盘;
执行用于封装所述多个小片的模制操作,其中露出每个导电支柱的至少一端,由此形成第一可堆叠组件;
形成基本上类似于所述第一可堆叠组件的第二可堆叠组件;
通过在所述第一可堆叠组件上形成第二可堆叠组件来形成堆叠组件,其中所述第一和第二可堆叠组件通过所述导电支柱彼此电耦合;及
把所述堆叠组件分离为多个堆叠封装。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/290,300 | 2005-11-30 | ||
US11/290,300 US7344917B2 (en) | 2005-11-30 | 2005-11-30 | Method for packaging a semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1983533A true CN1983533A (zh) | 2007-06-20 |
CN1983533B CN1983533B (zh) | 2010-11-03 |
Family
ID=38088040
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2006101630757A Expired - Fee Related CN1983533B (zh) | 2005-11-30 | 2006-11-30 | 用于封装半导体器件的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7344917B2 (zh) |
JP (1) | JP5661225B2 (zh) |
KR (1) | KR101349985B1 (zh) |
CN (1) | CN1983533B (zh) |
SG (1) | SG132619A1 (zh) |
TW (1) | TWI325626B (zh) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102299143A (zh) * | 2010-06-25 | 2011-12-28 | 台湾积体电路制造股份有限公司 | 半导体元件 |
CN102386113A (zh) * | 2010-09-03 | 2012-03-21 | 新科金朋有限公司 | 一种半导体器件及其制造方法 |
CN102456673A (zh) * | 2010-10-25 | 2012-05-16 | 环旭电子股份有限公司 | 芯片堆叠结构 |
CN102983106A (zh) * | 2011-09-02 | 2013-03-20 | 台湾积体电路制造股份有限公司 | 层叠封装结构和系统级封装结构的封装和功能测试 |
CN103579197A (zh) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | 具有防电磁波干扰的半导体组件 |
CN104576579A (zh) * | 2015-01-27 | 2015-04-29 | 江阴长电先进封装有限公司 | 一种三维叠层封装结构及其封装方法 |
US9177901B2 (en) | 2009-08-21 | 2015-11-03 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
USRE48111E1 (en) | 2009-08-21 | 2020-07-21 | JCET Semiconductor (Shaoxing) Co. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
Families Citing this family (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
SG120200A1 (en) | 2004-08-27 | 2006-03-28 | Micron Technology Inc | Slanted vias for electrical circuits on circuit boards and other substrates |
US7300857B2 (en) | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
KR101313391B1 (ko) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | 적층형 패키징 |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US7262134B2 (en) | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
US7629249B2 (en) | 2006-08-28 | 2009-12-08 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US7902643B2 (en) * | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US8367471B2 (en) * | 2007-06-15 | 2013-02-05 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
SG149710A1 (en) * | 2007-07-12 | 2009-02-27 | Micron Technology Inc | Interconnects for packaged semiconductor devices and methods for manufacturing such devices |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
SG150410A1 (en) * | 2007-08-31 | 2009-03-30 | Micron Technology Inc | Partitioned through-layer via and associated systems and methods |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US7884015B2 (en) | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7968378B2 (en) * | 2008-02-06 | 2011-06-28 | Infineon Technologies Ag | Electronic device |
US20090243058A1 (en) * | 2008-03-31 | 2009-10-01 | Yamaha Corporation | Lead frame and package of semiconductor device |
SG142321A1 (en) | 2008-04-24 | 2009-11-26 | Micron Technology Inc | Pre-encapsulated cavity interposer |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
US7923304B2 (en) * | 2009-09-10 | 2011-04-12 | Stats Chippac Ltd. | Integrated circuit packaging system with conductive pillars and method of manufacture thereof |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) * | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) * | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
US9159708B2 (en) | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US8836136B2 (en) | 2011-10-17 | 2014-09-16 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
CN103456645B (zh) * | 2013-08-06 | 2016-06-01 | 江阴芯智联电子科技有限公司 | 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法 |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
CN103943588A (zh) * | 2014-03-20 | 2014-07-23 | 张轩 | 一种用于超大功率电器的引线框架 |
CN103943586A (zh) * | 2014-03-20 | 2014-07-23 | 张轩 | 一种引线框架 |
CN103943587A (zh) * | 2014-03-20 | 2014-07-23 | 张轩 | 一种用于较大功率电器的引线框架 |
CN103943589A (zh) * | 2014-03-20 | 2014-07-23 | 张轩 | 一种压有凸台的引线框架 |
CN103943592A (zh) * | 2014-03-26 | 2014-07-23 | 张轩 | 一种带防震沟的引线框架 |
CN103943591A (zh) * | 2014-03-26 | 2014-07-23 | 张轩 | 一种带锁料口的引线框架 |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9842825B2 (en) * | 2014-09-05 | 2017-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrateless integrated circuit packages and methods of forming same |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9530749B2 (en) | 2015-04-28 | 2016-12-27 | Invensas Corporation | Coupling of side surface contacts to a circuit platform |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US10056528B1 (en) * | 2017-03-31 | 2018-08-21 | Intel Corporation | Interposer structures, semiconductor assembly and methods for forming interposer structures |
US10418255B2 (en) * | 2017-12-01 | 2019-09-17 | Micron Technology, Inc. | Semiconductor device packages and related methods |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US675268A (en) * | 1901-01-12 | 1901-05-28 | Library Bureau | Card-holder for type-writing machines. |
JP2000252411A (ja) * | 1999-03-03 | 2000-09-14 | Mitsui High Tec Inc | スタックド半導体装置及びその製造方法 |
JP3833859B2 (ja) * | 1999-10-14 | 2006-10-18 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3670917B2 (ja) * | 1999-12-16 | 2005-07-13 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US6483180B1 (en) | 1999-12-23 | 2002-11-19 | National Semiconductor Corporation | Lead frame design for burr-free singulation of molded array packages |
JP4251421B2 (ja) * | 2000-01-13 | 2009-04-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
EP1264520A4 (en) * | 2000-03-10 | 2007-02-28 | Chippac Inc | PACKAGING STRUCTURE AND METHOD |
DE10056572A1 (de) * | 2000-11-15 | 2002-05-23 | Bayerische Motoren Werke Ag | Brennkraftmaschine mit einem elektromagnetischen, auf einem Zylinderkopf angeordneten Aktor |
JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
JP3798620B2 (ja) * | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
JP2002343904A (ja) * | 2001-05-21 | 2002-11-29 | Matsushita Electric Ind Co Ltd | 半導体装置 |
TW497236B (en) | 2001-08-27 | 2002-08-01 | Chipmos Technologies Inc | A soc packaging process |
JP2003163458A (ja) * | 2001-11-29 | 2003-06-06 | Fujitsu Ltd | 多層配線基板及びその製造方法 |
TW536764B (en) | 2002-04-30 | 2003-06-11 | Walsin Advanced Electronics | Method for multi-chip package and structure thereof |
JP2003347722A (ja) * | 2002-05-23 | 2003-12-05 | Ibiden Co Ltd | 多層電子部品搭載用基板及びその製造方法 |
US6861288B2 (en) | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
JP2004273563A (ja) * | 2003-03-05 | 2004-09-30 | Shinko Electric Ind Co Ltd | 基板の製造方法及び基板 |
JP4204989B2 (ja) * | 2004-01-30 | 2009-01-07 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP4719424B2 (ja) * | 2004-03-15 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | パッド |
JP5094323B2 (ja) * | 2007-10-15 | 2012-12-12 | 新光電気工業株式会社 | 配線基板の製造方法 |
-
2005
- 2005-11-30 US US11/290,300 patent/US7344917B2/en not_active Expired - Fee Related
-
2006
- 2006-11-15 SG SG200607938-8A patent/SG132619A1/en unknown
- 2006-11-17 TW TW095142507A patent/TWI325626B/zh not_active IP Right Cessation
- 2006-11-29 JP JP2006321047A patent/JP5661225B2/ja not_active Expired - Fee Related
- 2006-11-30 KR KR1020060119486A patent/KR101349985B1/ko not_active IP Right Cessation
- 2006-11-30 CN CN2006101630757A patent/CN1983533B/zh not_active Expired - Fee Related
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9893045B2 (en) | 2009-08-21 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
USRE48408E1 (en) | 2009-08-21 | 2021-01-26 | Jcet Semiconductor (Shaoxing) Co., Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US9177901B2 (en) | 2009-08-21 | 2015-11-03 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
US9240380B2 (en) | 2009-08-21 | 2016-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
USRE48111E1 (en) | 2009-08-21 | 2020-07-21 | JCET Semiconductor (Shaoxing) Co. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
CN102299143A (zh) * | 2010-06-25 | 2011-12-28 | 台湾积体电路制造股份有限公司 | 半导体元件 |
CN102299143B (zh) * | 2010-06-25 | 2014-09-10 | 台湾积体电路制造股份有限公司 | 半导体元件 |
CN102386113A (zh) * | 2010-09-03 | 2012-03-21 | 新科金朋有限公司 | 一种半导体器件及其制造方法 |
CN102386113B (zh) * | 2010-09-03 | 2016-06-22 | 新科金朋有限公司 | 一种半导体器件及其制造方法 |
CN102456673A (zh) * | 2010-10-25 | 2012-05-16 | 环旭电子股份有限公司 | 芯片堆叠结构 |
CN102983106A (zh) * | 2011-09-02 | 2013-03-20 | 台湾积体电路制造股份有限公司 | 层叠封装结构和系统级封装结构的封装和功能测试 |
CN102983106B (zh) * | 2011-09-02 | 2016-01-13 | 台湾积体电路制造股份有限公司 | 层叠封装结构和系统级封装结构的封装和功能测试 |
CN103579197A (zh) * | 2012-07-19 | 2014-02-12 | 矽品精密工业股份有限公司 | 具有防电磁波干扰的半导体组件 |
CN103579197B (zh) * | 2012-07-19 | 2016-09-07 | 矽品精密工业股份有限公司 | 具有防电磁波干扰的半导体组件 |
CN104576579B (zh) * | 2015-01-27 | 2017-12-15 | 江阴长电先进封装有限公司 | 一种三维叠层封装结构及其封装方法 |
CN104576579A (zh) * | 2015-01-27 | 2015-04-29 | 江阴长电先进封装有限公司 | 一种三维叠层封装结构及其封装方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2007158331A (ja) | 2007-06-21 |
JP5661225B2 (ja) | 2015-01-28 |
SG132619A1 (en) | 2007-06-28 |
US20070122940A1 (en) | 2007-05-31 |
KR101349985B1 (ko) | 2014-01-13 |
CN1983533B (zh) | 2010-11-03 |
KR20070057038A (ko) | 2007-06-04 |
TW200735325A (en) | 2007-09-16 |
US7344917B2 (en) | 2008-03-18 |
TWI325626B (en) | 2010-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1983533B (zh) | 用于封装半导体器件的方法 | |
US6448661B1 (en) | Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof | |
US7807502B2 (en) | Method for fabricating semiconductor packages with discrete components | |
EP2130224B1 (en) | Apparatus for packaging semiconductor devices | |
TWI221327B (en) | Multi-chip package and process for forming the same | |
US9583475B2 (en) | Microelectronic package with stacked microelectronic units and method for manufacture thereof | |
US7728437B2 (en) | Semiconductor package form within an encapsulation | |
CN110364513B (zh) | 半导体芯片和包括半导体芯片的半导体封装 | |
TW200828523A (en) | Multi-component package with both top and bottom side connection pads for three-dimensional packaging | |
US8470640B2 (en) | Method of fabricating stacked semiconductor package with localized cavities for wire bonding | |
US8471375B2 (en) | High-density fine line structure and method of manufacturing the same | |
KR101047139B1 (ko) | 단층 보드온칩 패키지 기판 및 그 제조방법 | |
US7955953B2 (en) | Method of forming stacked die package | |
US7745260B2 (en) | Method of forming semiconductor package | |
US12062597B2 (en) | Three dimensional package for semiconductor devices and external components | |
US20090001547A1 (en) | High-Density Fine Line Structure And Method Of Manufacturing The Same | |
US20080303150A1 (en) | High-Density Fine Line Structure And Method Of Manufacturing The Same | |
CN115148714A (zh) | 半导体封装方法及半导体封装结构 | |
CN115148715A (zh) | 半导体封装方法及半导体封装结构 | |
KR20010060879A (ko) | 볼 그리드 어레이 패키지와 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Texas in the United States Patentee after: NXP America Co Ltd Address before: Texas in the United States Patentee before: Fisical Semiconductor Inc. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101103 Termination date: 20181130 |