CN102299143B - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN102299143B
CN102299143B CN201010583364.9A CN201010583364A CN102299143B CN 102299143 B CN102299143 B CN 102299143B CN 201010583364 A CN201010583364 A CN 201010583364A CN 102299143 B CN102299143 B CN 102299143B
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China
Prior art keywords
nude film
substrate
dielectric layer
layer
electrical couplings
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CN201010583364.9A
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CN102299143A (zh
Inventor
施应庆
林俊成
邱文智
郑心圃
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Abstract

本发明提供一种包含中介层的半导体元件，其中中介层包括：一基板；以及至少一介电层形成于基板上。多个基板穿孔(TSVs)穿过基板。第一金属凸块形成于介电层中且与多个基板穿孔电性耦合。第二金属凸块位于介电层上。裸片埋设于介电层中且接合到第一金属凸块。本发明实施例的基板上允许存在的金属凸块的数目可达到最大化。此外，也可改善尺寸因子。

Description

半导体元件
技术领域
本发明涉及一种集成电路，且特别是涉及一种包括中介层(interposers)的三维集成电路(3DIC)与其制法。
背景技术
各种电子元件(例如晶体管(transistors)、二极管(diodes)、电阻器(resistors)、电容(capacitors)等等)的集积密度(integration density)已经持续快速的提升。对大多数元件而言，集积密度的提升来自于不断地降低特征结构的尺寸(feature size)，以允许更多的元件整合于既定面积之中。
这些整合在本质上属于二维(2D)的提升，其中集成元件所占据的体积实质上位于半导体晶片的表面上。虽然光刻技术的显著提升使2D集成电路的形成得到相当大的改进，然而对于2D空间可达到的密度仍有物理上的限制。其中之一的限制在于需要微小尺寸以构成这些元件。此外，当越多元件置于一芯片时，需要越复杂的设计。另外一项额外的限制在于，当元件数目增加时，元件间的内连线结构(interconnections)的数目与长度会显著的增加。当内连线结构数目与长度增加时，电路RC延迟(circuit RC delay)与功率消耗(power consumption)两者皆会增加。
为了解决上述的限制，因此衍生出三维(3D)集成电路(ICs)，其中裸片被堆叠，且通过使用导线接合(wire-bonding)、倒装芯片接合(flip-chip bonding)及/或硅穿孔(through-silicon vias，TSV)等技术将裸片接合在一起，用以将裸片连接到封装基板上。然而，现有的3D ICs具有高尺寸因子(high form factor)。
发明内容
为克服现有技术的缺陷，本发明提供一种半导体元件，包括：一中介层(interposer)，其中该中介层包括：一基板；至少一介电层，位于该基板之上；多个基板穿孔(through-substrate vias，TSVs)穿过该基板；一第一金属凸块，位于该介电层中且与所述多个基板穿孔电性耦合；以及一第二金属凸块，位于该介电层之上；以及一第一裸片，埋设于该介电层之中且接合到该第一金属凸块。
本发明也提供一种半导体元件，包括：一第一裸片；一中介层，其中该中介层包括：一基板；多个第一基板穿孔(through-substrate vias，TSVs)穿过该基板；多个第一重新布线层(redistribution lines，RDLs)，位于该基板之上且与所述多个基板穿孔电性耦合；一介电层，位于该基板的顶表面上，该第一裸片位于该介电层中，其中该介电层包括一部分直接位于该第一裸片之上，且该介电层包括一第二部分包围该第一裸片；以及多个导通孔(vias)延伸到该介电层中，其中所述多个导通孔包括一第一部分直接位于该第一裸片之上且与该第一裸片电性耦合，且所述多个导通孔包括不与该第一裸片对准的一第二部分，且第二部分与所述多个第一基板穿孔电性耦合，且其中所述多个导通孔的末端彼此等高；多个第一金属凸块位于该介电层之上且与所述多个导通孔电性耦合，其中所述多个第一金属凸块包括一部分与该第一裸片电性耦合；以及一第二裸片，位于所述多个第一金属凸块之上且与所述多个第一金属凸块电性耦合。
本发明另提供一种半导体元件，包括：一中介层，其中该中介层大体上不包括集成电路元件，且该中介层包括：一硅基板；多个第一基板穿孔(through-substrate vias，TSVs)，位于该基板中；多个第一金属凸块，位于该中介层的第一侧上，该第一金属凸块的一部分与所述多个第一基板穿孔电性耦合；多个第二金属凸块，位于相对于该第一侧的一第二侧上，该第二金属凸块的一部分与所述多个第一基板穿孔电性耦合；一第一内连线结构(interconnect structure)，位于该中介层第一侧上且包括：至少一介电层，位于该硅基板之上；以及重新布线层(redistribution lines)，位于该介电层中且使所述多个第一金属凸块与所述多个第一基板穿孔电性耦合；一第一裸片，埋设于所述多个介电层中且位于所述多个第一金属凸块底下，其中该第一裸片与所述多个第一金属凸块电性耦合；以及一第二裸片，位于所述多个第一金属凸块之上且与所述多个第一金属凸块电性耦合。
本发明实施例的基板上允许存在的金属凸块的数目可达到最大化。此外，也可改善尺寸因子。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1A～图1G为一系列剖面图，用以说明本发明一实施例制作三维集成电路(3DIC)的各个工艺阶段，其中裸片埋设于中介层一侧的介电层中。
图2A～图2C为一系列剖面图，用以说明本发明一较佳实施例制作三维集成电路(3DIC)的各个工艺阶段，其中形成金属凸块于中介层的相对侧之前，第一层裸片与对各自的模封化合物接合/涂布于中介层上。
图3A～图3C为一系列剖面图，用以说明本发明一较佳实施例制作三维集成电路(3DIC)的各个工艺阶段，其中形成焊料凸块于中介层相对侧上之后，第一层裸片(不具有模封化合物)接合至中介层。
图4～图6为一系列剖面图，用以说明本发明各种三维集成电路(3DIC)的实施例。
【主要附图标记说明】
10～基板
12、12A～重新布线层(RDLs)
14～有源元件
18～介电层
20、20A～基板穿孔(TSVs)
21～绝缘层
22～第二层裸片(tier-2die)
24～黏着层
26～接合焊盘(bonding pads)
28～介电层
30～导通孔(vias)
32～重新布线层(RDLs)
34～介电层
35～金属凸块
36～载板(carrier)
37～凸块底层金属(UBMs)
38～金属凸块
39～黏着剂
44～第一层裸片(dier-1die)
45～底部填充物(underfill)
46A、46B～凸块
50～电子元件
54～模封化合物
60～基板穿孔(TSVs)
100～中介层晶片
100’～中介层
具体实施方式
以下特举出本发明的实施例，并配合附图作详细说明。以下实施例的元件和设计是为了简化所公开的发明，并非用以限定本发明。
本发明提供一种新颖的三维集成电路(3DIC)与其制法。实施例中叙述各个工艺阶段。也讨论各种实施例的变化。在各种图示与示范实施例中，类似的元件用类似的附图标记表示。
请参见图1A，提供一基板10。在说明书中，基板10与形成于基板10的相对两侧的介电层与金属结构特征合称为中介层晶片100。基板10由一半导体材料所组成，例如硅、硅化锗(silicon germanium)、碳化硅(silicon carbide)、砷化镓(gallium arsenide)或其他常用的半导体材料。另外，基板10也可由介电材料所组成，例如氧化硅(silicon oxide)。中介层晶片100可包括，或可大体上不包括有源元件，例如晶体管。图1A显示有源元件14形成于基板10的表面上。另外，中介层晶片100可包括，或不包括无源元件，例如电容(capacitors)、电阻(resistors)、电感(inductors)及/或类似的元件。基板穿孔(through-substrate vias，TSVs)20形成于基板10中，并且形成绝缘层21以电性隔离基板穿孔(TSVs)20与基板10。
重新布线层(redistribution lines，RDLs)12形成于基板10之上，且与该基板穿孔(TSVs)20电性耦合。重新布线层(RDLs)12可包括用于传递(routing)电子信号(electrical signal)的金属线(metal lines)，与用于连接后续形成的导通孔(vias)所需的金属焊盘(metal pads)。在一实施例中，重新布线层(RDLs)12由铜所组成，话虽如此，也可由其他材料所组成，例如铝(aluminum)、银(silver)、钛(titanium)、钽(tantalum)、钨(tungsten)、镍(nickel)及/或上述的合金。在说明书中，请参见图1A，中介层晶片100面向上的一侧称为前侧(frontside)，面向下的一侧称为背侧(back side)。介电层18形成于重新布线层(RDLs)12之上，并且形成一平坦表面。形成介电层18的材料可包括氮化物、聚酰亚胺(polyimide)、有机材料、无机材料以及类似的材料。在形成介电层18之后，重新布线层(RDLs)12被覆盖。
接着，请参见图1B，裸片22通过，例如黏着层24，附着于介电层18之上，其中裸片22具有接合焊盘(或金属凸块)26的一侧背对于介电层18。虽然仅显示一个裸片，但是也可接合多个相同的裸片22到中介层晶片100上。裸片22可以是包含集成电路元件形成于其中的元件裸片，其中集成电路元件包括例如晶体管(transistors)、电容(capacitors)、电感(inductors)、电阻(resistors)(图中未显示)，或类似的元件。此外，裸片22可以是包含核心电路(core circuits)的一逻辑裸片(logic die)，或是一存储器裸片(memory die)。裸片22之后也可称为第二层裸片(tier-2die)。
请参见图1C，介电层28形成于介电层18与裸片22之上。基本上(essentially)，形成介电层28的材料可等于形成介电层18的材料或与介电层18的材料属于同一类型。介电层28之后将包括两部分，第一部分覆盖裸片22，而第二部分围绕裸片22。接着，请参见图1D，形成导通孔(vias)30、重新布线层(RDLs)32与介电层34。在形成上述结构的工艺的实施例中，首先(例如通过蚀刻)在介电层18与28中形成导通孔开口(vias opening)，其中利用位于重新布线层(RDLs)12中的金属焊盘与裸片22的接合焊盘26作为蚀刻停止层。接着将金属材料填充于导通孔开口中以形成导通孔30。接着，形成重新布线层(RDLs)32。在另一示范实施例中，导通孔30与重新布线层(RDLs)32可通过同一金属填充工艺而形成。介电层34形成于重新布线层(RDLs)32之上。接着在介电层34之中形成开口，其中重新布线层(RDLs)32暴露的部分作为接合焊盘(bond pads)。重新布线层(RDLs)32由铜所组成，话虽如此，也可由其他材料所组成，例如铝(aluminum)、银(silver)、钨(tungsten)、钛(titanium)、钽(tantalum)及/或上述的合金。此外，重新布线层(RDLs)32可具有复合结构，复合结构包括一铜层与形成于铜层之上的金属抛光层(metalfinish)，其中金属抛光层可包括镍层(nickel layer)、钯层(palladium layer)、金层(gold layer)或上述的组合。在本文之后的叙述中，将介电层18与28、重新布线层(RDLs)12与32合称为内连线结构(interconnect structure)。
请参见图1E，一载板(carrier)36，其可以是玻璃晶片，通过金属凸块35与黏着层39(其可以是紫外光胶，或由其他已知的黏着材料所组成)接合到中介层晶片100的前侧。接着，请参见图1F，从中介层晶片100的背侧进行晶片背侧研磨，借以薄化基板10，直到基板穿孔(TSVs)20暴露在外为止。为了降低基板10的背表面的高度，还可进行一蚀刻工艺，使得基板穿孔(TSVs)20延伸突出于基板10的剩余部分。
请再次参见图1F，凸块底层金属(under-metal-metallurgies，UBMs)37与背侧金属凸块38形成于中介层晶片100的背侧，且上述两者与基板穿孔20电性耦合。背侧金属凸块38可以是焊料凸块(solder bumps)，例如共晶焊料凸块(eutectic solder bumps)、铜凸块、或是由金、银、镍、钨、铝及/或上述合金形成的其他金属凸块。形成的工艺可包括电镀，其中电镀可包括电极电镀(electro plating)或无电极电镀(electroless plating)。
虽然图中显示背侧金属凸块38直接形成于基板穿孔(TSVs)20之上，然而也可形成其他的背侧内连线结构(图中未显示)于背侧金属凸块38与基板穿孔(TSVs)20之间，并且使此背侧内连线结构与背侧金属凸块38与基板穿孔(TSVs)20电性耦合。背侧内连线结构可包括一或多层的重新布线层，各自形成于一介电层中。
请参见图1G，移除载板36，且将另一载板(图中未显示)接合于金属凸块38上。接着，凸块46(包括凸块46A与46B)可接合至中介层晶片100的前侧。凸块46可以是焊料凸块，例如，凸块46可以是铜凸块。接着，使用面对面接合方式(face-to-face bonding)并通过凸块46将第一层裸片(Tie-1 1die)44接合至中介层晶片100。虽然图中仅显示一个裸片44，然而也可将多个裸片44接合至中介层晶片100上。第一层裸片(Tier-1 die)44与第二层裸片(Tier-2 die)22可以是不同类型的裸片。举例而言，第一层裸片(Tier-1 die)44可以是一逻辑裸片，而第二层裸片(Tier-2 die)22可以是一存储器裸片。可观察到的是，凸块46A用于使第一层裸片(Tier-1 die)44与中介层晶片100电性耦合，而凸块46B用于使第一层裸片(Tier-1 die)44与第二层裸片(Tier-2 die)22电性耦合。因此，裸片22与44可直接互相连接，而不需要通过重新布线层(RDLs)、基板穿孔(TSVs)及/或类似的结构传递信号。
在接合第一层裸片(Tier-1 die)44之后，将底部填充物(underfill)45填充到介于第一层裸片(Tier-1 die)44与中介层晶片100之间的缝隙(gap)。可对中介层晶片100进行切割工艺(singulation)，切割中介层晶片100，使得裸片彼此分离，每一个裸片包括一个裸片22与中介层100’(如图1G)。在另一实施例中，在将第一层裸片(Tier-1 die)44接合至中介层晶片100之前，即先对中介层晶片100进行切割工艺。
接着，请再次参见图1G，包含中介层100’与裸片22、24的三维集成电路(3DIC)通过凸块38接合至电子元件50。电子元件50可包括一封装基板、一印刷电路板(printed circuit board，PCB)或类似的基板。
图2A到图2C显示另一实施例。除非特别注明，否则与图1A-图1G实施例相同的元件皆使用相同的附图标记表示。此实施例的初始步骤实质上等于图1A～图1D。虽然也可形成某些结构特征，例如介电层34与凸块底层金属(UBMs)37，但为了简化说明，这些结构特征并未显示于后续的实施例中。接着，请参见图2A，形成凸块46，并将第一层裸片(Tier-1 die)44接合至中介层晶片100。虽然仅显示一个第一层裸片(Tier-1 die)44，然而也可将多个第一层裸片(Tier-1 die)44接合至中介层晶片100上。同样地，凸块46A用于使第一层裸片(Tier-1 die)44与基板穿孔(TSVs)20电性耦合，而凸块46B用于使第一层裸片(Tier-1 die 44)与第二层裸片(Tier-2 die)22电性耦合。将底部填充物(underfill)45填入第一层裸片(Tier-1 die)44与中介层晶片100之间的缝隙(gap)。接着，形成模封化合物(molding compound)54，以覆盖第一层裸片(Tier-1die)44与中介层晶片100。
图2B显示凸块38的形成，此时模封化合物54作为一载板，并不需使用额外的载板承载模封化合物54。接着，进行一切割工艺以分割中介层晶片100(以及接合于其上的裸片22与44)。如图2C所示，此三维集成电路(3DIC)接合到电子元件上。
图3A-图3C也显示另一实施例。同样地，与图1A-图1G的实施例中相同的元件使用相同的附图标记表示。此实施例的初始步骤实质上等于图1A～图1D。接着，请参见图3A，第一层裸片44接合到中介层晶片100。同样地，凸块46A用于使第一层裸片(Tier-1 die)44与基板穿孔(TSVs)20电性耦合，而凸块46B用于使第一层裸片(Tier-1 die)44与第二层裸片(Tier-2 die)22电性耦合。接着将底部填充物(underfill)45填入第一层裸片(Tier-1 die)44与中介层晶片100之间的缝隙(gap)。比起显示于图2A中的实施例，可观察到并未有任何的模封化合物形成于此实施例中。接着，载板36接合到第一层裸片44。图3B到图3C显示形成凸块38，以及将最终的三维集成电路(resulting3DIC)接合到电子元件50上。同样地，在进行图3C步骤之前，可进行切割工艺，且可同时对附着于中介层晶片100上的载板36进行切割，或之后载板36可被切割胶带(dicing tape)(图中未显示)所取代。
图4到图6显示各种实施例。请参见图4，由于第二层裸片不够薄，无法填充于介电层18与28中，因此可在形成基板穿孔(TSVs)20之前，在基板10中形成凹口(recess)(凹口被裸片22与介电层18、28所填满)。裸片22可部分地或全部地位于基板10的凹口中。三维集成电路(3DIC)之后续形成工艺大体上与图1A到图3C的步骤相同。可观察到在图4中，一些基板穿孔(TSVs)(标为基板穿孔20A)直接位于裸片22底下，重新布线层12A与基板穿孔(TSVs)20电性耦合。因此，位于裸片22底下的空间可用于传递电子信号。另外，如图5所示，没有任何基板穿孔(TSV)或重新布线层直接形成于第二层裸片22底下。
图6显示另一实施例，其中基板穿孔(TSVs)60形成于第二层裸片22之中，且使第一层裸片44与金属凸块38电性耦合。举例而言，基板穿孔(TSVs)60可使第一层裸片44与金属凸块64电性耦合，金属凸块64与直接位于第二层裸片22底下的基板穿孔(TSVs)20A电性耦合。金属凸块64可以是焊料凸块、铜凸块或类似的结构。由于建立了一条使裸片11与金属凸块38电性耦合的较短电子路径，因此最终的三维集成电路(resulting 3DIC)的电子性能得以获得改善。须注意的是，在图6中，也可形成类似于图4与图5的凹口，其中裸片22可至少部分地或全部地位于凹口中。
在这些实施例中，第一层裸片44与第二层裸片22接合到中介层的同一侧，因此，第一层裸片44与第二层裸片22可通过直接接合而直接沟通(talkdirectly)。另一方面而言，裸片44与22位于同一侧，中介层的另外一侧并不具有任何裸片位于其上，因此，基板上允许存在的金属凸块的数目得以达到最大化(maximized)。此外，也可改善尺寸因子(form factor)。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种半导体元件，包括：
一中介层，其中该中介层包括：
一基板；
至少一介电层，位于该基板之上；
一导通孔，位于该介电层中；
多个基板穿孔穿过该基板；
一第一金属凸块，位于该介电层中且与所述多个基板穿孔电性耦合；以及
一第二金属凸块，位于该介电层之上，且通过该导通孔与所述多个基板穿孔电性耦合；以及
一第一裸片，埋设于该介电层之中且接合到该第一金属凸块。
2.根据权利要求1所述的半导体元件，其中该中介层包括一硅基板或一介电基板。
3.根据权利要求1所述的半导体元件，，其中该导通孔从高于该第一裸片的顶表面延伸到低于该第一裸片的底表面。
4.一种半导体元件，包括：
一第一裸片；
一中介层，其中该中介层包括：
一基板；
多个第一基板穿孔穿过该基板；
多个第一重新布线层，位于该基板之上且与所述多个第一基板穿孔电性耦合；
一介电层，位于该基板的顶表面上，该第一裸片位于该介电层中，其中该介电层包括一部分直接位于该第一裸片之上，且该介电层包括一第二部分包围该第一裸片；以及
多个导通孔延伸到该介电层中，其中所述多个导通孔包括一第一部分直接位于该第一裸片之上且与该第一裸片电性耦合，且所述多个导通孔包括不与该第一裸片对准的一第二部分，且第二部分与所述多个第一基板穿孔电性耦合，且其中所述多个导通孔的末端彼此等高；
多个第一金属凸块位于该介电层之上且与所述多个导通孔电性耦合，其中所述多个第一金属凸块包括一部分与该第一裸片电性耦合；以及
一第二裸片，位于所述多个第一金属凸块之上且与所述多个第一金属凸块电性耦合。
5.根据权利要求4所述的半导体元件，其中该中介层的基板包括一凹口，且其中该第一裸片的一部分位于该凹口中。
6.根据权利要求4所述的半导体元件，还包括一模封化合物位于该第二裸片之上且包围该第二裸片。
7.一种半导体元件，包括：
一中介层，其中该中介层大体上不包括集成电路元件，且该中介层包括：
一硅基板；
多个第一基板穿孔，位于该基板中；
多个第一金属凸块，位于该中介层的第一侧上，该第一金属凸块的一部分与所述多个第一基板穿孔电性耦合；
多个第二金属凸块，位于相对于该第一侧的一第二侧上，该第二金属凸块的一部分与所述多个第一基板穿孔电性耦合；以及
一第一内连线结构，位于该中介层第一侧上且包括：
至少一介电层，位于该硅基板之上；以及
重新布线层，位于该介电层中且使所述多个第一金属凸块与所述多个第一基板穿孔电性耦合；
一第一裸片，埋设于所述多个介电层中且位于所述多个第一金属凸块底下，其中该第一裸片与所述多个第一金属凸块电性耦合；以及
一第二裸片，位于所述多个第一金属凸块之上且与所述多个第一金属凸块电性耦合。
8.根据权利要求7所述的半导体元件，其中一凹口从该硅基板的顶表面延伸到硅基板中，其中该介电层延伸到该凹口中，且该第一裸片的一部分位于该凹口中。
9.根据权利要求7所述的半导体元件，其中该第一裸片包括所述多个第二基板穿孔位于其中，且该第一裸片使该第二裸片与所述多个第二金属凸块电性耦合。
10.根据权利要求7所述的半导体元件，还包括一模封化合物位于该第二裸片之上且包围该第二裸片。
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US20200035554A1 (en) 2020-01-30

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