KR101299875B1 - 임베디드 3ｄ 인터포저 구조물 - Google Patents

임베디드 3ｄ 인터포저 구조물 Download PDF

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KR101299875B1
KR101299875B1 KR1020100107140A KR20100107140A KR101299875B1 KR 101299875 B1 KR101299875 B1 KR 101299875B1 KR 1020100107140 A KR1020100107140 A KR 1020100107140A KR 20100107140 A KR20100107140 A KR 20100107140A KR 101299875 B1 KR101299875 B1 KR 101299875B1
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South Korea
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die
dielectric layer
metal bumps
substrate
interposer
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KR1020100107140A
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English (en)
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KR20120000483A (ko
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잉칭 시
징청 린
웬-치 치우
신푸 젱
첸-후아 유
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract

소자는, 기판, 기판상의 적어도 하나의 유전체 층(dielectric layer)을 포함하는 인터포저를 포함한다. 다수의 TSVs는 기판을 통과한다. 제1 금속 범프(first metal bump)는 적어도 하나의 유전체 층에 있으며, 다수의 TSVs에 전기적으로 연결된다. 제2 금속 범프(second metal bump)는 적어도 하나의 유전체 층 상에 있다. 다이는 적어도 하나의 유전체 층에 임베디드되며, 제1 금속 범프에 부착된다.

Description

임베디드 3Ｄ 인터포저 구조물 {Embedded 3D Interposer Structure}
본 발명은 집적 회로에 일반적으로 관련되는 것으로, 더욱 상세하게는 인터포저(interposer)를 포함하는 3 차원 집적 회로(three dimensional integrated circuit : 3DIC) 및 이를 형성하는 방법에 관한 것이다.
다양한 전자 부품(electronic component)(예를 들어, 트랜지스터, 다이오드, 저항, 커패시터 등)의 집적도(integration density)는 급격히 증가하고 있다. 대부분, 집적도의 향상은 최소 피쳐 사이즈(minimum feature size)의 반복된 감소에서 야기되며, 이는 더 많은 부품이 주어진 칩 면적에서 집적화될 수 있도록 허락한다.
집적 부품에 의해 차지되는 부피는 반도체 웨이퍼(wafer)의 표면에서 필수적이라는 점에서, 집적도 향상은 본질상 필수적으로 2 차원(two-dimensional :2D) 적이다. 비록 리소그래피(lithography)에서 드라마틱한 향상은 2D 집적 회로 형성에서 상당한 향상을 야기하지만, 2 차원에서 달성될 수 있는 밀도는 물리적인 제한이 있다. 이러한 제한 중 하나는 이러한 부품들을 제조하기 위해 요구되는 최소 크기이다. 또한, 많은 소자들이 하나의 칩에 더해질 때, 더욱 복잡한 설계가 요구된다. 추가적인 제한은 소자들의 수가 증가함에 따라 소자들 사이의 상호 접속(interconnection)의 수와 길이가 상당히 증가한다는 점에서 비롯된다. 상호 접속의 수와 길이가 증가하면, 회로 RC 지연(delay)과 전력 소모는 증가한다.
이에 따라, 3 차원 집적 회로(3DICs)가 형성되었으며, 여기서, 다이(die)는 다이들을 함께 연결하고 다이들을 패키지 기판에 연결하기 위해 사용되는 와이어-본딩(wire-bonding), 플립-칩 본딩(flip-chip bonding) 및/또는 TSV(through silicon vias)을 이용해 스택(stack)된다. 하지만, 종래 3DICs은 높은 폼 팩터(form factor)를 가진다.
본 발명의 일 실시 예에 따르면, 소자는 기판, 기판상의 적어도 하나의 유전체 층(dielectric layer)을 포함하는 인터포저를 포함한다. 복수의 TSVs는 기판을 통과한다. 제1 금속 범프(first metal bump)는 적어도 하나의 유전체 층에 있으며, 복수의 TSVs에 전기적으로 연결된다. 제2 금속 범프(second metal bump)는 적어도 하나의 유전체 층 상에 있다. 다이는 적어도 하나의 유전체 층에 임베디드되며, 제1 금속 범프에 부착된다.
다른 실시 예들이 또한 개시된다.
본 실시 예들과 그들의 이점에 대한 완전한 이해를 위해, 참조가 첨부된 도면과 함께 이하의 명세서에서 기술된다.
도 1a 내지 도 1g는 본 발명의 다양한 실시 예에 따른 3 차원 집적 회로(3DIC)의 제조에서 중간 단계의 단면도이며, 다이는 인터포저의 한 쪽의 유전체 층에 임베디드된다.
도 2a 내지 도 2c는 본 발명의 다양한 실시 예에 따른 3DIC의 제조에서 중간 단계의 단면도이며, 여기서, 티어-1 다이(tier-1 die) 및 각각의 몰딩 컴파운드(molding compound)는 솔더 범프(solder bump)가 인터포저의 반대 쪽에 형성되기 전에 인터포저에 부착/적용된다.
도 3a 내지 도 3c는 본 발명의 다양한 실시 예에 따른 3DICs의 제조에서 중간 단계의 단면도이며, 티어-1 다이(몰딩 컴파운드가 적용되지 않은)는 솔더 범프가 인터포저의 반대 쪽에 형성된 후에 인터포저에 부착된다. 그리고,
도 4 내지 도 6은 본 발명의 다양한 실시 예에 따른 3DICs의 단면도이다.
본 개시물의 실시 예의 생성과 사용은 이하에서 자세히 기술된다. 하지만, 실시 예들은 특정 맥락의 다양성에서 예시될 수 있는 적용 가능한 발명적 개념을 제공한다. 논의되는 특정 실시 예들은 단지 예시에 불과하며, 본 개시물의 범위를 제한하는 것은 아니다.
새로운 3차원 집적 회로(3DIC) 및 그 형성 방법이 제공된다. 일 실시 예를 제조하는 중간 단계가 도시된다. 다양한 실시 예들이 논의된다. 다양한 관점과 도시된 실시 예들을 통해, 참조 부호는 요소를 표기하기 위해 사용된다.
도 1a에서, 기판(10)이 마련된다. 본 명세서를 통해, 기판(10), 해당 유전체 층 및 기판(10)의 반대쪽에 형성된 금속 형상(metal feature)은 인터포저 웨이퍼(100)로서 언급된다. 기판(10)은 실리콘(silicon), 실리콘 게르마늄(silicon germanium), 실리콘 카바이드(silicon carbide), 갈륨 비소(gallium arsenide)와 같은 반도체 물질 또는 반도체 물질로 보통 사용되는 다른 물질로 형성될 수 있다. 대체적으로, 기판(10)은 실리콘 산화물(silicon oxide)과 같은 유전체 물질로 형성될 수 있다. 인터포저 웨이퍼(100)는 트랜지스터와 같은 능동 소자(active device)를 포함하거나, 이로부터 실질적으로 자유로울 수 있다. 도 1a는 기판(10)의 표면에 형성될 수 있는 능동 소자(14)를 나타낸다. 게다가, 인터포저 웨이퍼(100)는 커패시터, 저항, 인덕터 및/또는 이와 유사한 것과 같은 수동 소자(passive device)를 포함하거나, 이로부터 실질적으로 자유로울 수 있다. TSVs(through-substrate vias)(20)는 기판(10)에 형성되며, 절연층(insulation layer)(21)은 기판(10)으로부터 TSVs(20)를 전기적으로 절연시키도록 형성될 수 있다.
RDLs(redistribution lines)(12)은 기판(10)에 형성되며, TSVs(20)에 전기적으로 연결된다. RDLs(12)는 전기적 신호를 라우팅(routing)하기 위한 금속 선(metal line)과 연속적으로 형성된 비아(vias)를 랜딩(landing)하기 위한 금속 패드(metal pad)를 포함할 수 있다. 일 실시 예에서, RDLs(12)는 비록 알루미늄(aluminum), 은(silver), 티타늄(titanium), 탄탈륨(tantalum), 텅스텐(tungsten), 니켈(nickel) 및/또는 그들의 합금으로 형성될 수도 있지만, 구리(copper)로 형성될 수 있다. 기술을 하는 동안, 도 1a에서 바로 놓인 인터포저 웨이퍼(100)의 한 쪽은 전면(front side)으로 언급되며, 아래로 놓인 쪽은 후면(backside)으로 언급된다. 유전체 층(18)은 RDLs(12) 상에 형성되어, 평편한 상부 표면을 형성한다. 유전체 층(18)을 형성하기 위한 물질은 질화물(nitride), 폴리이미드(polymide), 유기물(organic material), 무기물(inorganic material) 및 이와 유사한 것을 포함할 수 있다. 유전체 층(18)의 형성 후에, RDLs(12)가 커버(cover)된다.
다음으로, 도 1b에 도시된 것처럼, 예를 들어, 다이(22)는 유전체 층(18)으로부터 이격되어 마주보는 본드 패드(또는 금속 범프)(26)를 가지며, 예를 들면, 접착제(adhesive)(24)를 통해, 유전체 층(18)에 부착된다. 비록 단지 하나의 다이(22)가 도시되었지만, 복수의 동일한 다이(22)가 인터포저 웨이퍼(100)에 부착될 수 있다. 다이(22)는 트랜지스터, 커패시터, 인덕터, 저항(미도시) 및 이와 유사한 것과 같은 집적 회로 소자들을 포함하는 소자 다이일 수 있다. 게다가, 다이(22)는 코어 회로(core circuit)를 포함하는 로직 다이(logic die) 또는 메모리 다이(memory die)일 수 있다. 다이(22)는 이하에서 티어-2(tier-2)로 언급될 수 있다.
도 1c에서, 유전체 층(28)은 유전체 층(18)과 다이(22) 상에 형성된다. 유전체 층(28)을 형성하기 위한 물질은 유전체 층(18)과 기본적으로 동일하거나 동일한 그룹에서 선택되는 것일 수 있다. 이에 따라, 유전체 층(28)은 다이(22)를 커버링하는 제1 부분과, 다이(22)를 둘러싸는 제2 부분을 포함할 수 있다. 다음으로, 도 1d에 도시된 바와 같이, 비아(vias)(30), RDLs(32) 및 유전체 층(34)이 형성된다. 예시적인 형성 공정에서, 비아 개구(via opening)(비아(30)에 의해 채워짐)는 유전체 층(18, 28)에서 RDLs(12)에서 금속 패드와 에칭 정지 층(etching stop layer)으로서 동작하는 다이(22)의 본드 패드(26)와 함께, 예를 들면 에칭(etching)에 의해, 먼저 형성된다. 이어서, 비아 개구는 비아(30)를 형성하기 위해 금속 물질에 의해 채워진다. 이어서, RDLs(32)가 형성된다. 대체적인 실시 예들에서, 비아(30) 및 RDLs(32)는 동일한 금속-충전 공정(metal-filling process)에서 형성될 수 있다. 유전체 층(34)은 RDLs(32) 상에 형성된다. 이어서, 개구가 유전체 층(34)에 형성되며, 여기서 RDLs(32)의 노출된 부분은 본드 패드로서 동작한다. RDls(32)는 비록 알루미늄, 은, 텅스텐, 티타늄, 탄탈륨 및/또는 이와 유사한 것들이 사용될 수 있지만, 구리에 의해 형성될 수 있다. 게다가, RDLs(32)는 구리 층 및 구리 층에 메탈 피니쉬(metal finish)를 포함하는 복합 구조물(composite structure)을 가질 수 있다. 여기서, 메탈 피니쉬는 니켈 층(nickel layer), 팔라듐 층(palladium layer), 금 층(gold layer) 또는 그들의 조합을 포함할 수 있다. 유전체 층(18, 28) 및 RDLs(12, 32) 이하에서 상호 접속 구조물(interconnect structure)로 언급될 수 있다.
도 1e에서, 글래스 웨이퍼(glass wafer)일 수 있는 캐리어(36)는 자외선 글루(ultra-violet(UV) glue) 또는 알려진 다른 접착 물질에 의해 형성된 접착제(adhesive)(39)를 통해, 인터포저 웨이퍼(100)의 전면에 접착된다. 다음으로, 도 1f에 도시된 바와 같이, 웨이퍼 후면 연마(grinding)는 TSVs(20)가 노출될 때까지, 후면으로부터 박형 기판(thin substrate)(10)으로 수행된다. 에칭은 TSVs(20)이 기판의 남은 부분의 후면에서 돌출되도록, 기판(10)의 후면을 더 감소시키기 위해 수행될 수 있다.
또한, 도 1f에 도시된 것과 같이, UBMs(under-metal-metallurgies)(37)와 후면 금속 범프(38)는 인터포저 웨이퍼(100)의 후면에 형성되며, TSVs(20)에 전기적으로 연결된다. 후면 금속 범프(38)는 공융 솔더 범프(eutectic solder bump), 구리 범프(copper solder) 또는 금, 은, 니켈, 텅스텐, 알루미늄 및/또는 그들의 합금으로 형성된 다른 금속 범프와 같은 솔더 범프일 수 있다. 형성 공정은 전기 도금(electro plating) 또는 무전해 도금(electroless plating)을 포함하는 도금을 수 있다.
비록 후면 금속 범프(38)가 TSVs(20)에 직접 형성되는 것으로 도시되었지만, 추가적인 후면 상호 접속 구조물(미도시)는 후면 금속 범프(38)과 TSVs(20) 사이에서 전기적으로 연결되어 형성될 수 있음이 언급된다. 후면 상호 접속 구조물은 하나의 유전체 층에 각각 형성된, 하나 또는 그 이상의 RDLs 층을 포함할 수 있다.
도 1g에서, 캐리어(36)는 부착(bonding)되지 않으며, 다른 캐리어(미도시)가 금속 범프(38)에 부착될 수 있다. 이에 따라, 범프(46)(범프 46a 및 46b를 포함함)는 인터포저 웨이퍼(100)의 전면에 부착될 수 있다. 범프(46)는 솔더 범프일 수 있으며, 예를 들어, 구리 범프일 수도 있다. 이에 따라, 티어-1 다이(44)는 페이스-투-페이스 본딩(face-to-face bonding)을 사용하는 범프(46)를 통해 인터포저 웨이퍼(100)에 부착된다. 비록 단지 하나의 다이(44)만을 도시하였지만, 인터포저 웨이퍼(100)에 부착된 복수의 다이(44)를 구비할 수 있다. 티어-1 다이(44) 및 티어-2 다이(22)는 다른 종류의 다이일 수 있다. 예를 들어, 티어-1 다이(44)는 로직 다이일 수 있는 반면, 티어-2 다이(22)는 메모리 다이일 수 있다. 범프(46a)는 인터포저 웨이퍼(100)에 티어-1 다이(44)를 전기적으로 연결하도록 사용될 수 있지만, 반면, 범프(46b)는 티어-2 다이(22)에 티어-1 다이(44)를 연결하도록 사용될 수 있다. 이에 따라, 다이(22, 44)는 서로 직접적으로 커뮤니케이팅할 수 있으며, 반면 신호는 RDLs, TSVs 및/또는 이와 유사한 것을 통해 연결될 필요가 없다.
티어-1 다이(44)의 본딩 후에, 언더필(underfill)(45)은 티어-1 다이(44)와 인터포저 웨이퍼(100) 사이의 갭(gap)에 채워진다. 싱귤레이션(singulation)은 인터포저 웨이퍼(100)에서 수행될 수 있으며, 인터포저 웨이퍼(100)는 다이들이 서로 분리되고, 각 다이들이 다이(22)와 인터포저(100')(도 1g) 중 하나를 포함하도록 이격되어 형성된다. 다른 실시 예들에서, 싱귤레이션(singulation)은 타이-1 다이(44)가 부착되기 전에, 인터포저 웨이퍼(100)에서 수행된다.
다음으로, 도 1g에서, 인터포저(100') 및 다이(22, 44)를 포함하는 3DIC는 범프(38)를 통해 전기적인 요소(50)에 부착된다. 전기적인 요소(50)는 패키지 기판, 인쇄 기판 보드(printed circuit board : PCB) 또는 이와 유사한 것일 수 있다.
도 2a 내지 도 2c는 다른 실시 예를 나타낸다. 특정한 다른 언급이 없다면, 이러한 실시 예들에서 참조 번호는 도 1a 내지 도 1g에 도시된 실시 예들에서 요소들과 같은 요소를 나타낸다. 본 실시 예에서 초기 단계는 도 1a 내지 도 1d에서 도시된 바와 기본적으로 동일하다. 명료함을 위해, 유전체 층(34) 및 UBMs(37)와 같은 일부 특징들은 비록 형성될 수 있지만, 이후 논의된 실시 예들에서 도시되지 않는다. 다음으로, 도 2a에 도시된 바와 같이, 범프(46)는 형성되고, 티어-1 다이(44)는 인터포저 웨이퍼(100)에 부착된다. 비록 단지 하나의 티어-1 다이(44)가 도시되지만, 복수의 동일한 티어-1 다이(44)가 인터포저 웨이퍼(100)에 부착될 수 있다. 또한, 범프(46A)는 TSVs(20)에 티어-1 다이(44)를 전기적으로 연결하기 위해 사용될 수 있으며, 반면, 범프(46B)는 티어-2 다이(22)에 티어-1 다이(44)를 전기적으로 연결하기 위해 사용될 수 있다. 언더필(45)는 티어-1 다이(44)와 인터포저 웨이퍼(100) 사이의 갭에 채워질 수 있다. 이후, 몰딩 컴파운드(molding compound)(54)는 티어-1 다이(44) 및 인터포저 웨이퍼(100)를 커버하기 위해 형성된다.
도 2b는 사용되거나 몰딩 컴파운드(54)에 사용되거나 부착되는 추가적인 캐리어 없이, 몰딩 컴파운드(54)가 캐리어로서 사용되는 동안 범프(38)의 형성을 도시한다. 다음으로, 싱귤레이션은 인터포터 웨이퍼(100)(및 거기에 부착된 다이(22, 44))를 다이로 분리하기 위해 수행된다. 이후, 도 2c에 도시된 바와 같이, 3DIC는 전기적인 요소(50)에 부착된다.
도 3a 내지 도 3c는 또 다른 실시 예를 나타낸다. 또한, 이러한 실시 예들에서 참조 번호는 도 1a 내지 도 1g에서 도시된 실시 예들에서처럼 같은 요소를 나타낸다. 본 실시 예의 초기 단계는 도 1a 내지 도 1d에 도시된 것과 기본적으로 동일하다. 다음으로, 도 3a에 도시된 바와 같이, 티어-1 다이(44)는 인터포저 웨이퍼(100)에 부착된다. 유사하게, 범프(46A)는 TSVs(20)에 티어-1 다이(44)를 전기적으로 연결하기 위해 사용될 수 있고, 반면, 범프(46B)는 티어-2 다이(22)에 티어-1 다이(44)를 전기적으로 연결하기 위해 사용될 수 있다. 이에 따라, 언더필(45)은 티어-1 다이(44)와 인터포저 웨이퍼(100) 사이의 갭에 채워질 수 있다. 도 2a에 도시된 실시 예와 본 실시 예를 비교하면, 몰딩 컴파운드는 본 실시 예에서 형성되지 않는다. 다음으로, 캐리어(36)는 티어-1 다이(44)에 부착된다. 도 3b 및 3c는 범프(38)의 형성과 전기적인 요소(50) 상에 3DIC 결과의 본딩을 도시한다. 또한, 싱귤레이션은 도 3c에 도시된 단계가 수행되기 이전에 수행될 수 있으며, 싱귤레이션은 그에 부착된 캐리어(36) 또는 캐리어(36)가 다이싱 테이프(dicing tape)(미도시)로 대체된 후, 수행될 수 있다.
도 4 내지 도 6은 다양한 실시 예들을 도시한다. 도 4에서, 티어-2 다이(22)가 유전체 층(18, 28)에 맞기에 충분히 얇지 않은 본 실시 예에서, 리세스(recess)(다이(22)와 유전체 층(18, 28)에 의해 채워짐)는 TSVs(20)의 형성 전에 기판(10)에서 형성될 수 있다. 다이(22)는 기판(10)의 리세스에 부분적으로 또는 전체적으로 위치한다. 3DIC의 남은 형성 공정은 도 1a 내지 3c에 도시된 것과 기본적으로 동일할 수 있다. 도 4에서, 일부 TSVs(TSVs(20a)로 표기됨)는 다이(22) 아래 직접적으로 위치하며, RDLs(12a)는 TSVs(20)에 전기적으로 연결된다. 이에 따라, 다이(22) 바로 아래 공간은 전기적인 신호의 전달하기 위해 사용될 수 있다. 다른 한편, 도 5에 도시된 바와 같이, 어떠한 TSV 및 RDL도 티어-2 다이(22) 바로 아래 형성되지 않는다.
도 6은 TSVs(60)가 티어-2 다이(22)에 형성되며, 금속 범프(38)에 티어-1 다이(44)를 전기적으로 연결하는, 또 다른 실시 예를 도시한다. 예를 들어, TSVs(60)는 티어-2 다이(22)의 바로 아래 있는 TSVs(20a)에 전기적으로 연결되는 금속 범프(64)에 티어-1 다이(22)를 전기적으로 연결할 수 있다. 금속 범프(64)는 솔더 범프, 구리 범프 또는 이와 유사한 것일 수 있다. 이에 따라, 짧은 전기적 패스(short electrical path)는 범프(38)에 다이(22)를 전기적으로 연결하도록 형성되며, 3DIC의 전기적 동작은 향상된다. 도 6에 도시된 실시 예에서, 도 4 및 5에 도시된 리세스와 유사한 리세스(미도시)는 리세스에서 적어도 부분적으로 및 가능한 전체적으로 다이(22)를 구비하여 형성될 수 있다.
실시 예들에서, 티어-1 다이(44) 및 티어-2 다이(22)는 인터포저의 동일한 쪽에 부착될 수 있어, 티어-1 다이(44)와 티어 -2 다이(22)는 그들의 직접적인 본딩을 통해 직접적으로 토크(talk)할 수 있다. 반면에, 동일한 쪽의 양 다이(44, 22)를 가지며, 인터포저의 다른 쪽은 부착된 어떠한 다이를 가지지 않으며, 허용된 금속 범프의 수는 최대가 된다. 게다가, 폼 팩터는 향상된다.
비록 본 실시 예들과 그들의 이점이 자세히 기술되었지만, 첨부된 청구항에 의해 정의된 것과 같은 본 발명의 사상과 범위로부터 벗어남이 없이 다양한 변화, 교체 및 변경이 생성될 수 있음이 이해되어 져야한다. 게다가, 본 명세서의 사상은본 명세서에 기술된 공정, 기계, 제조 및 물질의 조합, 수단 방법 및 단계의 특정 실시 예에 제한되는 것은 아니다. 당해 기술 분야의 숙련된 자들 중 하나는 기술, 공정, 기계, 제조 및 물질의 조합, 수단 방법 또는 단계, 혼재 존재하거나 개발될 수 있는 것들로부터 여기에 기술된 해당 실시 예들이 본 개시물에 따라 사용될 수 있는 것과 같이 실질적으로 동일한 기능을 수행하거나 실질적으로 동일한 결과를 달성하는 것을 인정한다. 이에 따라, 첨부된 청구항은 공정, 기계, 제조, 물질의 조합, 수단, 방법 또는 단계와 같은 그들의 범위 내에서 포함되도록 의도된다. 게다가, 각각의 청구항은 별도의 실시 예, 다양한 청구항의 조합을 구성하며, 실시 예들은 본 개시물의 범위 내이다.

Claims (10)

  1. 기판;
    상기 기판 상의 적어도 하나의 유전체 층;
    상기 기판을 관통하는 복수의 TSV(through-substrate via)들;
    상기 복수의 TSV들에 전기적으로 연결되고, 상기 적어도 하나의 유전체 층 내에 있는 제1 금속 범프; 및
    상기 적어도 하나의 유전체 층 상의 제2 금속 범프
    를 포함하는 인터포저(interposer); 및
    상기 제1 금속 범프에 부착되며(bonded) 상기 적어도 하나의 유전체 층 내에 임베디드(embedded)된 제1 다이
    를 포함하는 소자.
  2. 제1항에 있어서,
    상기 제2 금속 범프에 부착된 제2 다이를 더 포함하는 소자.
  3. 제2항에 있어서,
    상기 제1 다이는 그 내부에 TSV를 더 포함하고,
    상기 제1 다이 내부의 상기 TSV는 상기 인터포저의 상기 기판 내의 상기 복수의 TSV들 중 하나에 전기적으로 연결되는 것인 소자.
  4. 제1항에 있어서,
    상기 복수의 TSV들 중 하나에 상기 제2 금속 범프를 전기적으로 연결하는, 상기 적어도 하나의 유전체 층 내의 비아를 더 포함하고,
    상기 비아는 상기 제1 다이의 상부 표면보다 높은 레벨로부터 상기 제1 다이의 하부 표면보다 낮은 레벨로 연장하는 것인 소자.
  5. 제1항에 있어서,
    상기 기판은 리세스(recess)를 포함하고,
    상기 제1 다이의 적어도 일부분은 상기 리세스 내에 위치하는 것인 소자.
  6. 제1 다이;
    인터포저로서, 상기 인터포저는,
    기판;
    상기 기판을 관통하는 복수의 제1 TSV(through-substrate via)들;
    상기 복수의 제1 TSV들에 전기적으로 연결되는, 상기 기판 상의 복수의 제1 RDL(redistribution line)들;
    상기 기판의 상부 표면 상의 유전체 층으로서, 상기 제1 다이는 상기 유전체층 내에 위치하고, 상기 유전체 층은, 상기 제1 다이 바로 위에 배치된 부분 및 상기 제1 다이를 둘러싸는 제2 부분을 포함하는 것인, 상기 유전체 층; 및
    상기 유전체 층 내로 연장하는 복수의 비아들로서, 상기 복수의 비아들은, 상기 제1 다이에 전기적으로 연결되며 상기 제1 다이 바로 위에 배치된 제1 세트의 비아들 및 상기 복수의 제1 TSV들의 일부에 전기적으로 연결되며 상기 유전체 층의 상기 제2 부분 내에 배치된 제2 세트의 비아들을 포함하고, 상기 복수의 비아들의 상부 단부들은 서로 같은 높이에 있는 것인, 상기 복수의 비아들
    을 포함하는 것인, 상기 인터포저;
    상기 복수의 비아들에 전기적으로 연결되는, 상기 유전체 층 상의 복수의 제1 금속 범프들로서, 상기 복수의 제1 금속 범프들은 상기 제1 다이에 전기적으로 연결된 부분을 포함하는 것인, 상기 복수의 제1 금속 범프들; 및
    상기 복수의 제1 금속 범프들에 부착되는, 상기 복수의 제1 금속 범프들 상의 제2 다이
    를 포함하는 소자.
  7. 제6항에 있어서,
    상기 인터포저에 부착된 복수의 제2 금속 범프들을 더 포함하고,
    상기 복수의 제1 금속 범프들 및 상기 복수의 제2 금속 범프들은 상기 인터포저의 대향하는 면(side)들에 있는 것인 소자.
  8. 제6항에 있어서,
    상기 제2 다이 상에서 상기 제2 다이를 둘러싸는 몰딩 컴파운드(molding compound)를 더 포함하는 소자.
  9. 소자에 있어서,
    인터포저(interposer);
    제1 다이; 및
    제2 다이를 포함하고,
    상기 인터포저는,
    실리콘 기판;
    상기 기판 내의 복수의 제1 TSV(through-substrate via)들;
    상기 인터포저의 제1 측면 상의 복수의 제1 금속 범프들로서, 상기 복수의 제1 금속 범프들의 일부는 상기 복수의 제1 TSV들에 전기적으로 연결되는 것인, 상기 복수의 제1 금속 범프들;
    상기 제1 측면과 대향하는, 상기 인터포저의 제2 측면 상의 복수의 제2 금속 범프들로서, 상기 복수의 제2 금속 범프들은 상기 복수의 제1 TSV들에 전기적으로 연결되는 것인, 상기 복수의 제2 금속 범프들; 및
    상기 인터포저의 상기 제1 측면 상의 제1 상호 접속 구조물로서, 상기 제1 상호 접속 구조물은, 상기 실리콘 기판 상의 적어도 하나의 유전체 층, 및 상기 복수의 제1 금속 범프들과 상기 복수의 제1 TSV들 사이에 전기적으로 연결되는, 상기 적어도 하나의 유전체 층 내의 재분배 라인(redistribution line)들을 포함하는 것인, 상기 제1 상호 접속 구조물
    을 포함하고,
    상기 제1 다이는 상기 복수의 제1 금속 범프들 아래에서 상기 적어도 하나의 유전체 층 내에 임베디드되어 있고, 상기 제1 다이는 상기 복수의 제1 금속 범프들에 전기적으로 연결되며,
    상기 제2 다이는 상기 복수의 제1 금속 범프들 상에서 상기 복수의 제1 금속 범프들에 부착되는 것인, 소자.
  10. 제9항에 있어서,
    상기 적어도 하나의 유전체 층 내의 복수의 비아들을 더 포함하고,
    상기 복수의 비아들은,
    상기 제1 다이에 상기 복수의 제1 금속 범프들을 전기적으로 연결하는 제1 비아; 및
    상기 복수의 제1 TSV들에 상기 복수의 제1 금속 범프들을 전기적으로 연결하는 제2 비아를 포함하는 것인, 소자.
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US20110316147A1 (en) 2011-12-29
US20130309813A1 (en) 2013-11-21
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US20200035554A1 (en) 2020-01-30
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