TWI467734B - 半導體元件 - Google Patents

半導體元件 Download PDF

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Publication number
TWI467734B
TWI467734B TW099140310A TW99140310A TWI467734B TW I467734 B TWI467734 B TW I467734B TW 099140310 A TW099140310 A TW 099140310A TW 99140310 A TW99140310 A TW 99140310A TW I467734 B TWI467734 B TW I467734B
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Taiwan
Prior art keywords
die
substrate
vias
dielectric layer
layer
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TW099140310A
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English (en)
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TW201201351A (en
Inventor
施應慶
林俊成
邱文智
鄭心圃
余振華
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台灣積體電路製造股份有限公司
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Publication of TW201201351A publication Critical patent/TW201201351A/zh
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Publication of TWI467734B publication Critical patent/TWI467734B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Description

半導體元件
本發明係有關於積體電路，且特別是有關於一種包括中介層(interposers)之三維積體電路(3DIC)與其製法。
各種電子元件(例如電晶體(transistors)、二極體(diodes)、電阻器(resistors)、電容(capacitors)等等)之集積密度(integration density)已經持續快速的提升。對大多數元件而言，集積密度之提升來自於不斷地降低特徵結構之尺寸(feature size)，以允許更多的元件整合於既定面積之中。
這些整合在本質上屬於二維(2D)的提升，其中積體元件所佔據之體積實質上位於半導體晶圓之表面上。雖然微影技術的顯著提升使2D積體電路的形成得到相當大的改進，然而對於2D空間可達到之密度仍有物理上的限制。其中之一的限制在於需要微小尺寸以構成這些元件。此外，當越多元件置於一晶片時，需要越複雜的設計。另外一項額外的限制在於，當元件數目增加時，元件間的內連線結構(interconnections)的數目與長度會顯著的增加。當內連線結構數目與長度增加時，電路RC延遲(circuit RC delay)與功率消耗(power consumption)兩者皆會增加。
為了解決上述之限制，因此衍生出三維(3D)積體電路(ICs)，其中晶粒被堆疊，且藉由使用導線接合(wire-bonding)、覆晶接合(flip-chip bonding)及/或矽穿孔(through-silicon vias,TSV)等技術將晶粒接合在一起，用以將晶粒連接到封裝基板上。然而，習知的3D ICs具有高尺寸因子(high form factor)。
本發明提供一種半導體元件，包括：一中介層(interposer)，其中該中介層包括：一基板；至少一介電層，位於該基板之上；複數個基板穿孔(through-substrate vias,TSVs)穿過該基板；一第一金屬凸塊，位於該介電層中且與該些基板穿孔電性耦合；以及一第二金屬凸塊，位於該介電層之上；以及一第一晶粒，埋設於該介電層之中且接合到該第一金屬凸塊。
本發明亦提供一種半導體元件，包括：一第一晶粒；一中介層，其中該中介層包括：一基板；複數個第一基板穿孔(through-substrate vias,TSVs)穿過該基板；複數個第一重新佈線層(redistribution lines,RDLs)，位於該基板之上且與該些基板穿孔電性耦合；一介電層，位於該基板之頂表面上，該第一晶粒位於該介電層中，其中該介電層包括一部份直接位於該第一晶粒之上，且該介電層包括一第二部份包圍該第一晶粒；以及複數個導通孔(vias)延伸到該介電層中，其中該些導通孔包括一第一部份直接位於該第一晶粒之上且與該第一晶粒電性耦合，且該些導通孔包括不與該第一晶粒對準之一第二部份，且第二部份與該些第一基板穿孔電性耦合，且其中該些導通孔之末端彼此等高；複數個第一金屬凸塊位於該介電層之上且與該些導通孔電性耦合，其中該些第一金屬凸塊包括一部份與該第一晶粒電性耦合；以及一第二晶粒，位於該些第一金屬凸塊之上且與該些第一金屬凸塊電性耦合。
本發明另提供一種半導體元件，包括：一中介層，其中該中介層大體上不包括積體電路元件，且該中介層包括：一矽基板；複數個第一基板穿孔(through-substrate vias,TSVs)，位於該基板中；複數個第一金屬凸塊，位於該中介層之第一側上，該第一金屬凸塊之一部份與該些第一基板穿孔電性耦合；複數個第二金屬凸塊，位於相對於該第一側之一第二側上，該第二金屬凸塊之一部份與該些第一基板穿孔電性耦合；一第一內連線結構(interconnect structure)，位於該中介層第一側上且包括：至少一介電層，位於該矽基板之上；以及重新佈線層(redistribution lines)，位於該介電層中且使該些第一金屬凸塊與該些第一基板穿孔電性耦合；一第一晶粒，埋設於該些介電層中且位於該些第一金屬凸塊底下，其中該第一晶粒與該些第一金屬凸塊電性耦合；以及一第二晶粒，位於該些第一金屬凸塊之上且與該些第一金屬凸塊電性耦合。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下特舉出本發明之實施例，並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明，並非用以限定本發明。
本發明提供一種新穎的三維積體電路(3DIC)與其製法。實施例中敘述各個製程階段。亦討論各種實施例之變化。於各種圖示與示範實施例中，類似的元件用類似的標號表示。
請參見第1A圖，提供一基板10。於說明書中，基板10與形成於基板10之相對兩側的介電層與金屬結構特徵合稱為中介層晶圓100。基板10由一半導體材料所組成，例如矽、矽化鍺(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)或其他常用之半導體材料。另外，基板10亦可由介電材料所組成，例如氧化矽(silicon oxide)。中介層晶圓100可包括，或可大體上不包括主動元件，例如電晶體。第1A圖顯示主動元件14形成於基板10的表面上。另外，中介層晶圓100可包括，或不包括被動元件，例如電容(capacitors)、電阻(resistors)、電感(inductors)及/或類似之元件。基板穿孔(through-substrate vias,TSVs) 20形成於基板10中，並且形成絕緣層21以電性隔離基板穿孔(TSVs) 20與基板10。
重新佈線層(redistribution lines,RDLs) 12形成於基板10之上，且與該基板穿孔(TSVs) 20電性耦合。重新佈線層(RDLs) 12可包括用於傳遞(routing)電子訊號(electrical signal)之金屬線(metal lines)，與用於連接後續形成的導通孔(vias)所需之金屬墊(metal pads)。於一實施例中，重新佈線層(RDLs) 12由銅所組成，話雖如此，也可由其他材料所組成，例如鋁(aluminum)、銀(silver)、鈦(titanium)、鉭(tantalum)、鎢(tungsten)、鎳(nickel)及/或上述之合金。於說明書中，請參見第1A圖，中介層晶圓100面向上的一側稱為前側(front side)，面向下的一側稱為背側(back side)。介電層18形成於重新佈線層(RDLs)12之上，並且形成一平坦表面。形成介電層18之材料可包括氮化物、聚亞醯胺(polyimide)、有機材料、無機材料以及類似之材料。於形成介電層18之後，重新佈線層(RDLs) 12被覆蓋。
接著，請參見第1B圖，晶粒22藉由，例如黏著層24，附著於介電層18之上，其中晶粒22具有接合墊(或金屬凸塊)26的一側背對於介電層18。雖然僅顯示一個晶粒，但是亦可接合複數個相同的晶粒22到中介層晶圓100上。晶粒22可以是包含積體電路元件形成於其中之元件晶粒，其中積體電路元件包括例如電晶體(transistors)、電容(capacitors)、電感(inductors)、電阻(resistors)(圖中未顯示)，或類似之元件。此外，晶粒22可以是包含核心電路(core circuits)之一邏輯晶粒(logic die)，或是一記憶體晶粒(memory die)。晶粒22之後亦可稱為第二層晶粒(tier-2 die)。
請參見第1C圖，介電層28形成於介電層18與晶粒22之上。基本上(essentially)，形成介電層28之材料可等於形成介電層18之材料或與介電層18之材料屬於同一類型。介電層28之後將包括兩部份，第一部分覆蓋晶粒22，而第二部份圍繞晶粒22。接著，請參見第1D圖，形成導通孔(vias) 30、重新佈線層(RDLs) 32與介電層34。於形成上述結構之製程的實施例中，首先(例如藉由蝕刻)於介電層18與28中形成導通孔開口(vias opening)，其中利用位於重新佈線層(RDLs) 12中的金屬墊與晶粒22之接合墊26作為蝕刻停止層。接著將金屬材料填充於導通孔開口中以形成導通孔30。接著，形成重新佈線層(RDLs) 32。於另一示範實施例中，導通孔30與重新佈線層(RDLs) 32可藉由同一金屬填充製程而形成。介電層34形成於重新佈線層(RDLs) 32之上。接著於介電層34之中形成開口，其中重新佈線層(RDLs) 32暴露的部份作為接合墊(bond pads)。重新佈線層(RDLs) 32由銅所組成，話雖如此，也可由其他材料所組成，例如鋁(aluminum)、銀(silver)、鎢(tungsten)、鈦(titanium)、鉭(tantalum)及/或上述之合金。此外，重新佈線層(RDLs) 32可具有複合結構，複合結構包括一銅層與形成於銅層之上的金屬拋光層(metal finish)，其中金屬拋光層可包括鎳層(nickel layer)、鈀層(palladium layer)、金層(gold layer)或上述之組合。在本文之後的敘述中，將介電層18與28、重新佈線層(RDLs) 12與32合稱為內連線結構(interconnect structure)。
請參見第1E圖，一載板(carrier) 36，其可以是玻璃晶圓，藉由金屬凸塊35與黏著層39(其可以是紫外光膠，或由其他已知之黏著材料所組成)接合到中介層晶圓100之前側。接著，請參見第1F圖，從中介層晶圓100之背側進行晶圓背側研磨，藉以薄化基板10，直到基板穿孔(TSVs)20暴露在外為止。為了降低基板10之背表面的高度，尚可進行一蝕刻製程，使得基板穿孔(TSVs) 20延伸突出於基板10的剩餘部份。
請再次參見第1F圖，凸塊底層金屬(under-metal-metallurgies,UBMs)37與背側金屬凸塊38形成於中介層晶圓100之背側，且上述兩者與基板穿孔20電性耦合。背側金屬凸塊38可以是焊料凸塊(solder bumps)，例如共晶焊料凸塊(eutectic solder bumps)、銅凸塊、或是由金、銀、鎳、鎢、鋁及/或上述合金形成之其他金屬凸塊。形成之製程可包括電鍍，其中電鍍可包括電極電鍍(electro plating)或無電極電鍍(electroless plating)。
雖然圖中顯示背側金屬凸塊38直接形成於基板穿孔(TSVs) 20之上，然而亦可形成其他的背側內連線結構(圖中未顯示)於背側金屬凸塊38與基板穿孔(TSVs) 20之間，並且使此背側內連線結構與背側金屬凸塊38與基板穿孔(TSVs) 20電性耦合。背側內連線結構可包括一或多層之重新佈線層，各自形成於一介電層中。
請參見第1G圖，移除載板36，且將另一載板(圖中未顯示)接合於金屬凸塊38上。接著，凸塊46(包括凸塊46A與46B)可接合至中介層晶圓100之前側。凸塊46可以是焊料凸塊，例如，凸塊46可以是銅凸塊。接著，使用面對面接合方式(face-to-face bonding)並藉由凸塊46將第一層晶粒(Tier-1 die) 44接合至中介層晶圓100。雖然圖中僅顯示一個晶粒44，然而亦可將複數個晶粒44接合至中介層晶圓100上。第一層晶粒(Tier-1 die) 44與第二層晶粒(Tier-2 die) 22可以是不同類型的晶粒。舉例而言，第一層晶粒(Tier-1 die) 44可以是一邏輯晶粒，而第二層晶粒(Tier-2 die) 22可以是一記憶體晶粒。可觀察到的是，凸塊46A用於使第一層晶粒(Tier-1 die) 44與中介層晶圓100電性耦合，而凸塊46B用於使第一層晶粒(Tier-1 die) 44與第二層晶粒(Tier-2 die) 22電性耦合。因此，晶粒22與44可直接互相連接，而不需要透過重新佈線層(RDLs)、基板穿孔(TSVs)及/或類似的結構傳遞訊號。
於接合第一層晶粒(Tier-1 die) 44之後，將底部填充物(underfill) 45填充到介於第一層晶粒(Tier-1 die) 44與中介層晶圓100之間的縫隙(gap)。可對中介層晶圓100進行切割製程(singulation)，切割中介層晶圓100，使得晶粒彼此分離，每一個晶粒包括一個晶粒22與中介層100’(如第1G圖)。於另一實施例中，在將第一層晶粒(Tier-1 die) 44接合至中介層晶圓100之前，即先對中介層晶圓100進行切割製程。
接著，請再次參見第1G圖，包含中介層100’與晶粒22、24之三維積體電路(3DIC)藉由凸塊38接合至電子元件50。電子元件50可包括一封裝基板、一印刷電路板(printed circuit board,PCB)或類似之基板。
第2A到2C圖顯示另一實施例。除非特別註明，否則與第1A-1G圖實施例相同之元件皆使用相同的標號表示。此實施例之初始步驟實質上等於第1A圖~第1D圖。雖然亦可形成某些結構特徵，例如介電層34與凸塊底層金屬(UBMs) 37，但為了簡化說明，這些結構特徵並未顯示於後續的實施例中。接著，請參見第2A圖，形成凸塊46，並將第一層晶粒(Tier-1 die) 44接合至中介層晶圓100。雖然僅顯示一個第一層晶粒(Tier-1 die) 44，然而亦可將複數個第一層晶粒(Tier-1 die) 44接合至中介層晶圓100上。同樣地，凸塊46A用於使第一層晶粒(Tier-1 die) 44與基板穿孔(TSVs) 20電性耦合，而凸塊46B用於使第一層晶粒(Tier-1 die 44)與第二層晶粒(Tier-2 die) 22電性耦合。將底部填充物(underfill) 45填入第一層晶粒(Tier-1 die) 44與中介層晶圓100之間的縫隙(gap)。接著，形成模封化合物(molding compound) 54，以覆蓋第一層晶粒(Tier-1 die) 44與中介層晶圓100。
第2B圖顯示凸塊38的形成，此時模封化合物54作為一載板，並不需使用額外的載板承載模封化合物54。接著，進行一切割製程以分割中介層晶圓100(以及接合於其上的晶粒22與44)。如第2C圖所示，此三維積體電路(3DIC)接合到電子元件上。
第3A-3C圖亦顯示另一實施例。同樣地，與第1A-1G圖之實施例中相同的元件使用相同的標號表示。此實施例之初始步驟實質上等於第1A圖~第1D圖。接著，請參見第3A圖，第一層晶粒44接合到中介層晶圓100。同樣地，凸塊46A用於使第一層晶粒(Tier-1 die) 44與基板穿孔(TSVs) 20電性耦合，而凸塊46B用於使第一層晶粒(Tier-1 die) 44與第二層晶粒(Tier-2 die) 22電性耦合。接著將底部填充物(underfill) 45填入第一層晶粒(Tier-1 die) 44與中介層晶圓100之間的縫隙(gap)。比起顯示於第2A圖中的實施例，可觀察到並未有任何的模封化合物形成於此實施例中。接著，載板36接合到第一層晶粒44。第3B圖到第3C圖顯示形成凸塊38，以及將最終的三維積體電路(resulting 3DIC)接合到電子元件50上。同樣地，於進行第3C圖步驟之前，可進行切割製程，且可同時對附著於中介層晶圓100上的載板36進行切割，或之後載板36可被切割膠帶(dicing tape)(圖中未顯示)所取代。
第4圖到第6圖顯示各種實施例。請參見第4圖，由於第二層晶粒不夠薄，無法填充於介電層18與28中，因此可於形成基板穿孔(TSVs)20之前，於基板10中形成凹口(recess)(凹口被晶粒22與介電層18、28所填滿)。晶粒22可部份地或全部地位於基板10的凹口中。三維積體電路(3DIC)之後續形成製程大體上與第1A圖到第3C圖之步驟相同。可觀察到於第4圖中，一些基板穿孔(TSVs)(標為基板穿孔20A)直接位於晶粒22底下，重新佈線層12A與基板穿孔(TSVs) 20電性耦合。因此，位於晶粒22底下的空間可用於傳遞電子訊號。另外，如第5圖所示，沒有任何基板穿孔(TSV)或重新佈線層直接形成於第二層晶粒22底下。
第6圖顯示另一實施例，其中基板穿孔(TSVs) 60形成於第二層晶粒22之中，且使第一層晶粒44與金屬凸塊38電性耦合。舉例而言，基板穿孔(TSVs) 60可使第一層晶粒44與金屬凸塊64電性耦合，金屬凸塊64係與直接位於第二層晶粒22底下的基板穿孔(TSVs) 20A電性耦合。金屬凸塊64可以是焊料凸塊、銅凸塊或類似的結構。由於建立了一條使晶粒11與金屬凸塊38電性耦合的較短電子路徑，因此最終的三維積體電路(resulting 3DIC)之電子性能得以獲得改善。須注意的是，於第6圖中，亦可形成類似於第4圖與第5圖之凹口，其中晶粒22可至少部份地或全部地位於凹口中。
於這些實施例中，第一層晶粒44與第二層晶粒22接合到中介層的同一側，因此，第一層晶粒44與第二層晶粒22可藉由直接接合而直接溝通(talk directly)。另一方面而言，晶粒44與22位於同一側，中介層的另外一側並不具有任何晶粒位於其上，因此，基板上允許存在的金屬凸塊的數目得以達到最大化(maximized)。此外，亦可改善尺寸因子(form factor)。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．基板
12、12A．．．重新佈線層(RDLs)
14．．．主動元件
18．．．介電層
20、20A．．．基板穿孔(TSVs)
21．．．絕緣層
22．．．第二層晶粒(tier-2 die)
24．．．黏著層
26．．．接合墊(bonding pads)
28‧‧‧介電層
30‧‧‧導通孔(vias)
32‧‧‧重新佈線層(RDLs)
34‧‧‧介電層
35‧‧‧金屬凸塊
36‧‧‧載板(carrier)
37‧‧‧凸塊底層金屬(UBMs)
38‧‧‧金屬凸塊
39‧‧‧黏著劑
44‧‧‧第一層晶粒(dier-1 die)
45‧‧‧底部填充物(underfill)
46A、46B‧‧‧凸塊
50‧‧‧電子元件
54‧‧‧模封化合物
60‧‧‧基板穿孔(TSVs)
100‧‧‧中介層晶圓
100’‧‧‧中介層
第1A~1G圖為一系列剖面圖，用以說明本發明一實施例製作三維積體電路(3DIC)之各個製程階段，其中晶粒埋設於中介層一側的介電層中。
第2A~2C圖為一系列剖面圖，用以說明本發明一較佳實施例製作三維積體電路(3DIC)之各個製程階段，其中形成金屬凸塊於中介層之相對側之前，第一層晶粒與對各自的模封化合物接合/塗佈於中介層上。
第3A~3C圖為一系列剖面圖，用以說明本發明一較佳實施例製作三維積體電路(3DIC)之各個製程階段，其中形成焊料凸塊於中介層相對側上之後，第一層晶粒(不具有模封化合物)接合至中介層。
第4~6圖為一系列剖面圖，用以說明本發明各種三維積體電路(3DIC)之實施例。
10．．．基板
18．．．介電層
20．．．基板穿孔(TSVs)
22．．．第二層晶粒(tier-2 die)
28．．．介電層
30．．．導通孔(vias)
34．．．介電層
37．．．凸塊底層金屬(UBMs)
38．．．金屬凸塊
44．．．第一層晶粒(dier-1 die)
45．．．底部填充物(underfill)
46A、46B．．．凸塊
50．．．電子元件
100’．．．中介層

Claims (10)

  1. 一種半導體元件，包括：一中介層(interposer)，其中該中介層包括：一基板；至少一介電層，位於該基板之上；複數個基板穿孔(through-substrate vias,TSVs)穿過該基板；一第一金屬凸塊，位於該介電層中且與該些基板穿孔電性耦合；以及一第二金屬凸塊，位於該介電層之上；以及一第一晶粒，埋設於該介電層之中且藉由一重新佈線層接合到該第一金屬凸塊，其中該重新佈線層位於該第一晶粒遠離該基板之一側。
  2. 如申請專利範圍第1項所述之半導體元件，其中該中介層包括一矽基板或一介電基板。
  3. 如申請專利範圍第1項所述之半導體元件，尚包括一導通孔(via)於該介電層中，且藉由該導通孔使第二金屬凸塊與該些基板穿孔電性耦合，其中該導通孔從高於該第一晶粒之頂表面延伸到低於該第一晶粒之底表面。
  4. 一種半導體元件，包括：一第一晶粒；一中介層，其中該中介層包括：一基板；複數個第一基板穿孔(through-substrate vias,TSVs) 穿過該基板；複數個第一重新佈線層(redistribution lines,RDLs)，位於該基板之上且與該些基板穿孔電性耦合；一介電層，位於該基板之頂表面上，該第一晶粒位於該介電層中，其中該介電層包括一部份直接位於該第一晶粒之上，且該介電層包括一第二部份包圍該第一晶粒；以及複數個導通孔(vias)延伸到該介電層中，其中該些導通孔包括一第一部份直接位於該第一晶粒之上且與該第一晶粒電性耦合，且該些導通孔包括不與該第一晶粒對準之一第二部份，且第二部份與該些第一基板穿孔電性耦合，且其中該些導通孔之末端彼此等高；複數個第一金屬凸塊位於該介電層之上且與該些導通孔電性耦合，其中該些第一金屬凸塊包括一部份與該第一晶粒電性耦合，其中該第一晶粒藉由該重新佈線層接合到該第一金屬凸塊，且該重新佈線層位於該第一晶粒遠離該基板之一側；以及一第二晶粒，位於該些第一金屬凸塊之上且與該些第一金屬凸塊電性耦合。
  5. 如申請專利範圍第4項所述之半導體元件，其中該中介層之基板包括一凹口(recess)，且其中該第一晶粒之一部份位於該凹口中。
  6. 如申請專利範圍第4項所述之半導體元件，尚包括一模封化合物(molding compound)位於該第二晶粒之上且包圍該第二晶粒。
  7. 一種半導體元件，包括：一中介層，其中該中介層大體上不包括積體電路元件，且該中介層包括：一矽基板；複數個第一基板穿孔(through-substrate vias,TSVs)，位於該基板中；複數個第一金屬凸塊，位於該中介層之第一側上，該第一金屬凸塊之一部份與該些第一基板穿孔電性耦合；複數個第二金屬凸塊，位於相對於該第一側之一第二側上，該第二金屬凸塊之一部份與該些第一基板穿孔電性耦合；一第一內連線結構(interconnect structure)，位於該中介層第一側上且包括：至少一介電層，位於該矽基板之上；以及重新佈線層(redistribution lines)，位於該介電層中且使該些第一金屬凸塊與該些第一基板穿孔電性耦合；一第一晶粒，埋設於該些介電層中且位於該些第一金屬凸塊底下，其中該第一晶粒藉由該重新佈線層與該些第一金屬凸塊電性耦合且該重新佈線層位於該第一晶粒遠離該基板之一側；以及一第二晶粒，位於該些第一金屬凸塊之上且與該些第一金屬凸塊電性耦合。
  8. 如申請專利範圍第7項所述之半導體元件，其中一凹口從該矽基板之頂表面延伸到矽基板中，其中該介 電層延伸到該凹口中，且該第一晶粒之一部份位於該凹口中。
  9. 如申請專利範圍第7項所述之半導體元件，其中該第一晶粒包括該些第二基板穿孔位於其中，且該第一晶粒使該第二晶粒與該些第二金屬凸塊電性耦合。
  10. 如申請專利範圍第7項所述之半導體元件，尚包括一模封化合物(molding compound)位於該第二晶粒之上且包圍該第二晶粒。
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