CN102163596B - 集成电路元件及其形成方法 - Google Patents

集成电路元件及其形成方法 Download PDF

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CN102163596B
CN102163596B CN2011100348266A CN201110034826A CN102163596B CN 102163596 B CN102163596 B CN 102163596B CN 2011100348266 A CN2011100348266 A CN 2011100348266A CN 201110034826 A CN201110034826 A CN 201110034826A CN 102163596 B CN102163596 B CN 102163596B
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internal connection
wire structure
substrate
chip
integrated circuit
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CN102163596A (zh
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胡宪斌
余振华
陈明发
林俊成
赖隽仁
林咏淇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明一实施例提供一种集成电路元件及其形成方法，该集成电路元件包括：一中介层，大抵不具有集成电路元件，其中该中介层包括：一基底，具有一第一侧及相反于该第一侧的一第二侧；多个穿基底导电结构，位于该基底之中；一第一内连线结构，位于该基底的该第一侧上，且电性耦接至至少一所述多个穿基底导电结构；以及一第二内连线结构，位于该基底的该第二侧上，且电性耦接至至少一所述多个穿基底导电结构；一第一芯片，接合于该第一内连线结构之上；以及一第二芯片，接合于该第二内连线结构之上。本发明的实施例可避免可能造成的合格率损失。此外，流程时间可减少。

Description

集成电路元件及其形成方法
技术领域
本发明涉及集成电路，且特别涉及包含中介层(interposers)的三维集成电路(three-dimensional integrated circuits，3DICs)及其形成方法。
背景技术
自从集成电路的发明起，半导体工业已经历持续的快速成长，这是由于各种电子元件(即，晶体管、二极管、电阻元件、电容元件等)的整合密度的持续增进。占最大原因地，此整合密度的增进来自于最小特征尺寸(minimumfeature size)的一再缩小化，其允许了更多元件整合至所给予的芯片面积中。
这些整合增进实际上为实质二维的，其中所整合的元件所占的体积实质于半导体晶片的表面上。虽然，微影工艺的显著的增进已于二维集成电路制作中造成相当大的进步，但在二维中所能达到的密度有着物理限制。这些限制其中之一为制造这些元件所需的最小尺寸。并且，当更多的元件放进一芯片中时，需要更多复杂的设计。另一附加限制是因为随着元件数目的增加，元件间的内连线的数目与长度随的而显著增加。当内连线的长度与数目增加时，电路的电阻电容延迟(RC delay)与功率损耗(power consumption)也都增加。
因而形成了三维集成电路(3DICs)，其中可堆叠两芯片，其于其中一芯片中形成有穿硅导电结构(through-silicon vias，TSVs)以将另一芯片连接至封装基板。穿硅导电结构常常在前端工艺(front-end-of-line，FEOL)(其中形成了元件，例如，晶体管)之后形成，且还可能在后端工艺(back-end-of-line，BEOL)(其中形成了内连线结构)之后形成。这可能造成已形成的芯片的合格率损失。再者，既然穿硅导电结构是在集成电路形成之后才形成，制造的流程时间也会拉长。
发明内容
为克服上述现有技术的缺陷，本发明一实施例提供一种集成电路元件，包括：一中介层，大抵不具有集成电路元件，其中该中介层包括：一基底，具有一第一侧及相反于该第一侧的一第二侧；多个穿基底导电结构，位于该基底之中；一第一内连线结构，位于该基底的该第一侧上，且电性耦接至至少一所述多个穿基底导电结构；以及一第二内连线结构，位于该基底的该第二侧上，且电性耦接至至少一所述多个穿基底导电结构；一第一芯片，接合于该第一内连线结构之上；以及一第二芯片，接合于该第二内连线结构之上。
本发明一实施例提供一种集成电路元件，包括：一中介层，大抵不具有集成电路元件，其中该中介层包括：一基底，具有一第一侧及相反于该第一侧的一第二侧；多个穿基底导电结构，位于该基底之中；一第一内连线结构，位于该基底的该第一侧上，且电性耦接至至少一所述多个穿基底导电结构；以及一开口，位于该基底之中，且邻接至少一所述多个穿基底导电结构；一第一芯片，接合于该第一内连线结构之上；以及一第二芯片，形成于该开口之中，且接合至该第一内连线结构之上。
本发明一实施例提供一种集成电路元件的形成方法，包括：提供一硅基底，大抵不具有集成电路元件；形成一穿基底导电结构，自该硅基底的一前侧穿过该硅基底至一预定深度；于该硅基底的该前侧上形成一第一内连线结构，其中该第一内连线结构包括至少一介电层及位于该至少一介电层中的金属结构；将一第一芯片接合至该第一内连线结构上；自该硅基底的一背侧移除该硅基底以使该穿基底导电结构的一端露出；于该硅基底的该背侧上形成一第二内连线结构，且该第二内连线结构电性耦接至该穿基底导电结构的该端；形成一开口，穿过该第二内连线结构及该硅基底，并到达该第一内连线结构的一表面；以及将一第二芯片接合至该开口中的该第一内连线结构的该表面上。
本发明的实施例可避免因为于芯片中形成穿基底导电结构时所可能造成的合格率损失。再者，因为中介层晶片及相应的穿基底导电结构可形成于芯片已形成的时候，所以流程时间可减少。
也揭示其他实施例。
附图说明
图1A-图1I显示根据本发明实施例制造三维集成电路的工艺剖面图，其中芯片接合于中介层的两侧上。
图2A-图2D显示根据本发明实施例制造三维集成电路的工艺剖面图，其中使用封装化合物以形成用以形成更多大凸块的平坦表面。
图3A-图3C显示根据本发明实施例制造三维集成电路的工艺剖面图，其中使用虚置硅晶片以形成用以形成更多大凸块的平坦表面。
图4A-图4E显示根据本发明实施例制造三维集成电路的工艺剖面图，其中一芯片位于中介层的开口之中。
图5A-图5D显示根据本发明实施例制造三维集成电路的工艺剖面图，其中中介层中的穿基底导电结构具有不同的长度。
其中，附图标记说明如下：
10～基底；
12、32、58～内连线结构；
14～金属线路；
16～介层窗；
18、25～介电层；
20、20A、20B～穿基底导电结构；
22、50～芯片；
23、52、80～底胶；
24～前侧(金属)凸块(或焊盘)；
26～承载基板；
28～粘着层；
34～介电层；
36～凸块下金属层；
38～背侧金属凸块；
38A、38B、38B’～凸块；
49～重布线路；
54～封装化合物；
56～深介层窗；
60～切割胶带；
62～线；
66～虚置晶片；
68～空腔；
69、70～氧化物层；
72～表面；
74～开口；
76～光致抗蚀剂；
88、88A、88B～金属结构；
100～中介层晶片；
L1、L2～长度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。为了简单与清楚化，许多结构可能会绘成不同的尺寸。
提供一种新颖的三维集成电路(3DIC)及其形成方法。将说明制造实施例的中间工艺步骤。将讨论实施例的变化。在通篇的图式与实施例中，相似的标号将用以标示相似的元件。
请参照图1A，提供基底10。在通篇说明中，基底10及对应的内连线结构12及32(未显示于图1A中，请参照图1D)将共同称作中介层晶片(interposerwafer)100。基底10可由半导体材料形成，例如硅、硅锗、碳化硅、砷化镓、或其他常用的半导体材料。或者，基底10由介电材料形成。中介层晶片100大抵不具有集成电路元件，包含例如是晶体管及二极管的有源元件。此外，中介层晶片100可包括(或可不具有)例如是电容元件、电阻元件、电感元件、变容元件(varactors)、及/或其相似物的被动元件。
前侧(front-side)内连线结构12形成于基底10之上。内连线结构12包括一或更多的介电层18及位于介电层18中的金属线路(metal lines)14及介层窗(vias)16。在通篇的叙述中，中介层晶片100在图1A中朝上的一侧称作前侧，而朝下的一侧称作背侧。金属线路14及介层窗16称作前侧重布线路(front-side redistribution lines，RDLs)。再者，穿基底导电结构(through-substratevias，TSVs)20形成于基底10中至预定深度，且可能穿过一些或全部的介电层18。穿基底导电结构20电性耦接至前侧重布线路(14/16)。
接着，于中介层晶片100的前侧上形成前侧(金属)凸块(或焊盘)24，且其电性耦接至穿基底导电结构20及重布线路(14/16)。在一实施例中，前侧金属凸块24为焊料凸块(solder bumps)，例如共晶焊料凸块(eutectic solderbumps)。在另一实施例中，前侧金属凸块24为铜凸块或其他金属凸块，其可由金、银、镍、钨、铝、及/或前述的合金而形成。前侧金属凸块24可突出于内连线结构12的表面。
请参照图1B，将芯片(dies)22接合至前侧金属凸块24。芯片22可为包含集成电路元件的元件芯片，例如包含晶体管、电容元件、电感元件、电阻元件(未显示)、及其相似物于其中。再者，芯片22可为包括核心电路(corecircuit)的逻辑芯片，且可例如为中央处理单元(center processing unit，CPU)芯片。芯片22与前侧金属凸块24之间的接合可为焊料接合(solder bonding)或直接金属对金属接合(direct metal-to-metal bonding)，例如铜对铜接合。作为替代地，芯片22在背侧内连线结构32(图1D)形成之后才接合，之后将详细讨论。底胶23注入于芯片22与中介层晶片100之间的间隔之中，并被固化。
请参照图1C，通过粘着层28将承载基板(carrier)26(其可为玻璃晶片，glass wafer)接合至中介层晶片100的前侧之上。粘着层28可为紫外线胶(UVglue)或可由其他所知的粘着材料形成。进行晶片背侧研磨以自背侧薄化基底10直至穿基底导电结构20露出。可进行蚀刻工艺以进一步降低基底10的表面而使穿基底导电结构20突出于基底10剩余部分的背表面。
接着，如图1D及图1E所示，形成背侧内连线结构32以连接穿基底导电结构20。在许多实施例中，背侧内连线结构32可具有相似于前侧内连线结构12的结构，而可包括金属凸块及一或更多层的重布线路。例如，背侧内连线结构32可包括位于基底10上的介电层34，其中介电层34可为低温聚酰亚胺层(low-temperature polyimide layer)或可由所周知的介电材料形成，例如旋涂玻璃(spin-on glass)、氧化硅、氮氧化硅、或其相似物。介电层34可使用化学气相沉积(CVD)而形成。当使用低温聚酰亚胺层时，介电层34也可用作应力缓冲层。如图1E所示，接着形成凸块下金属层(UBM)36及背侧金属凸块38A。相似地，背侧金属凸块38A可为焊料凸块，例如共晶焊料凸块、铜凸块、或其他由金、银、镍、钨、铝、及/或前述的合金所形成的金属凸块。在一实施例中，凸块下金属层36及背侧金属凸块38A的形成可包括毯覆式形成凸块下金属层、于凸块下金属层上形成遮罩，其具有开口、于开口中电镀背侧金属凸块38A、移除遮罩、及进行快速蚀刻以移除毯覆式凸块下金属层先前由遮罩所覆盖的部分。
请参照图1F，将芯片50接合至中介层晶片100的背侧。芯片50可通过前侧内连线结构12、背侧内连线结构32、及穿基底导电结构20而电性耦接至芯片22。芯片22及芯片50可为不同形式的芯片。例如，芯片22可为逻辑芯片，例如CPU芯片，而芯片50可为记忆体芯片。
接着，如图1H所示，于中介层晶片100的背侧上形成大凸块38B，且其电性耦接至背侧内连线结构32、穿基底导电结构20、及可能的芯片22及50。大凸块38B可为焊料凸块，其例如由共晶焊料(eutectic solder)形成，虽然它们也可为其他形式的凸块，例如金属接点(metal bonds)。在其他实施例中，接合芯片50及形成大凸块38B的顺序可颠倒。图1G显示另一实施例，其中先形成大凸块38B，接着接合芯片50以形成显示于图1H中的结构。在这些实施例中，凸块38A(以下称为小凸块)及大凸块38B可使用单一步骤凸块形成工艺(one-step bump formation process)而同时形成。
在图1I中，取下如图1H所示的承载基板26，例如借由对粘着层28(UV胶)照射紫外光而造成粘着层28失去黏性。接着，将切割胶带60贴合至最终结构的前侧。接着，沿着线62进行切割以将中介层晶片100及接合于中介层晶片100上的芯片22及50分离成数个芯片。
在图1I中，由于芯片50的存在，中介层晶片100的部分的背侧不可用于形成大凸块38B。然而，在显示于图2A-图2D的其他实施例中，可形成更多的大凸块38B，这是因为一些大凸块38B(如图2D所示，标示为38B’)可形成作垂直对准并重叠于芯片50。简要的工艺流程显示于图2A-图2D之中。此实施例的起始工艺步骤可实质上相同于第1A-1F图所示者，其中形成了用以接合芯片50的小凸块38A，而这一次不形成大凸块38B。接着，如图2A所示，将芯片50接合至中介层晶片100的背侧。将底胶52填入芯片50与中介层晶片100之间的间隔之中，并接着将底胶52固化。
请参照图2B，将封装化合物(molding compound)54(或称为封装材料，encapsulating material)形成于芯片50及中介层晶片100之上。封装化合物54的顶表面可高于或等高于芯片50的顶表面。请参照图2C，形成深介层窗(deepvias)56以穿过封装化合物54，并电性耦接至背侧内连线结构32。接着，形成内连线结构58，其包括电性耦接至深介层窗56的重布线路49，并接着形成凸块下金属层(未标示)及大凸块38B。再次，可于凸块下金属层之下形成应力缓冲层，其可由聚酰亚胺层或防焊层(solder resist)而形成。可发现一些大凸块38B(标作38B’)可直接形成于部分的芯片50之上，且与部分的芯片50垂直重叠，因而大凸块38B的数目可增加至超出图1I所示的结构。
在图2D中，取下承载基板26。接着，将切割胶带60贴合至最终结构的前侧。接着，进行切割以将中介层晶片100及接合于中介层晶片100上的芯片22及50分离成多个芯片。
图3A-图3D显示另一实施例，此实施例的起始工艺步骤可实质上相同于显示于图1A-图1F及图2A中者，其中芯片50接合于中介层晶片100之上。接着，如第3A图所示，将虚置晶片(dummy wafer)66接合至中介层晶片100之上，其中虚置晶片的材料也称为封装材料(encapsulating material)。在一实施例中，虚置晶片66为一虚置硅晶片。在另一实施例中，虚置晶片66由其他半导体材料形成，例如碳化硅、砷化镓、或其相似物。虚置晶片66可不具有集成电路元件(例如电容元件、电阻元件、变容元件、电感元件、及/或晶体管)于其中。在又一实施例中，虚置晶片66可为介电材料晶片(dielectric wafer)。空腔(cavities)68形成于虚置晶片66之中。虚置晶片66于中介层晶片100上的接合可包括氧化物对氧化物接合(oxide-to-oxidebonding)。在一实施例中，在虚置晶片66接合至中介层晶片100上之前，预先于虚置晶片66上形成氧化物层69，其可由氧化硅(例如，热氧化物，thermaloxide)所形成，且氧化物层70可预先形成于中介层晶片100之上。接着，通过氧化物对氧化物接合而将氧化物层69接合至氧化物层70之上。因此，芯片50藏置于空腔68之中，且最终结构的表面72是平坦的。
接着，如图3B所示，形成穿基底导电结构(即，深介层窗56)以穿过虚置晶片66及氧化物层69及70，并电性耦接至背侧内连线结构32。接着，形成内连线结构58，其包括电性耦接至深介层窗56的重布线路49，并接着形成凸块下金属层(未标示)及大凸块38B。再次，大凸块38B包括凸块38B’，其直接形成于芯片50之上，且垂直重叠于芯片50。
在图3C中，将承载基板26取下。接着，将切割胶带60粘贴至最终结构的一侧上。接着，进行切割以将中介层晶片100及接合于中介层晶片100上的芯片22及50分离成多个芯片。
图4A-图4D显示又一实施例，其中芯片50位于中介层晶片100中的空腔中。首先，形成显示于图4A中的结构，其中工艺可实质上相同于如图1A-图1E所示。因此，形成的细节在此不再讨论。接着，如图4B所示，于中介层晶片100中形成开口74，例如可使用湿式蚀刻或干式蚀刻。其进行可借由形成并图案化光致抗蚀剂76，且接着通过光致抗蚀剂76中的开口蚀刻中介层晶片100。蚀刻可停止于当蚀刻到前侧内连线结构12时，或前侧内连线结构12中的部分的金属结构(metal features)露出时。前侧内连线结构12中所露出的金属结构可用作焊盘(bond pads)。
在图4C中，将芯片50插入开口74中，并接合至前侧内连线结构12中的金属结构之上。接合可为焊料接合、金属对金属接合、或其相似接合。因此，芯片50可电性耦接至芯片22及穿基底导电结构20。接着，将底胶80填入开口74中的剩余空间之中。
请参照图4D，形成大凸块38B。在另一实施例中，大凸块38B形成于开口74的形成(图4B)与芯片50的接合之前。在图4E中，粘贴切割胶带60，且可将显示于图4E中的三维集成电路切割成个别的芯片。
在另一实施例中，在形成显示于图4C的结构之后，将封装化合物54(第2B-2D图)或虚置晶片66(图3A-图3C)形成/接合于显示于图4C的结构上，以及中介层晶片100的相对于芯片22的相反侧上。剩余的工艺步骤可相似于显示于第2B-2D图及图3A-图3C中，因而在此不再讨论。再者，在每一上述讨论的实施例中，可在接合芯片50之前或之后，将芯片22接合至中介层晶片50之上，并可在形成大凸块38B后接合。
在以上的实施例中，中介层晶片100中的穿基底导电结构20(例如参照图1C)可具有相同的长度。在另一实施例中，穿基底导电结构20可具有不同的长度。图5A-图5D显示形成具有不同长度的穿基底导电结构20的实施例。请参照图5A，提供中介层晶片100的基底10，且内连线结构12形成于基底10之上。内连线结构12包括凸块下金属层及凸块(未标示)。接着，如图5B所示，将芯片22接合至中介层晶片100之上，且将底胶23注入芯片22与中介层晶片100之间的间隔中，并将底胶23固化。
请参照图5C，将承载基板26(其可为玻璃晶片)通过粘着层28而接合至中介层晶片100的前侧上。进行晶片背侧研磨以自背侧将基底10薄化至所需的厚度。接着，形成穿基底导电结构开口(TSV openings)(其由所示的穿基底导电结构20所占据)以穿过基底10。再者，穿基底导电结构开口延伸进入介电层18，其用以形成内连线结构12。接着，于穿基底导电结构开口中填充金属材料以形成穿基底导电结构20，并形成用以电性隔离穿基底导电结构20与基底10的介电层25。在最终结构中，(内连线结构12的)金属结构(metalfeatures)88包括金属结构88A及88B，其中金属结构88A相较于金属结构88B埋藏于较深的介电层18内部。在穿基底导电结构开口的形成中，金属结构88A及88B可用作蚀刻停止层，因而介电层18的蚀刻停止于不同的深度。因此，穿基底导电结构20A的长度L1(图5D)大于穿基底导电结构20B的长度L2。后续工艺步骤可实质上相同于显示于图1E-图1I中，或实质相同于显示于其他实施例中者(当合适时)。
可发现在实施例中(例如，图1I、图2D、图3C及图4E)，在任何的芯片22及50中不需穿基底导电结构，虽然穿基底导电结构是可以形成于芯片22及50的。然而，芯片22及50中的元件可电性耦接至大凸块38B，并彼此电性耦接。在公知的三维集成电路中，穿基底导电结构在形成了元件芯片中的集成电路之后才形成。这造成合格率损失及封装流程时间的增加。然而，在实施例中，任何元件芯片22及50中不需穿基底导电结构，而可避免因为于芯片22及50中形成穿基底导电结构时所可能造成的合格率损失。再者，因为中介层晶片100及相应的穿基底导电结构可形成于芯片22及50已形成的时候，所以流程时间可减少。
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (9)

1.一种集成电路元件，包括：
一中介层，不具有集成电路元件，其中该中介层包括：
一基底，具有一第一侧及相反于该第一侧的一第二侧；
多个穿基底导电结构，位于该基底之中；
一第一内连线结构，位于该基底的该第一侧上，且电性耦接至至少一所述多个穿基底导电结构；以及
一第二内连线结构，位于该基底的该第二侧上，且电性耦接至至少一所述多个穿基底导电结构；
一第一芯片，接合于该第一内连线结构之上；
一第二芯片，接合于该第二内连线结构之上；
一封装材料，位于该第二内连线结构之上，且包围该第二芯片；
一封装材料，位于该第二芯片之上；以及
一空腔，位于该封装材料与该第二芯片之间。
2.如权利要求1所述的集成电路元件，还包括：
一导电介层窗，穿过该封装材料，且电性耦接至该第二内连线结构；
一第三内连线结构，位于该封装材料之上，且电性连接至该导电介层窗；以及
一凸块，形成于该第三内连线结构之上，且电性耦接至该导电介层窗。
3.如权利要求1所述的集成电路元件，还包括：
一导电介层窗，穿过该封装材料，且电性耦接至该第二内连线结构；
一第三内连线结构，位于该封装材料之上，且电性耦接至该导电介层窗；以及
一凸块，形成于该第三内连线结构之上，且电性耦接至该导电介层窗。
4.如权利要求3所述的集成电路元件，其中该封装材料包括一虚置硅基底。
5.如权利要求1所述的集成电路元件，其中所述多个穿基底导电结构具有不同的长度，且自该基底延伸进入该第一内连线结构不同的深度。
6.如权利要求1所述的集成电路元件，还包括一焊料凸块，位于该第二内连线结构之上，且邻接该第二芯片。
7.一种集成电路元件，包括：
一中介层，不具有集成电路元件，其中该中介层包括：
一基底，具有一第一侧及相反于该第一侧的一第二侧；
多个穿基底导电结构，位于该基底之中；
一第一内连线结构，位于该基底的该第一侧上，且电性耦接至至少一所述多个穿基底导电结构；以及
一开口，位于该基底之中，且邻接至少一所述多个穿基底导电结构；
一第一芯片，接合于该第一内连线结构之上；以及
一第二芯片，形成于该开口之中，且接合至该第一内连线结构之上。
8.如权利要求7所述的集成电路元件，还包括一第二内连线结构，位于该基底的该第二侧之上，且电性耦接至少一所述多个穿基底导电结构。
9.一种集成电路元件的形成方法，包括：
提供一硅基底，不具有集成电路元件；
形成一穿基底导电结构，自该硅基底的一前侧穿过该硅基底至一预定深度；
于该硅基底的该前侧上形成一第一内连线结构，其中该第一内连线结构包括至少一介电层及位于该至少一介电层中的金属结构；
将一第一芯片接合至该第一内连线结构上；
自该硅基底的一背侧移除该硅基底以使该穿基底导电结构的一端露出；
于该硅基底的该背侧上形成一第二内连线结构，且该第二内连线结构电性耦接至该穿基底导电结构的该端；
形成一开口，穿过该第二内连线结构及该硅基底，并到达该第一内连线结构的一表面；以及
将一第二芯片接合至该开口中的该第一内连线结构的该表面上。
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