TWI741388B - 半導體封裝體及其製造方法 - Google Patents
半導體封裝體及其製造方法 Download PDFInfo
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- TWI741388B TWI741388B TW108136771A TW108136771A TWI741388B TW I741388 B TWI741388 B TW I741388B TW 108136771 A TW108136771 A TW 108136771A TW 108136771 A TW108136771 A TW 108136771A TW I741388 B TWI741388 B TW I741388B
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Abstract
一種半導體封裝體包括重佈線結構、至少一個半導體裝置及多個散熱膜。所述至少一個半導體裝置安裝在所述重佈線結構上。所述多個散熱膜以並排的方式設置在所述至少一個半導體裝置上,且共同地覆蓋所述至少一個半導體裝置的上表面。一種製造半導體封裝體的方法亦被提及。
Description
本發明的實施例是有關於一種半導體封裝體及其製造方法。
半導體裝置用於各種電子應用,例如(舉例來說)個人電腦、手機、數位相機及其他電子設備。半導體裝置通常通過在半導體基底之上依序沉積絕緣層或介電層以及導電層以及使用微影將各個材料層圖案化以在半導體基底上形成電路組件及元件。
在嘗試進一步提高電路密度時,已探究了三維(three-dimensional,3D)積體電路(integrated circuit,IC)。在三維積體電路的典型形成製程中,將兩個晶粒接合在一起,且在每一晶粒與基底上的接觸接墊之間形成電連接。中介層堆疊是三維積體電路技術的一部分,其中嵌入有矽穿孔(Through-Silicon-Via,TSV)的中介層利用微凸塊連接到裝置矽。三維積體電路製造製程流程可被分成兩種類型。在基底上晶圓上晶片(chip-on-wafer-on-substrate,CoWoS)製程流程中,首先將
裝置矽晶片貼合到矽中介層晶圓,接著對矽中介層晶圓進行劃切。接著將所得的堆疊矽貼合到基底上。
然而,一些半導體封裝體趨於表現出翹曲,其中在處理期間(例如在溫度應力期間)出現基底的翹曲。所述翹曲可能造成可靠性問題(例如貼合到半導體裝置的膜型熱界面材料的分層),且這種分層將引起半導體封裝體的大的熱阻。
根據本發明的實施例,一種半導體封裝體包括重佈線結構、至少一個半導體裝置以及多個散熱膜。所述至少一個半導體裝置安裝在所述重佈線結構上。所述多個散熱膜以並排的方式設置在所述至少一個半導體裝置上且共同地覆蓋所述至少一個半導體裝置的上表面。
根據本發明的實施例,一種半導體封裝體包括基底、經包封半導體封裝體、多個散熱膜以及封蓋。所述經包封半導體封裝體設置在所述基底上。所述多個散熱膜以並排的方式設置在所述經包封半導體封裝體上且覆蓋所述經包封半導體封裝體的上表面。所述封蓋設置在所述基底上且接觸所述多個散熱膜。
根據本發明的實施例,一種製造半導體封裝體的方法包括:在基底上提供經包封半導體封裝體;將散熱片材切割成多個散熱膜;將所述多個散熱膜貼合在所述經包封半導體封裝體上,其中所述多個散熱膜共同地覆蓋所述經包封半導體封裝體的上表
面;在所述基底上提供封蓋,其中所述封蓋接觸所述多個散熱膜。
10:半導體封裝體
12、14:半導體裝置
70:經包封半導體封裝體
70BS:底表面
80、202:基底
120、140:主體
121、141:主動表面
122、142:連接接墊
200:重佈線結構
202a:第一表面
202b:第二表面
204:穿孔
206:導電接墊
230:導電接頭
240:包封材料
240a:頂表面
300:重佈線層
300s:頂表面
302:介電層
304:金屬化圖案
350:電連接件
400:散熱膜
400a:第一散熱膜
400b:第二散熱膜
500:封蓋
802:安裝部分
804:黏合劑
C:載體
PKU:封裝單元
RFL:回焊製程
S110、S120、S130、S140:步驟
SL:切割道
T1、T2:厚度
結合附圖閱讀以下詳細說明,會最好地理解本揭露的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1到圖9示出根據本揭露一些示例性實施例的半導體封裝體的製造中的中間階段的剖視圖。
圖10示出根據本揭露一些示例性實施例的半導體封裝體的製造中的中間階段的俯視圖。
圖11示出根據本揭露一些示例性實施例的半導體封裝體的製造中的中間階段的俯視圖。
圖12示出根據本揭露一些示例性實施例的半導體封裝體的製造中的中間階段的俯視圖。
圖13示出根據本揭露一些示例性實施例的半導體封裝體的的製造製程的方塊圖。
以下揭露內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露。當然,這些僅為實例而非旨在進行限制。舉例來說,在
以下說明中,在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見,且自身並不表示所論述的各個實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在…之下”、“在…下方”、“下部的”、“在…上方”、“上部的”等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。除圖中所繪示的定向以外,所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同定向。設備可被另外定向(旋轉90度或處於其他定向),且本文所使用的空間相對性描述語可同樣相應地作出解釋。
還可包括其他特徵及製程。舉例來說,可包括測試結構以幫助進行三維封裝體或三維積體電路裝置的驗證測試。測試結構可包括例如形成在重佈線層中或基底上的測試接墊,以使得能夠測試三維封裝體或三維積體電路、使用探針(probe)和/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外,本文中所揭露的結構及方法可接合包括對已知良好晶粒的中間驗證的測試方法一起使用,以提高良率並降低成本。
對於本文中提供的實施例來說,可在特定的上下文(即,
將散熱片材切割成多個散熱膜並將散熱膜貼合到經包封半導體裝置上)中論述所述技術。在加熱製程期間,半導體封裝體可能會發生翹曲,且以共同尺寸來切割的散熱膜會提高散熱膜與經包封半導體裝置之間的黏附力,從而通過降低散熱膜與經包封半導體裝置之間分層的可能性來提高散熱效率。
根據本揭露的一些實施例,製造製程可包括使用基底上晶圓上晶片(CoWoS)封裝處理形成多晶片封裝結構。其他實施例也可使用包括積體扇出型(integrated fan-out,InFO)封裝處理在內的其他處理。本文中所論述的實施例是為了提供能夠提出或使用本揭露主題的實例,且所屬領域中的一般技術人員將容易地理解可作出修改而所述修改同時保持在不同實施例的預期範圍內。相同的參考編號及字符在以下圖中指代相、同的組件。儘管方法實施例可被論述為以特定順序執行,但是其他方法實施例可以任何邏輯順序執行。
圖1到圖9示出根據本揭露一些示例性實施例的半導體封裝體的製造中的中間階段的剖視圖。現參照圖1,提供重佈線結構200。在一些實施例中,重佈線結構200可為中介層(interposer),所述中介層包括基底202、多個穿孔204以及多個導電接墊206於其中。在一些實施例中,基底202可包括塊狀半導體基底、絕緣體上矽(silicon on insulator,SOI)基底或多層式半導體材料基底。基底202的半導體材料可為矽、鍺、矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、GaAsP、AlInAs、
AlGaAs、GaInAs、GaInP、GaInAsP、或其組合。在一些實施例中,基底202可為經摻雜或未經摻雜的。在一些實施例中,導電接墊206形成在中介層(重佈線結構200)的第一表面202a上。在一些實施例中,穿孔204形成在基底202中並與導電接墊206連接。在一些實施例中,穿孔204以特定深度延伸到基底202中。在一些實施例中,穿孔204是基底穿孔。在一些實施例中,當基底202是矽基底時,穿孔204是矽穿孔。在一些實施例中,穿孔204可通過在基底202中形成孔或凹槽以及接著利用導電材料填充凹槽來形成。在一些實施例中,凹槽可通過例如蝕刻、銑削(milling)、雷射鑽孔等形成。在一些實施例中,導電材料可通過電化學鍍覆製程、化學氣相沉積(chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)或物理氣相沉積(physical vapor deposition,PVD)形成,且導電材料可包括銅、鎢、鋁、銀、金或其組合。
根據本揭露的一些實施例,與穿孔204連接的導電接墊206可被形成為形成在重佈線結構200上的重佈線層的導電部分。在一些實施例中,導電接墊206包括凸塊下金屬(under bump metallurgy,UBM)。在某些實施例中,中介層(重佈線結構200)還可包括主動裝置或被動裝置,例如形成在基底202中的電晶體、電容器、電阻器或二極體被動裝置。
在其他實施例中,重佈線結構200可為用於InFO封裝體的重佈線路層,且可通過例如沉積導電層、將導電層圖案化以形
成重佈線路、部分地覆蓋重佈線路以及利用介電層填充重佈線路之間的間隙等來形成。重佈線路的材料可包括金屬或金屬合金,包括鋁、銅、鎢和/或它們的合金。介電層可由介電材料形成,例如氧化物、氮化物、碳化物、氮化碳、其組合和/或其多層。重佈線路形成在介電層中且電連接到設置在介電層上的半導體裝置(例如,半導體裝置12、半導體裝置14)。
在圖1中,在重佈線結構200上設置至少一個半導體裝置。在本實施例中,以並排的方式在重佈線結構200上設置多個半導體裝置12、半導體裝置14,但是本揭露並非僅限於此。在一些實施例中,半導體裝置12、半導體裝置14是從晶圓單體化出的個別晶粒。在一些實施例中,多個半導體裝置12包含相同的電路,例如裝置及金屬化圖案,或者多個半導體裝置12是相同類型的晶粒。在一些實施例中,多個半導體裝置14包含相同的電路系統,或者多個半導體裝置14是相同類型的晶粒。在某些實施例中,半導體裝置12與半導體裝置14可具有不同的電路系統或者為不同類型的晶粒。在替代實施例中,半導體裝置12與半導體裝置14可具有相同的電路系統。
根據本揭露的一些實施例,半導體裝置12可為主晶粒,而半導體裝置14是輔助晶粒(tributary die)。從界定在切割道(scribe lane,SL)之間的多個封裝單元PKU來看,主晶粒可排列在封裝單元PKU的中心位置中的重佈線結構200上,而輔助晶粒排列在主晶粒的旁邊並與主晶粒隔開。在一些實施例中,輔助
晶粒排列在主晶粒周圍或環繞主晶粒。當然,半導體裝置12、半導體裝置14的數目及佈局設計並非僅限於此。在某些實施例中,半導體裝置12的表面積可大於半導體裝置14的表面積。此外,在一些實施例中,半導體裝置12與半導體裝置14可具有不同的尺寸,從而包括不同的表面積和/或不同的厚度。在一些實施例中,半導體裝置12可為邏輯晶粒,包括中央處理器(central processing unit,CPU)晶粒、圖形處理單元(graphics processing unit,GPU)晶粒、系統晶片(system-on-chip,SoC)晶粒、微控制器等。在一些實施例中,半導體裝置12可為電源管理晶粒,例如電源管理積體電路(power management integrated circuit,PMIC)晶粒。在一些實施例中,半導體裝置14可為記憶體晶粒,包括動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒或高帶寬記憶體(high bandwidth memory,HBM)晶粒。在一些實施例中,半導體裝置12包括主體120及形成在主體120的主動表面121上的連接接墊122。在某些實施例中,連接接墊122還可包括用於將半導體裝置12接合到其他結構的柱狀結構。在一些實施例中,半導體裝置14包括主體140及形成在主體140的主動表面141上的連接接墊142。在其他實施例中,連接接墊142還可包括用於將半導體裝置14接合到其他結構的柱狀結構。
根據本揭露的一些實施例,半導體裝置12、半導體裝置14例如通過利用導電接頭230進行的倒裝晶片接合而附接到重佈
線結構200的第一表面202a。通過回焊製程,在連接接墊122、連接接墊142與導電接墊206之間形成電連接及實體連接半導體裝置12、半導體裝置14與重佈線結構200的導電接頭230。在某些實施例中,導電接頭230是微凸塊,例如具有銅金屬柱的微凸塊。在另一實施例中,導電接頭230是焊料凸塊、無鉛焊料凸塊或微凸塊,例如受控塌陷晶粒連接(controlled collapse chip connection,C4)凸塊或包含銅柱的微凸塊。導電接頭230通過連接接墊122、連接接墊142以及導電接墊206將半導體裝置12、半導體裝置14與重佈線結構200的穿孔204進行電連接。
根據本揭露的一些實施例,半導體裝置12、半導體裝置14與重佈線結構200之間的接合可為焊料接合。在一些實施例中,半導體裝置12、半導體裝置14與重佈線結構200之間的接合可為直接金屬對金屬接合,例如銅對銅接合。在一些實施例中,可向半導體裝置12、半導體裝置14與環繞導電接頭230的重佈線結構200之間的間隙分配底部填充材料(未示出)。
現參照圖2,在重佈線結構200之上形成包封材料240,且包封材料240覆蓋半導體裝置12、半導體裝置14以及導電接頭230。在一些實施例中,包封材料240可為模製化合物。在一些實施例中,包封材料240包含環氧樹脂,且可通過壓縮模製或轉移模製形成。在一個實施例中,執行固化製程來固化包封材料240。在一些實施例中,半導體裝置12、半導體裝置14及導電接頭230由包封材料240包封。在一些實施例中,可執行平坦化製程(包
括研磨或拋光)以部分地移除包封材料240,從而暴露出第一晶粒(半導體裝置12)及第二晶粒(半導體裝置14)的背側表面12S、背側表面14S。因此,半導體裝置12、半導體裝置14的上表面(背側表面12S、背側表面14S)與包封材料240的頂表面240a共面(等高)。
現參照圖3,將圖2所示結構倒置或翻轉,並放置在載體C上,使得載體C直接接觸第一晶粒(半導體裝置12)及第二晶粒(半導體裝置14)的背側表面12S、背側表面14S以及包封材料240的頂表面240a。如圖3所示,在此處理階段,重佈線結構200沒有減薄且具有厚度T1。
現參照圖4,在重佈線結構200為中介層的實施例中,可對中介層200執行減薄製程以部分地移除或減薄中介層(重佈線結構200)的基底202,直到穿孔204裸露出且形成中介層的第二表面202b為止。在一些實施例中,減薄製程可包括背面研磨製程、拋光製程或蝕刻製程。在一些實施例中,在減薄製程之後,中介層(重佈線結構200)減薄到厚度T2。
現參照圖5,在基底202(中介層(重佈線結構200))的第二表面202b上形成重佈線層300。在一些實施例中,重佈線層300電連接多個穿孔204和/或電連接穿孔204與外部裝置。在某些實施例中,重佈線層300包括至少一個介電層302及介電層302中的多個金屬化圖案304。在一些實施例中,金屬化圖案304可包括接墊、通孔和/或跡線以對穿孔204進行內連,並進一步將穿孔
204連接到一個或多個外部裝置。儘管在圖5及以下圖中示出一層介電層,但是在重佈線結構中可包括多於一個介電層。在一些實施例中,介電層302的材料包括氧化矽、氮化矽、碳化矽、氮氧化矽或低介電常數介電材料(例如磷矽酸鹽玻璃材料、氟矽酸鹽玻璃材料、硼磷矽酸鹽玻璃材料、SiOC、旋塗玻璃材料、旋塗聚合物或矽化碳材料)。在一些實施例中,介電層302可通過旋轉塗布或沉積(包括化學氣相沉積(CVD)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)等)形成。在一些實施例中,金屬化圖案304包括凸塊下金屬(UBM)。在一些實施例中,金屬化圖案304的形成可包括使用微影技術及一個或多個蝕刻製程將介電層圖案化以及將金屬材料填充到經圖案化的介電層的開口中。可例如通過使用化學機械拋光製程移除介電層上的任何過量的導電材料。在一些實施例中,金屬化圖案304的材料包括銅、鋁、鎢、銀及其組合。
現參照圖6,在金屬化圖案304上設置電耦合到穿孔204的電連接件350。在一些實施例中,電連接件350被放置在重佈線層300的頂表面300s上,並且被定位在金屬化圖案304上。在一些實施例中,電連接件350包括無鉛焊料球、焊料球、球柵陣列(ball grid array,BGA)球、凸塊、C4凸塊或微凸塊。在一些實施例中,電連接件350可包括導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫或其組合。在一些實施例中,電連接件350通過
例如蒸鍍、電鍍、印刷或焊料轉移在重佈線層300上形成焊料膏且接著使所述焊料膏回焊成期望的凸塊形狀來形成。在一些實施例中,電連接件350通過植球等被放置在重佈線層300上。在其他實施例中,電連接件350通過濺射、印刷、化學鍍敷或電鍍覆或者CVD形成無焊料金屬柱(例如銅柱)以及接著通過在金屬柱上進行鍍覆形成無鉛頂蓋層來形成。
根據本揭露的一些實施例,電連接件350可用於接合到外部裝置或附加電組件。在一些實施例中,電連接件350用於接合到基底,例如電路基底、半導體基底或封裝基底等。
現參照圖7,執行單體化製程以沿著封裝單元PKU周圍的切割道SL將圖6所示封裝結構切割成多個封裝體。在整個說明中,圖7所示的包括半導體裝置12、半導體裝置14、包封材料240、重佈線結構200的封裝體被稱為經包封半導體封裝體70。因此,多個經包封半導體封裝體70中的每一者包括至少一個半導體裝置12/半導體裝置14、環繞半導體裝置12/半導體裝置14的包封材料240、包括穿孔204的重佈線結構200、包括介電層302及金屬化圖案304的重佈線層300以及設置在重佈線層300的表面(頂表面300s)上的電連接件350。在一些實施例中,單體化製程可包括鋸切(sawing)製程或切割(dicing)製程。
在單體化製程之後,將經包封半導體封裝體70從載體C分離並移除載體C。在隨後的製程中,可將經包封半導體封裝體70翻轉並進一步安裝在基底80(例如電路基底或封裝基底等)上。
現參照圖8,提供上面有安裝部分802的基底80。在一些實施例中,基底80可放置在安裝在平臺上的基底夾具(未示出)上。基底夾具可為具有多於一個夾具單元的平板夾具。在一些實施例中,基底80可包括構成基底、疊層基底、電路板(例如印刷電路板(printed circuit board,PCB))等。在一些實施例中,安裝部分802可包括形成在基底80的接墊上的預焊料。另外,基底80還可包括電接觸件或其中的其他電組件。
圖13示出根據本揭露一些示例性實施例的半導體封裝體的製造製程的方塊圖。現參照圖8及圖13,執行步驟S110,在基底80上提供至少一個經包封半導體封裝體70。在一些實施例中,經包封半導體封裝體70被設置成使其底表面70BS面對基底80。在圖8中,儘管示出一個經包封半導體封裝體70及一個基底80,但是可使用多個封裝體及多個電路基底。在一些實施例中,在回焊製程之前,經包封半導體封裝體70(以及半導體裝置12、半導體裝置14)可能稍微翹曲,但是在回焊製程之前,經包封半導體封裝體70的翹曲程度可小於在經歷回焊製程時經包封半導體封裝體70的翹曲程度。
根據本揭露的一些實施例,將經包封半導體封裝體70放置在基底80上,且接著執行回焊製程RFL。在一些實施例中,將經包封半導體封裝體70拾取並放置在基底80的頂表面之上,且封裝體70的底表面70BS上的電連接件350對準並設置在基底80的安裝部分802上。執行回焊製程作為經包封半導體封裝體70及
基底80的接合製程的一部分以將電連接件350接合到安裝部分802。在一些實施例中,回焊製程包括在回焊溫度下對電連接件350及安裝部分802執行熱加熱製程,以使電連接件350變成熔化狀態或半熔化狀態,以與基底80的安裝部分802積體及接合。電連接件350的回焊溫度需要高於電連接件350的熔點。在一個實施例中,電連接件是C4凸塊,回焊溫度介於210℃到250℃的範圍內。在一個實施例中,電連接件350是焊料球或無鉛焊料球,回焊溫度介於200℃到260℃的範圍內。
根據本揭露的一些實施例,在熱處理製程(例如回焊製程)期間,在熱衝擊下,基底80、半導體裝置(以及半導體裝置12、半導體裝置14)由於熱膨脹係數(coefficient of thermal expansion,CTE)不匹配而發生翹曲。在一些實施例中,翹曲的經包封半導體封裝體70的幾何形狀可對應於並根據翹曲的基底80的幾何形狀。在本實施例中,經包封半導體封裝體70彎曲並變得凸起(哭臉形狀(cry-shape)),但是本揭露並非僅限於此。
現參照圖9及圖13,為減少(校正)經包封半導體封裝體70及基底80的翹曲,可在基底80上提供圖9所示封蓋500,且封蓋500通過熱界面材料(thermal interface material,TIM)附接到經包封半導體封裝體70的上表面。在一些實施例中,熱界面材料可為從散熱片材切割(步驟S120)下來的多個散熱膜400。在一些實施例中,散熱膜400可包含導熱材料及電絕緣材料,例如環氧樹脂,如同與金屬(如銀或金)混合的環氧樹脂、“熱油
脂”、“白色油脂”等或其組合。舉例來說,在一些實施例中,作為實例,散熱膜400的材料可包括環氧樹脂、矽酮、無機材料(例如輕度交聯矽酮聚合物、一種或多種基質聚合物、具有一種或多種導熱填料的聚合物)、其他材料或其多個層或其組合。在包含基質聚合物的散熱膜400的實施例中,基質聚合物可包括乙烯-丙烯、乙烯-丙烯-二烯單體、氫化聚異戊二烯或其組合。在包含導熱填料的散熱膜400的實施例中,導熱填料可包括氧化鋁、氮化硼、氮化鋁、鋁、銅、銀、銦或其組合。導熱填料分散在散熱膜400內。作為另外一種選擇,散熱膜400可包含其他材料、填料及屬性。本揭露並非僅限於此。
根據本揭露的一些實施例,封蓋500的材料可包括鋼,且在其他實施例中,可為銅、不銹鋼等或其組合。可將散熱膜400貼合到經包封半導體封裝體70的上表面並共同地覆蓋(貼合到)經包封半導體封裝體70的上表面(步驟S130)。在一些實施例中,使用拾取及放置工具將散熱膜400貼合到經包封半導體封裝體70的上表面。接著可使用拾取及放置工具(可與用於散熱膜400的拾取及放置工具相同或相似)將封蓋500放置在散熱膜400上(步驟Sl40),以將封蓋500貼合到經包封半導體封裝體70的剩餘部分。在一些實施例中,封蓋500接觸散熱膜400。舉例來說,在一些實施例中,封蓋500可用作散熱器。在其他實施例中,散熱器(未示出)還可設置在封蓋500上以用於增強散熱。在替代實施例中,封蓋可包括多個靠近封蓋的頂表面設置的向上延伸的鰭。
圖10示出根據本揭露一些示例性實施例的半導體封裝製造中的中間階段的俯視圖。圖11示出根據本揭露一些示例性實施例的半導體封裝製造中的中間階段的俯視圖。現參照圖10及圖11,在一些實施例中,圖10示出在散熱膜400放置在基底80上之前安裝在基底80上的經包封半導體封裝體70的俯視圖。圖11示出在放置散熱膜400之後及在將封蓋500放置在散熱膜400上之前的結構的俯視圖。應注意,圖10中的經包封半導體封裝體70(半導體裝置12、半導體裝置14)的佈局設計可與圖8所示經包封半導體封裝體70(半導體裝置12、半導體裝置14)的佈局設計稍微不同。然而,圖10所示經包封半導體封裝體70可通過與圖1到圖8中所闡述的相同或至少相似的製造製程形成。在一些實施例中,可在基底80的將被附接封蓋(例如,圖9所示封蓋500)的外圍區上分配黏合劑804,以將封蓋附接到基底80。當安裝封蓋時,可施加壓力,並使黏合劑804固化。在一些實施例中,黏合劑804可包括高轉變溫度(transition temperature)的黏合劑。作為另外一種選擇,可使用其他類型的黏合劑804。
根據本揭露的一些實施例,如圖11所示,以共同尺寸將散熱片材切割成多個散熱膜400。在一些實施例中,散熱膜400的尺寸可相同。然而,在其他實施例中,根據半導體裝置12、半導體裝置14的實際需要及佈局設計,散熱膜400的尺寸可彼此不同。在一些實施例中,散熱膜400以並排的方式設置在經包封半導體封裝體70上。更具體來說,散熱膜400可以並排的方式設置
在半導體裝置12、半導體裝置14的上表面(背側表面)上,且共同地覆蓋(接觸)半導體裝置12、半導體裝置14的上表面,如圖11所示。在一些實施例中,散熱膜400也可覆蓋包封材料240。也就是說,散熱膜400中的至少一者可設置在包封材料240的頂表面上。
在一些實施例中,散熱膜400的尺寸可不對應於且不根據半導體裝置12、半導體裝置14的尺寸。換句話說,從俯視圖看,多個散熱膜400中的每一者的邊緣可不與半導體裝置12、半導體裝置14中的每一者的邊緣對準。對於具有一個半導體裝置12或半導體裝置14的半導體封裝體的實施例來說,散熱膜400可共同地覆蓋所述一個半導體裝置12或半導體裝置14。對於具有多個半導體裝置12及多個半導體裝置14的半導體封裝體的實施例來說,彼此相鄰的多個散熱膜400中的兩個散熱膜400可共同地覆蓋半導體裝置12/半導體裝置14中的一者。
利用這種排列,將散熱膜400切割成更小的片以貼合到經包封半導體封裝體70。因此,小片散熱膜400可容易地對應於經包封半導體封裝體70的形狀或半導體裝置12、半導體裝置14的輪廓,而不必為每一產品定製散熱片。因此,散熱膜400的排列提高了半導體封裝體10的生產率及製程靈活性。
此外,小片散熱膜400可容易地對應於經包封半導體封裝體70的上表面的曲率(翹曲)。因此,可避免或至少減少經包封半導體封裝體70的高度翹曲區處的散熱膜400的分層。分層將
在半導體封裝體10中導致大的熱阻。因此,散熱膜400的排列提高了半導體封裝體10的良率及散熱效率。
圖12示出根據本揭露一些示例性實施例的半導體封裝製造中的中間階段的俯視圖。應注意,圖12所示半導體封裝體包含與先前結合圖9到圖11揭露的半導體封裝體相同或相似的許多特徵。為清晰及簡潔起見,可省略對相同或相似特徵的詳細說明,且相同或相似的參考編號表示相同或相似的組件。圖12所示半導體封裝體與圖9到圖11所示半導體封裝體之間的主要區別闡述為如下。
現參照圖9及圖12,散熱膜400包括至少一個第一散熱膜400a及至少一個第二散熱膜400b。在一些實施例中,第一散熱膜400a的厚度和/或黏性不同於第二散熱膜400b的厚度和/或黏性。在一些實施例中,第一散熱膜400a的厚度可顯著大於第二散熱膜400b的厚度。利用這種排列,第一散熱膜400a可貼合到經包封半導體封裝體70的高度翹曲區(例如,外圍區),且第二散熱膜400b可貼合到經包封半導體封裝體70的低翹曲區(例如,中心區)。也就是說,經包封半導體封裝體70的貼合第一散熱膜400a的區具有比經包封半導體封裝體70的貼合第二散熱膜400b的另一區高的翹曲。因此,當第一散熱膜400a及第二散熱膜400b貼合到翹曲的經包封半導體封裝體70時,封蓋500仍可與第一散熱膜400a及第二散熱膜400b牢固接觸。
根據本揭露的一些實施例,第一散熱膜400a的黏性可顯
著大於第二散熱膜400b的黏性。利用這種排列,第一散熱膜400a可貼合到經包封半導體封裝體70的高度翹曲區(例如,外圍區),且第二散熱膜400b可貼合到經包封半導體封裝體70的低翹曲區(例如,中心區)。因此,可避免或至少減少經包封半導體封裝體70的高度翹曲區處的第一散熱膜400a的分層。在一些實施例中,第一散熱膜400a的厚度及黏性均可大於第二散熱膜400b的厚度及黏性。因此,可避免或減少經包封半導體封裝體70的高度翹曲區處的第一散熱膜400a的分層,且封蓋500可與第一散熱膜400a及第二散熱膜400b牢固接觸,從而改善半導體封裝體的散熱。
基於以上論述,可看出本揭露提供各種優點。然而,應理解,本文中未必論述所有優點,且其他實施例可提供不同的優點,且對於所有實施例來說並不需要特定優點。
根據本揭露的一些實施例,一種半導體封裝體包括重佈線結構、至少一個半導體裝置以及多個散熱膜。所述至少一個半導體裝置安裝在所述重佈線結構上。所述多個散熱膜以並排的方式設置在所述至少一個半導體裝置上且共同地覆蓋所述至少一個半導體裝置的上表面。在實施例中,所述半導體封裝體還包括包封材料,所述包封材料設置在所述重佈線結構上且包封所述至少一個半導體裝置。在實施例中,所述包封材料的頂表面與所述至少一個半導體裝置的所述上表面共面,且所述多個散熱膜中的至少一者設置在所述包封材料的所述頂表面上。在實施例中,所述至少一個半導體裝置包括以並排的方式設置在所述重佈線結構上
的多個半導體裝置,且所述多個散熱膜共同地覆蓋所述多個半導體裝置的多個上表面。在實施例中,所述半導體封裝體還包括基底,其中所述重佈線結構通過多個電連接件安裝在所述基底上。在實施例中,所述半導體封裝體還包括封蓋,所述封蓋設置在所述基底上且接觸所述多個散熱膜。在實施例中,所述多個散熱膜包括至少一個第一散熱膜及至少一個第二散熱膜,且所述至少一個第一散熱膜的厚度或黏性不同於所述至少一個第二散熱膜的厚度或黏性。在實施例中,所述多個散熱膜的尺寸是相同的。
根據本揭露的一些實施例,一種半導體封裝體包括基底、經包封半導體封裝體、多個散熱膜以及封蓋。所述經包封半導體封裝體設置在所述基底上。所述多個散熱膜以並排的方式設置在所述經包封半導體封裝體上且覆蓋所述經包封半導體封裝體的上表面。所述封蓋設置在所述基底上且接觸所述多個散熱膜。在實施例中,所述經包封半導體封裝體包括包封材料及被所述包封材料包封的至少一個半導體裝置,且所述多個散熱膜覆蓋所述至少一個半導體裝置的上表面。在實施例中,所述包封材料的頂表面與所述至少一個半導體裝置的所述上表面共面,且所述多個散熱膜覆蓋所述包封材料的所述頂表面。在實施例中,所述至少一個半導體裝置包括以並排的方式設置在所述基底上的多個半導體裝置,且所述多個散熱膜中的兩個散熱膜共同地覆蓋所述多個半導體裝置中的一個半導體裝置。在實施例中,所述經包封半導體封裝體還包括重佈線結構,所述至少一個半導體裝置設置在所
述重佈線結構處,且所述重佈線結構通過多個電連接件安裝在所述基底上。在實施例中,所述多個散熱膜包括至少一個第一散熱膜及至少一個第二散熱膜,且所述至少一個第一散熱膜的厚度或黏性不同於所述至少一個第二散熱膜的厚度或黏性。在實施例中,所述多個散熱膜的尺寸是相同的。
根據本揭露的一些實施例,一種製造半導體封裝體的方法包括以下步驟。在基底上提供經包封半導體封裝體。將散熱片材切割成多個散熱膜。將所述多個散熱膜貼合在所述經包封半導體封裝體上,其中所述多個散熱膜共同地覆蓋所述經包封半導體封裝體的上表面。在所述基底上提供封蓋,其中所述封蓋接觸所述多個散熱膜。在實施例中,在所述基底上提供所述經包封半導體封裝體還包括:將所述經包封半導體封裝體通過多個電連接件安裝在所述基底上。在實施例中,在所述基底上提供所述經包封半導體封裝體還包括:在重佈線結構上提供至少一個半導體裝置;在所述重佈線結構上提供包封材料,其中所述包封材料包封所述至少一個半導體裝置。在實施例中,在所述基底上提供所述經包封半導體封裝體還包括:對所述包封材料執行平坦化製程,使得所述包封材料的頂表面與所述至少一個半導體裝置的頂表面共面,其中所述多個散熱膜接觸所述至少一個半導體裝置的所述頂表面。在實施例中,所述至少一個半導體裝置包括以並排的方式排列的多個半導體裝置,且所述多個散熱膜中的兩個散熱膜共同地覆蓋所述多個半導體裝置中的一個半導體裝置。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本揭露的各個方面。所屬領域中的技術人員應理解,他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
10:半導體封裝體
12、14:半導體裝置
70:經包封半導體封裝體
70BS:底表面
80:基底
350:電連接件
400:散熱膜
500:封蓋
802:安裝部分
804:黏合劑
Claims (10)
- 一種半導體封裝體,包括:重佈線結構;至少一個半導體裝置,安裝在所述重佈線結構上;以及多個散熱膜,以並排的方式呈二維陣列設置在所述至少一個半導體裝置上,且共同地覆蓋所述至少一個半導體裝置的上表面,其中所述多個散熱膜的尺寸是相同的。
- 如申請專利範圍第1項所述的半導體封裝體,還包括包封材料,所述包封材料設置在所述重佈線結構上且包封所述至少一個半導體裝置。
- 如申請專利範圍第2項所述的半導體封裝體,其中所述包封材料的頂表面與所述至少一個半導體裝置的所述上表面共面,且所述多個散熱膜中的至少一者設置在所述包封材料的所述頂表面上。
- 如申請專利範圍第1項所述的半導體封裝體,其中所述至少一個半導體裝置包括以並排的方式設置在所述重佈線結構上的多個半導體裝置,且所述多個散熱膜共同地覆蓋所述多個半導體裝置的多個上表面。
- 如申請專利範圍第1項所述的半導體封裝體,還包括基底,其中所述重佈線結構通過多個電連接件安裝在所述基底上。
- 如申請專利範圍第1項所述的半導體封裝體,其中所述多個散熱膜包括至少一個第一散熱膜及至少一個第二散熱膜,且 所述至少一個第一散熱膜的厚度不同於所述至少一個第二散熱膜的厚度。
- 如申請專利範圍第1項所述的半導體封裝體,其中所述多個散熱膜包括至少一個第一散熱膜及至少一個第二散熱膜,且所述至少一個第一散熱膜的黏性不同於所述至少一個第二散熱膜的黏性。
- 一種半導體封裝體,包括:基底;經包封半導體封裝體,設置在所述基底上,其中所述經包封半導體封裝體包括重佈線結構、安裝在所述重佈線結構上的至少一個半導體裝置以及包封所述至少一個半導體裝置的包封材料;以及多個散熱膜,以並排的方式呈二維陣列貼合在所述經包封半導體封裝體上,且覆蓋所述經包封半導體封裝體的上表面,其中所述多個散熱膜的尺寸是相同的;以及封蓋,設置在所述基底上且接觸所述多個散熱膜。
- 一種製造半導體封裝體的方法,包括:在基底上提供經包封半導體封裝體,其中所述經包封半導體封裝體包括重佈線結構、安裝在所述重佈線結構上的至少一個半導體裝置以及包封所述至少一個半導體裝置的包封材料;將散熱片材切割成多個散熱膜;將所述多個散熱膜呈陣列貼合在所述經包封半導體封裝體 上,其中所述多個散熱膜共同地覆蓋所述經包封半導體封裝體的上表面;以及在所述基底上提供封蓋,其中所述封蓋接觸所述多個散熱膜。
- 如申請專利範圍第9項所述的製造半導體封裝體的方法,其中在所述基底上提供所述經包封半導體封裝體還包括:將所述經包封半導體封裝體通過多個電連接件安裝在所述基底上。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7348218B2 (en) * | 2005-03-29 | 2008-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing thereof |
JP5128561B2 (ja) * | 2004-05-11 | 2013-01-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 熱インターフェース接着剤及び再加工 |
US8421217B2 (en) * | 2009-01-22 | 2013-04-16 | International Business Machines Corporation | Achieving mechanical and thermal stability in a multi-chip package |
US9202769B2 (en) * | 2009-11-25 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming thermal lid for balancing warpage and thermal management |
TWI529878B (zh) * | 2012-08-29 | 2016-04-11 | 美國博通公司 | 集成電路封裝件及其裝配方法 |
CN108028239A (zh) * | 2015-08-31 | 2018-05-11 | 三星电子株式会社 | 半导体封装结构及其制造方法 |
TW201906025A (zh) * | 2017-06-30 | 2019-02-01 | 台灣積體電路製造股份有限公司 | 散熱方法 |
TW201913920A (zh) * | 2017-08-31 | 2019-04-01 | 台灣積體電路製造股份有限公司 | 半導體元件及其製造方法 |
Family Cites Families (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5128561B1 (zh) | 1967-06-05 | 1976-08-20 | ||
US8030755B2 (en) * | 2005-04-22 | 2011-10-04 | Stats Chippac Ltd. | Integrated circuit package system with a heat sink |
US8350377B2 (en) * | 2008-09-25 | 2013-01-08 | Wen-Kun Yang | Semiconductor device package structure and method for the same |
US8471376B1 (en) * | 2009-05-06 | 2013-06-25 | Marvell International Ltd. | Integrated circuit packaging configurations |
US9336310B2 (en) * | 2009-07-06 | 2016-05-10 | Google Inc. | Monitoring of negative feedback systems |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US9040349B2 (en) * | 2012-11-15 | 2015-05-26 | Amkor Technology, Inc. | Method and system for a semiconductor device package with a die to interposer wafer first bond |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9583415B2 (en) * | 2013-08-02 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with thermal interface material on the sidewalls of stacked dies |
US20150115433A1 (en) * | 2013-10-25 | 2015-04-30 | Bridge Semiconductor Corporation | Semiconducor device and method of manufacturing the same |
US9859199B2 (en) * | 2013-12-18 | 2018-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor package using carbon nano material in molding compound |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9269700B2 (en) * | 2014-03-31 | 2016-02-23 | Micron Technology, Inc. | Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
TW201601358A (zh) * | 2014-06-19 | 2016-01-01 | 道康寧公司 | 用於晶圓級z軸熱中介層的可光圖案化聚矽氧 |
TWI778938B (zh) * | 2015-03-16 | 2022-10-01 | 美商艾馬克科技公司 | 半導體裝置和製造其之方法 |
KR20160122022A (ko) * | 2015-04-13 | 2016-10-21 | 에스케이하이닉스 주식회사 | 인터포저를 갖는 반도체 패키지 및 제조 방법 |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
US10079192B2 (en) * | 2015-05-05 | 2018-09-18 | Mediatek Inc. | Semiconductor chip package assembly with improved heat dissipation performance |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
US9853011B2 (en) * | 2016-03-29 | 2017-12-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
US10483237B2 (en) * | 2016-11-11 | 2019-11-19 | Semiconductor Components Industries, Llc | Vertically stacked multichip modules |
US11004761B2 (en) * | 2017-02-28 | 2021-05-11 | Mitsubishi Electric Corporation | Packaging of a semiconductor device with dual sealing materials |
US11362044B2 (en) * | 2017-03-14 | 2022-06-14 | Mediatek Inc. | Semiconductor package structure |
US10256217B2 (en) * | 2017-05-29 | 2019-04-09 | Tslc Corp. | Light emitting device |
US10083891B1 (en) * | 2017-10-20 | 2018-09-25 | Globalfoundries Inc. | Memory having thermoelectric heat pump and related IC chip package and method |
US10636715B2 (en) * | 2017-11-06 | 2020-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of fabricating the same |
US10566261B2 (en) * | 2017-11-15 | 2020-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out packages with embedded heat dissipation structure |
KR102036762B1 (ko) * | 2018-05-15 | 2019-10-28 | 주식회사 네패스 | 반도체 패키지 |
US11075133B2 (en) * | 2018-06-29 | 2021-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Underfill structure for semiconductor packages and methods of forming the same |
US11183460B2 (en) * | 2018-09-17 | 2021-11-23 | Texas Instruments Incorporated | Embedded die packaging with integrated ceramic substrate |
US11107747B2 (en) * | 2018-09-19 | 2021-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package with composite thermal interface material structure and method of forming the same |
US10504824B1 (en) * | 2018-09-21 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
US10510713B1 (en) * | 2018-10-28 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondcutor package and method of manufacturing the same |
US11626343B2 (en) * | 2018-10-30 | 2023-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with enhanced thermal dissipation and method for making the same |
CN111211059B (zh) * | 2018-11-22 | 2023-07-04 | 矽品精密工业股份有限公司 | 电子封装件及其制法与散热件 |
US11139223B2 (en) * | 2018-11-29 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US10804172B2 (en) * | 2018-12-10 | 2020-10-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device with thermal conducting material for heat dissipation |
US10818651B2 (en) * | 2019-01-29 | 2020-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure |
US11029475B2 (en) * | 2019-04-08 | 2021-06-08 | Cisco Technology, Inc. | Frame lid for in-package optics |
US11152330B2 (en) * | 2019-04-16 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package structure and method for forming the same |
US10777518B1 (en) * | 2019-05-16 | 2020-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of manufacturing the same |
US11133282B2 (en) * | 2019-05-31 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | COWOS structures and methods forming same |
US11380620B2 (en) * | 2019-06-14 | 2022-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including cavity-mounted device |
US11282763B2 (en) * | 2019-06-24 | 2022-03-22 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device having a lid with through-holes |
US11239135B2 (en) * | 2019-07-18 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
US11011448B2 (en) * | 2019-08-01 | 2021-05-18 | Intel Corporation | IC package including multi-chip unit with bonded integrated heat spreader |
US11164855B2 (en) * | 2019-09-17 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure with a heat dissipating element and method of manufacturing the same |
US10943883B1 (en) * | 2019-09-19 | 2021-03-09 | International Business Machines Corporation | Planar wafer level fan-out of multi-chip modules having different size chips |
US11289398B2 (en) * | 2019-09-27 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and manufacturing method thereof |
KR20210063824A (ko) * | 2019-11-25 | 2021-06-02 | 삼성전자주식회사 | 방열 구조를 포함하는 전자 장치 |
-
2019
- 2019-07-29 US US16/524,172 patent/US11728238B2/en active Active
- 2019-10-09 TW TW108136771A patent/TWI741388B/zh active
- 2019-10-16 CN CN201910982516.3A patent/CN112310010A/zh active Pending
-
2022
- 2022-07-04 US US17/857,162 patent/US20220336321A1/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5128561B2 (ja) * | 2004-05-11 | 2013-01-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 熱インターフェース接着剤及び再加工 |
US7348218B2 (en) * | 2005-03-29 | 2008-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of manufacturing thereof |
US8421217B2 (en) * | 2009-01-22 | 2013-04-16 | International Business Machines Corporation | Achieving mechanical and thermal stability in a multi-chip package |
US9202769B2 (en) * | 2009-11-25 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming thermal lid for balancing warpage and thermal management |
TWI529878B (zh) * | 2012-08-29 | 2016-04-11 | 美國博通公司 | 集成電路封裝件及其裝配方法 |
CN108028239A (zh) * | 2015-08-31 | 2018-05-11 | 三星电子株式会社 | 半导体封装结构及其制造方法 |
TW201906025A (zh) * | 2017-06-30 | 2019-02-01 | 台灣積體電路製造股份有限公司 | 散熱方法 |
TW201913920A (zh) * | 2017-08-31 | 2019-04-01 | 台灣積體電路製造股份有限公司 | 半導體元件及其製造方法 |
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US11728238B2 (en) | 2023-08-15 |
TW202105640A (zh) | 2021-02-01 |
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