TW201906025A - 散熱方法 - Google Patents

散熱方法

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Publication number
TW201906025A
TW201906025A TW106142888A TW106142888A TW201906025A TW 201906025 A TW201906025 A TW 201906025A TW 106142888 A TW106142888 A TW 106142888A TW 106142888 A TW106142888 A TW 106142888A TW 201906025 A TW201906025 A TW 201906025A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
wafer
die
virtual
circuit die
Prior art date
Application number
TW106142888A
Other languages
English (en)
Inventor
余振華
陳明發
陳琮瑜
文興 洪
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201906025A publication Critical patent/TW201906025A/zh

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Abstract

一種裝置包括：積體電路晶粒，具有第一側及與所述第一側相對的第二側；晶粒堆疊，位於所述積體電路晶粒的所述第一側上；虛擬半導體特徵，位於所述積體電路晶粒的所述第一側上，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離；第一粘合劑，設置在所述晶粒堆疊與所述虛擬半導體特徵之間；以及多個傳導性連接件，位於所述積體電路晶粒的所述第二側上。

Description

散熱方法
本發明的實施例是有關於一種散熱方法。
在對積體電路進行封裝時，多個半導體晶粒可通過結合被堆疊，且可結合到例如中介層（interposer）及封裝基板等的其他封裝組件。所得的封裝被稱為三維積體電路（Three-Dimensional Integrated Circuit，3DIC）。在三維積體電路中，熱量耗散是一項挑戰。
在有效地耗散在三維積體電路的內晶粒中產生的熱量方面，可能存在瓶頸。在典型的三維積體電路中，在內晶粒中產生的熱量可必須被耗散到外元件後，所述熱量才能被傳導到散熱器。然而，在經堆疊晶粒與外元件之間，存在不能有效地傳導熱量的其他材料，例如底部填充劑、模塑化合物等。因此，熱量可能被陷滯在底部經堆疊晶粒的內區中，且因此引起尖銳的局部溫度峰值（有時被稱為熱點（hot spot））。此外，因由高功率消耗晶粒產生的熱量所致的熱點可對周圍晶粒引起熱串擾（thermal crosstalk）問題，從而負面地影響周圍晶粒的性能及整個三維積體電路封裝的可靠性。
一種散熱方法，包括：將晶粒堆疊放置在裝置晶圓的前側上；在所述裝置晶圓的背側上形成傳導性連接件；將所述裝置晶圓單體化以形成積體電路晶粒，所述晶粒堆疊設置在所述積體電路晶粒上；將所述積體電路晶粒放置在載體基板上；將虛擬晶圓的前側結合到所述積體電路晶粒，所述晶粒堆疊設置在所述虛擬晶圓的所述前側中的凹槽中；從所述載體基板剝離所述積體電路晶粒；以及將所述虛擬晶圓單體化以形成虛擬半導體特徵，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及構造的具體實例以簡化本發明。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有額外特徵、從而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...下方（beneath）”、“在...下麵（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所說明的一個元件或特徵與另一（些）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，形成一種裝置封裝，其具有位於積體電路晶粒上的晶粒堆疊以及位於所述積體電路晶粒上且環繞所述晶粒堆疊的虛擬半導體特徵。所述虛擬半導體特徵與所述積體電路晶粒及所述晶粒堆疊電性隔離。所述虛擬半導體特徵由具有高導熱性的材料形成，且有助於避免在所述積體電路晶粒與所述晶粒堆疊的介面處（例如，在所述晶粒堆疊的底部晶粒中）發生熱量積聚。避免熱量積聚可改善裝置封裝的可靠性及電氣性能。
圖1A及圖1B分別說明裝置晶圓102及在裝置晶圓102中形成的積體電路晶粒50的剖視圖。具體來說，積體電路晶粒50可為在裝置晶圓102中形成的中介層、邏輯裝置等，裝置晶圓102可包括不同的裝置區102A，所述不同的裝置區102A在後續步驟中被單體化以形成多個積體電路晶粒50。積體電路晶粒50包括基板52、裝置54、傳導性插塞56、層間介電質（inter-layer dielectric，ILD）58、內連線60、晶粒連接件62、介電材料64、及穿孔66。在一些實施例中，積體電路晶粒50是邏輯裝置等。在一些實施例中，積體電路晶粒50是中介層等。
基板52具有：前表面（例如，在圖1A及圖1B中面向上的表面），有時被稱為主動側；以及後表面（例如，在圖1A及圖1B中面向下的表面），有時被稱為非主動側。基板52是裝置晶圓102的被單體化出的一部分（例如，來自裝置區102A中的一者，以下進一步論述）。基板52可為經摻雜或未經摻雜的半導體（例如矽），或者可為絕緣體上半導體（semiconductor-on-insulator，SOI）基板的主動層。基板52可包含其他半導體材料，例如：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其組合。也可使用其他基板，例如多層式基板或梯度式基板。
裝置54可形成在基板52的前側中及/或基板52的前側上。裝置54可為電晶體、二極體、電容器、電阻器等。在其中積體電路晶粒50是邏輯晶粒的實施例中，裝置54包括主動裝置。在其中積體電路晶粒50是中介層的實施例中，裝置54可為被動裝置或可被省略，使得積體電路晶粒50不含主動裝置。傳導性插塞56電性且實體地耦合到裝置54。層間介電質58環繞裝置54及傳導性插塞56。
內連線60對裝置54進行內連，以形成積體電路。內連線60可例如由位於基板52的前側上的介電層中的金屬化圖案形成。所述金屬化圖案包括在一個或多個介電層中形成的金屬線及通孔。內連線60的金屬化圖案通過傳導性插塞56電性耦合到裝置54。
晶粒連接件62可為傳導性柱（例如，包含例如銅、鋁、鎢、鎳或其合金等的金屬），且機械及電性耦合到內連線60。晶粒連接件62可通過例如鍍覆等形成。晶粒連接件62對積體電路晶粒50的相應積體電路進行電性耦合。
介電材料64位於積體電路晶粒50的主動側上，例如位於內連線60上。介電材料64橫向包封晶粒連接件62，且介電材料64與積體電路晶粒50是橫向共邊界的。介電材料64是含矽介電層，並且可由氧化矽、SiON、SiN等形成，且可通過沉積程序（例如化學氣相沉積（chemical vapor deposition，CVD）、等離子增強化學氣相沉積（plasma enhanced chemical vapor deposition，PECVD）、物理氣相沉積（physical vapor deposition，PVD）、原子層沉積（atomic layer deposition，ALD）等）來形成。介電材料64可為內連線60的最頂層。
穿孔66形成在半導體基板中，且可為例如矽穿孔（through silicon via，TSV）。可通過施加適合的光阻並將其顯影且隨後蝕刻基板52以產生矽穿孔開口來形成穿孔66。可給所述矽穿孔開口填充例如里襯（圖中未示出）、障壁層（圖中也未示出）及傳導性材料。在實施例中，所述里襯可為介電材料（例如氮化矽、氧化矽、介電聚合物、這些材料的組合等），且可通過例如化學氣相沉積、氧化、物理氣相沉積、原子層沉積等的程序來形成。所述障壁層可包含例如氮化鈦等的傳導性材料，但作為另一選擇，可利用例如氮化鉭、鈦、另一介電質等的其他材料。可使用化學氣相沉積程序（例如等離子增強化學氣相沉積）來形成所述障壁層。然而，作為另一選擇，可使用其他替代性程序，例如濺鍍、金屬有機化學氣相沉積（metal organic chemical vapor deposition，MOCVD）、或原子層沉積（ALD）。所述障壁層可被形成為覆形於矽穿孔開口的基本形狀。所述傳導性材料可為銅、鋁、鎢、合金、經摻雜多晶矽、其組合等。可通過沉積晶種層且隨後將銅電鍍到所述晶種層上、從而填充及過填充矽穿孔開口來形成所述傳導性材料。一旦矽穿孔開口已被填充，便可通過例如化學機械拋光（chemical-mechanical polish，CMP）等的研磨程序來移除矽穿孔開口以外的多餘障壁層及多餘傳導性材料，但可使用任意適合的移除程序。
圖2至圖12B是根據一些實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。圖2至圖12B是剖視圖。在圖2至圖11中，通過將各種元件結合到裝置晶圓102來形成裝置封裝100。在實施例中，裝置封裝100是晶圓上晶圓（chip-on-wafer，CoW）封裝，但應瞭解，各實施例可應用於其他三維積體電路封裝。在圖12A及圖12B中，通過將裝置封裝100安裝到基板來形成裝置封裝200。在實施例中，裝置封裝200是基板上晶圓上晶圓（chip-on-wafer-on-substrate，CoWoS）封裝，但應瞭解，各實施例可應用於其他三維積體電路封裝。圖12A及圖12B示出不同的實施例。
在圖2中，在裝置晶圓102上形成有積體電路晶粒50之後，將晶粒堆疊104結合到裝置晶圓102的前側。晶粒堆疊104是在裝置晶圓102被單體化之前結合在每一裝置區102A中。晶粒堆疊104可為包括多個經堆疊及經內連記憶體晶粒的高頻寬記憶體（high bandwidth memory，HBM）模組或混合記憶體立方體（hybrid memory cube，HMC）模組。所述記憶體晶粒可為動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory， SRAM）晶粒等。晶粒堆疊104的各層級可利用例如矽穿孔（TSV）、微凸塊等的傳導性特徵（圖中未示出）被內連。晶粒堆疊104可通過例如混合鍵結（hybrid bonding）、熔融鍵結（fusion bonding）、焊接接合（solder joint）（例如，微凸塊）等而結合到裝置晶圓102。
在其中裝置晶圓102中形成有例如邏輯裝置等的積體電路裝置的實施例中，在操作期間，熱量可被陷滯在晶粒堆疊104下方。邏輯裝置可占每一裝置封裝100的功率消耗的一大部分；例如，邏輯裝置可占每一裝置封裝100的功率消耗的高達90%。此外，晶粒堆疊104可具有高功率密度。在其中晶粒堆疊104是經堆疊靜態隨機存取記憶體晶粒的實施例中，晶粒堆疊104可具有從50瓦（watt，W）/cm2至300 W/cm2的功率密度。晶粒堆疊104的高功率密度與裝置晶圓102的高功率消耗的組合可抑制從裝置晶圓102經由晶粒堆疊104進行熱量耗散。此可使熱量被陷滯在晶粒堆疊104中的最底晶粒處，因為來自最底晶粒的熱量必須傳播最遠的距離（例如，穿過晶粒堆疊104）。因此，熱量可積聚在裝置封裝100中，而使裝置封裝100超過標稱操作溫度，從而使裝置封裝100的可靠性及電氣性能降級。
在圖3中，在裝置晶圓102的背側上形成傳導性連接件106。可在形成傳導性連接件106之前將裝置晶圓102的背側薄化。可通過化學機械拋光（CMP）程序、研磨程序等來實現所述薄化。傳導性連接件106電性連接到裝置晶圓102的特徵（例如，邏輯裝置、中介層等），且可為球柵陣列（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶圓連接（controlled collapse chip connection，C4）凸塊、微凸塊、由無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。在一些實施例中，通過首先通過例如蒸鍍、電鍍、印刷、焊料轉移、植球等常用的方法形成一層焊料來形成傳導性連接件106。一旦已在結構上形成一層焊料，便可執行回焊以將材料成形為所需的凸塊形狀。
在圖4中，通過單體化程序將裝置晶圓102（例如，參見圖3）單體化成多個積體電路晶粒50，以形成中間裝置封裝100。經單體化積體電路晶粒50中的每一者結合到對應的晶粒堆疊104。可通過將裝置晶圓102放置在膠帶108上並沿例如位於裝置晶圓102的相鄰裝置區102A之間的切割道區進行鋸切來實現所述單體化。在一些實施例中，所述單體化程序包括鋸切程序、鐳射程序或其組合。所述單體化程序會將各封裝區中的每一者與相鄰的封裝區單體化開。
在圖5中，將包括積體電路晶粒50及晶粒堆疊104的中間裝置封裝100放置在載體基板110上。載體基板110可為玻璃載體基板、陶瓷載體基板等。載體基板110也可為晶圓等。
在圖6中，製備虛擬晶圓112。虛擬晶圓112由半導體材料形成，且可為半導體基板。所述半導體基板可為塊狀半導體（bulk semiconductor）、絕緣體上半導體（SOI）基板等，其可被摻雜（例如，以p型摻雜劑或n型摻雜劑）或未被摻雜。半導體材料在製作程序中易於獲得，且具有良好的導熱性。舉例來說，矽具有從120 W·m−1·K−1至150 W·m−1·K−1的導熱性，從而使其成為良好的熱量導體。在虛擬晶圓112的前側中圖案化有凹槽114。凹槽114的圖案對應於載體基板110上的中間裝置封裝100的圖案。凹槽114具有比積體電路晶粒50的總寬度W2小且比晶粒堆疊104的寬度W3大的寬度W1。凹槽114具有比晶粒堆疊104的高度D2大的深度D1。可通過蝕刻程序（例如適合的幹蝕刻或濕蝕刻）來圖案化出凹槽114。在實施例中，在虛擬晶圓112上形成光阻材料並將所述光阻材料暴露於光，從而在所述光阻材料中形成與凹槽114的圖案對應的圖案。隨後，可使用經圖案化光阻作為蝕刻掩模來在虛擬晶圓112中蝕刻凹槽114。在實施例中，虛擬晶圓112不具有電功能，且不含主動裝置及被動裝置。
在圖7A至圖7C中，將虛擬晶圓112的前側放置在中間裝置封裝100上。圖7A至圖7C示出不同的實施例，且針對圖7A所示實施例來說明後續處理步驟。由於晶粒堆疊104、積體電路晶粒50及凹槽114的相對寬度，晶粒堆疊104被設置在凹槽114中，且積體電路晶粒50接觸虛擬晶圓112。虛擬晶圓112結合到每一中間裝置封裝100的積體電路晶粒50。如上所述，虛擬晶圓112可不具有電功能。此外，在虛擬晶圓112與積體電路晶粒50的介面處未形成有電接面（例如，p-n接面、金屬-半導體接面等）。因此，虛擬晶圓112可與晶粒堆疊104的及積體電路晶粒50的主動裝置（例如，裝置54）、以及其他周圍裝置電性隔離。虛擬晶圓112可通過例如熔融鍵結、混合鍵結、微凸塊等而結合到積體電路晶粒50。
在其中虛擬晶圓112是通過熔融鍵結而結合到積體電路晶粒50的實施例（例如，圖7A）中，使用氧化物層（例如介電材料64等）在虛擬晶圓112與中間裝置封裝100之間形成共價鍵。在此類實施例中，介電材料64的與虛擬晶圓112接觸的部分可實質上不含晶粒連接件62；例如，晶粒連接件62可僅設置在晶粒堆疊104下方。虛擬晶圓112與中間裝置封裝100之間的介面可為矽-矽共價鍵結機制、矽-氧化物共價鍵結機制、氧化物-氧化物共價鍵結機制、或任何其他共價鍵結機制。可對積體電路晶粒50及/或虛擬晶圓112執行表面處理，從而在介電材料64的及/或虛擬晶圓112的頂部中形成OH鍵。隨後，將虛擬晶圓112對準在中間裝置封裝100之上並壓靠積體電路晶粒50，以與介電材料64形成鍵。在壓在一起之後，可將中間裝置封裝100及虛擬晶圓112退火，以強化所述鍵。在退火期間，介電材料64的及/或虛擬晶圓112的頂部中的OH鍵斷裂，以在積體電路晶粒50（例如，內連線60）與虛擬晶圓112之間形成Si-O-Si鍵，從而強化積體電路晶粒50與虛擬晶圓112之間的鍵。
在其中虛擬晶圓112是通過混合鍵結而結合到積體電路晶粒50的實施例（例如，圖7B）中，在虛擬晶圓112中形成虛擬結合墊116。在此類實施例中，未設置在晶粒堆疊104下方的晶粒連接件62可為與積體電路晶粒50的裝置54電性隔離的虛擬結合墊；例如，只有設置在晶粒堆疊104下方的晶粒連接件62才可電性連接到裝置54。如上所述，可執行表面處理。將中間裝置封裝100與虛擬晶圓112對準（包括虛擬結合墊116與晶粒連接件62）且彼此壓靠，以形成弱鍵。如上所述，可執行退火程序，以強化積體電路晶粒50的介電特徵及金屬特徵與虛擬晶圓112之間的鍵。
在其中虛擬晶圓112是通過微凸塊而結合到積體電路晶粒50的實施例（例如，圖7C）中，可在積體電路晶粒50上及虛擬晶圓112的前側上形成虛擬微凸塊118。虛擬微凸塊118可與積體電路晶粒50的裝置54電性隔離。當將虛擬晶圓112放置在中間裝置封裝100上時，可將各虛擬微凸塊118對準。隨後，可使用可回焊材料120（例如焊料）將虛擬晶圓112的微凸塊118結合到積體電路晶粒50的微凸塊118。
在圖8中，通過平面化程序將虛擬晶圓112薄化。所述平面化程序可例如是化學機械拋光程序、研磨程序等。對虛擬晶圓112的背側執行所述平面化程序，直至凹槽114延伸穿透虛擬晶圓112為止，從而形成開口122。晶粒堆疊104設置在開口122中。在所示實施例中，所述平面化程序是在形成開口122之後停止，且開口122的深度D3大於晶粒堆疊104的高度D2。在其他實施例中，在執行平面化程序之後，虛擬晶圓112的背側與晶粒堆疊104的頂表面齊平。
在圖9中，在開口122中形成粘合劑124。粘合劑124可為模塑化合物、環氧樹脂等，且可通過壓縮模塑（compression molding）、轉移模塑（transfer molding）、射出模塑（injection molding）等來施加。在開口122中形成粘合劑124，且可能會在晶粒堆疊104及/或虛擬晶圓112之上形成多餘的量。隨後，使粘合劑124固化。可執行可選的平面化程序，以移除晶粒堆疊104及/或虛擬晶圓112之上的多餘粘合劑124。在平面化之後，粘合劑124的頂表面、晶粒堆疊104的頂表面及虛擬晶圓112的頂表面是齊平的。
在圖10中，執行載體基板剝離，以從中間裝置封裝100拆離（剝離）載體基板110。隨後，通過單體化程序將虛擬晶圓112單體化，從而形成虛擬半導體特徵128。可通過將虛擬晶圓112及裝置封裝100放置在膠帶126上並沿例如位於裝置封裝100中的相鄰者之間的切割道區進行鋸切來實現所述單體化。在一些實施例中，所述單體化程序包括鋸切程序、鐳射程序或其組合。經單體化封裝是最終的裝置封裝100。
圖11示出所得的經單體化裝置封裝100。在每一裝置封裝100中，虛擬半導體特徵128環繞晶粒堆疊104並接觸積體電路晶粒50。虛擬半導體特徵128的邊緣橫向延伸越過積體電路晶粒50的邊緣。換句話說，虛擬半導體特徵128的外側壁具有比積體電路晶粒50的寬度大的寬度。虛擬半導體特徵128接觸積體電路晶粒50的頂表面的未被晶粒堆疊104及粘合劑124覆蓋的部分。在實施例中，虛擬半導體特徵128接觸積體電路晶粒50的頂表面面積的至少大部分（例如，多於50%）。
如上所述，積體電路晶粒50可為邏輯裝置，且可占每一裝置封裝100的功率消耗的高達90%。因此，積體電路晶粒50可占由每一裝置封裝100產生的熱量的高達90%。此外，虛擬半導體特徵128由為良好熱量導體的半導體材料形成。由於虛擬半導體特徵128接觸積體電路晶粒50的頂表面的至少大部分，因而虛擬半導體特徵128可有助於移除由積體電路晶粒50產生的熱量中的某些熱量。此可有助於防止熱量被陷滯在晶粒堆疊104下方，從而降低裝置封裝100的操作溫度並改善裝置封裝100的可靠性及電氣性能。
在圖12A及圖12B中，通過將裝置封裝100安裝到封裝基板202來形成裝置封裝200。封裝基板202可由例如矽、鍺、金剛石等的半導體材料形成。作為另一選擇，也可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些材料的組合等的化合物材料。另外，封裝基板202可為絕緣體上半導體基板。一般來說，絕緣體上半導體基板包含一層半導體材料，例如磊晶矽、鍺、矽鍺、絕緣體上矽（silicon-on-insulator，SOI）、絕緣體上矽鍺（silicon germanium-on-insulator，SGOI）、或其組合。在一個替代性實施例中，封裝基板202是基於絕緣芯（例如玻璃纖維強化樹脂芯）。一種示例性芯材料是玻璃纖維樹脂，例如FR4。芯材料的替代方案包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或作為另一選擇，包括其他印刷電路板（printed circuit board，PCB）材料或膜。可將例如味之素增層膜（Ajinomoto Build-up Film，ABF）等的增層膜或其他積層用於封裝基板202。
封裝基板202可包括主動裝置及被動裝置（圖中未示出）。如所屬領域中的普通技術人員將認識到，可使用各種各樣的裝置（例如電晶體、電容器、電阻器、這些裝置的組合等）來產生裝置封裝200的設計的結構性及功能性要求。可使用任意適合的方法來形成所述裝置。
封裝基板202還可包括金屬化層及通孔（圖中未示出）以及位於所述金屬化層及通孔之上的結合墊204。所述金屬化層可形成在主動裝置及被動裝置之上且被設計成將各種裝置連接以形成功能性電路系統。所述金屬化層可由交替的介電材料（例如，低介電常數介電材料）層及傳導性材料（例如，銅）層形成（其中通孔將各傳導性材料層內連），且可通過任意適合的程序（例如沉積、鑲嵌、雙重鑲嵌等）來形成。在一些實施例中，封裝基板202實質上不含主動裝置及被動裝置。
在一些實施例中，對傳導性連接件106進行回焊，以將裝置封裝100附裝到結合墊204，從而將積體電路晶粒50結合到封裝基板202。傳導性連接件106將封裝基板202（包括封裝基板202中的金屬化層）電性及/或實體地耦合到裝置封裝100。在一些實施例中，在安裝在封裝基板202上之前，可將被動裝置（例如，表面安裝裝置（surface mount device，SMD），圖中未說明）附裝到裝置封裝100（例如，被結合到結合墊204）。在此類實施例中，所述被動裝置可與傳導性連接件106結合到裝置封裝100的同一表面。
傳導性連接件106可在其被回焊之前上面先形成有環氧樹脂助焊劑（圖中未示出），其中在裝置封裝100附裝到封裝基板202之後，所述環氧樹脂助焊劑中的環氧樹脂部分中的至少某些存留下來。此種存留的環氧樹脂部分可充當底部填充劑，以降低應力並保護因對傳導性連接件106進行回焊而產生的接點。
可在裝置封裝100與封裝基板202之間形成環繞傳導性連接件106及積體電路晶粒50的底部填充劑206。底部填充劑206可在裝置封裝100被附裝之後通過毛細管流動程序（capillary flow process）而形成，或者可在裝置封裝100被附裝之前通過適合的沉積方法而形成。
在圖12A所示實施例中，將散熱器208A附裝到裝置封裝200。散熱器208A可由具有高導熱性的材料（例如鋼、不銹鋼、銅等、或其組合）形成。在一些實施例（以下論述）中，散熱器208A塗布有另一金屬（例如金）。散熱器208A覆蓋並環繞裝置封裝100。在一些實施例中，散熱器208A是單一連續的材料。在一些實施例中，散熱器208A包括可為相同材料或不同材料的多個片塊。
散熱器208A通過粘合劑210附裝到封裝基板202。粘合劑210可為環氧樹脂、膠等，且也可為導熱性材料。散熱器208A還通過熱介面材料（thermal interface material，TIM）212附裝到裝置封裝100。熱介面材料212可為聚合物材料、焊料膏、銦焊料膏等，且可在散熱器208A附裝到裝置封裝200之前被施配在晶粒堆疊104、粘合劑124及虛擬半導體特徵128上。熱介面材料212將裝置封裝100與散熱器208A熱耦合。
在圖12B所示實施例中，將支撐環208B附裝到裝置封裝200。在一些實施例中，支撐環208B可由具有高導熱性的材料（例如鋼、不銹鋼、銅等、或其組合）形成。支撐環208B為裝置封裝200提供機械加強，且可防止裝置封裝200發生翹曲。支撐環208B通過粘合劑210附裝到封裝基板202。
圖13至圖17B是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。圖13至圖17B是剖視圖。
在圖13中，在裝置封裝100被放置在載體基板110上之後，在晶粒堆疊104上形成粘合劑130。粘合劑130可為熱介面材料（類似於熱介面材料212）、晶粒貼合膜（die attach film，DAF）等、或其組合。
在圖14中，將虛擬晶圓112放置在裝置封裝100上。在放置之後，晶粒堆疊104及粘合劑130被設置在凹槽114中。放置虛擬晶圓112會使粘合劑130攤鋪開，使得粘合劑130填充凹槽114。具體來說，粘合劑130填充晶粒堆疊104的各側與虛擬晶圓112的界定凹槽114的各側之間的空隙。虛擬晶圓112可以與以上針對圖7A至圖7C所論述的方式類似的方式結合到裝置封裝100。
在圖15中，執行載體基板剝離以從裝置封裝100拆離（剝離）載體基板110。隨後，通過單體化程序將虛擬晶圓112單體化，從而形成虛擬半導體特徵128及裝置封裝100。由於凹槽114中形成有粘合劑130，因而不形成粘合劑124，且可省略各種平面化步驟。
圖16示出所得的經單體化裝置封裝100。由於可省略平面化步驟，因而虛擬半導體特徵128覆蓋晶粒堆疊104。此外，虛擬半導體特徵128的邊緣橫向延伸越過積體電路晶粒50的邊緣。
在圖17A及圖17B中，通過將裝置封裝100安裝到封裝基板202來形成裝置封裝200。在一些實施例中，對傳導性連接件106進行回焊，以將裝置封裝100附裝到封裝基板202的結合墊204。可在裝置封裝100與封裝基板202之間形成環繞傳導性連接件106及積體電路晶粒50的底部填充劑206。
在圖17A所示實施例中，將散熱器208A附裝到裝置封裝200。使用粘合劑210將散熱器208A粘附到封裝基板202。可在虛擬半導體特徵128上施配熱介面材料212，從而將裝置封裝100與散熱器208A熱耦合。
在圖17B所示實施例中，將支撐環208B附裝到裝置封裝200。使用粘合劑210將支撐環208B粘附到封裝基板202。支撐環208B為裝置封裝200提供機械加強，且可防止裝置封裝200發生翹曲。
圖18至圖24B是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。圖18至圖24B是剖視圖。
在圖18中，在裝置晶圓102被單體化成多個積體電路晶粒50之前，將虛擬晶圓112放置在裝置晶圓102上。晶粒堆疊104被設置在虛擬晶圓112的凹槽114中。虛擬晶圓112的前側結合到裝置晶圓102。虛擬晶圓112可以與以上針對圖7A至圖7C所論述的方式類似的方式結合到裝置晶圓102。
在圖19中，通過平面化程序將虛擬晶圓112薄化。對虛擬晶圓112的背側執行所述平面化程序，直至凹槽114延伸穿透虛擬晶圓112為止，從而形成開口122。
在圖20中，在開口122中形成粘合劑124。可執行可選的平面化程序，以移除晶粒堆疊104及/或虛擬晶圓112之上的多餘粘合劑124。在平面化之後，粘合劑124的頂表面、晶粒堆疊104的頂表面及虛擬晶圓112的頂表面是齊平的。
在圖21中，在裝置晶圓102的背側上形成傳導性連接件106。傳導性連接件106電性連接到裝置晶圓102的特徵。在形成傳導性連接件106之前，可將裝置晶圓102的背側薄化。
在圖22中，通過單體化程序將裝置晶圓102及虛擬晶圓112同時單體化，從而形成多個積體電路晶粒50及多個虛擬半導體特徵128。可通過將裝置晶圓102放置在膠帶126上並沿例如位於裝置晶圓102的相鄰封裝區之間的切割道區進行鋸切來實現所述單體化。在一些實施例中，所述單體化程序包括鋸切程序、鐳射程序或其組合。
圖23示出所得的經單體化裝置封裝100。由於裝置晶圓102及虛擬半導體特徵128被同時單體化，因而虛擬半導體特徵128的邊緣與積體電路晶粒50的邊緣是橫向共邊界的。換句話說，虛擬半導體特徵128的外側壁具有與積體電路晶粒50的外側壁相同的寬度。
在圖24A及圖24B中，通過將裝置封裝100安裝到封裝基板202來形成裝置封裝200。在一些實施例中，對傳導性連接件106進行回焊，以將裝置封裝100附裝到封裝基板202的結合墊204。可在裝置封裝100與封裝基板202之間形成環繞傳導性連接件106的底部填充劑206。由於積體電路晶粒50與虛擬半導體特徵128為相同的寬度，因而底部填充劑206不環繞積體電路晶粒50。
在圖24A所示實施例中，將散熱器208A附裝到裝置封裝200。使用粘合劑210將散熱器208A粘附到封裝基板202。可在晶粒堆疊104、粘合劑124及虛擬半導體特徵128上施配熱介面材料212，從而將裝置封裝100與散熱器208A熱耦合。
在圖24B所示實施例中，將支撐環208B附裝到裝置封裝200。使用粘合劑210將支撐環208B粘附到封裝基板202。支撐環208B為裝置封裝200提供機械加強，且可防止裝置封裝200發生翹曲。
圖25至圖32是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。圖25至圖32是剖視圖。在圖25至圖32所示實施例中，在虛擬晶圓112中形成通孔132。通孔132的材料具有比虛擬晶圓112的材料高的導熱性，從而進一步改善虛擬晶圓112的導熱性。雖然是在圖18至圖24B所示實施例中說明形成通孔132，但應瞭解，可針對其中散熱器208A附裝到裝置封裝200的任何實施例在虛擬晶圓112中形成通孔132。
在圖25中，製備虛擬晶圓112。在虛擬晶圓112中形成通孔132。通孔132是從虛擬晶圓112的前側至少局部地向虛擬晶圓112中延伸深度D4的矽穿孔（TSVs）。深度D4可小於凹槽114的深度D1，或者可等於或大於深度D1。
可通過向虛擬晶圓112的前側施加適合的光阻並將所述光阻顯影且隨後蝕刻虛擬晶圓112以產生矽穿孔開口來形成通孔132。可給所述矽穿孔開口填充例如里襯（圖中未示出）、障壁層（圖中也未示出）及傳導性材料。在實施例中，所述里襯可為介電材料（例如氮化矽、氧化矽、介電聚合物、這些材料的組合等），且可通過例如化學氣相沉積、氧化、物理氣相沉積、原子層沉積等的程序來形成。所述障壁層可包含例如氮化鈦等的傳導性材料，但作為另一選擇，可利用例如氮化鉭、鈦、另一介電質等的其他材料。可使用化學氣相沉積程序（例如等離子增強化學氣相沉積）來形成所述障壁層。然而，作為另一選擇，可使用其他替代性程序，例如濺鍍、金屬有機化學氣相沉積（MOCVD）、或原子層沉積（ALD）。所述障壁層可被形成為覆形於矽穿孔開口的基本形狀。所述傳導性材料可為具有比虛擬晶圓112的半導體材料高的導熱性的金屬。在實施例中，所述傳導性材料包含銅，但作為另一選擇，可利用例如鋁、鎢、合金、經摻雜多晶矽、其組合等其他適合的材料。可通過沉積晶種層且隨後將銅電鍍到所述晶種層上、從而填充及過填充矽穿孔開口來形成所述傳導性材料。一旦矽穿孔開口已被填充，便可通過例如化學機械拋光等的研磨程序來移除矽穿孔開口以外（例如，在虛擬晶圓112的前側上）的多餘障壁層及多餘傳導性材料，但可使用任意適合的移除程序。
在圖26中，將虛擬晶圓112翻轉並放置在裝置封裝100上。晶粒堆疊104被設置在凹槽114中，且積體電路晶粒50接觸虛擬晶圓112。虛擬晶圓112可以與以上針對圖7A至圖7C所論述的方式類似的方式結合到裝置晶圓102。在其中使用混合鍵結的實施例中，通孔132耦合到積體電路晶粒50的金屬特徵（例如，晶粒連接件62）。在此類實施例中，未設置在晶粒堆疊104下方的晶粒連接件62可為與積體電路晶粒50的裝置54電性隔離的虛擬結合墊；例如，只有設置在晶粒堆疊104下方的晶粒連接件62才可耦合到通孔132。
在圖27中，通過平面化程序將虛擬晶圓112薄化。對虛擬晶圓112的背側執行所述平面化程序，直至凹槽114延伸穿透虛擬晶圓112為止，從而形成開口122。
在圖28中，在開口122中形成粘合劑124。可執行可選的平面化程序，以移除晶粒堆疊104及/或虛擬晶圓112之上的多餘粘合劑124。在平面化之後，粘合劑124的頂表面、晶粒堆疊104的頂表面及虛擬晶圓112的頂表面是齊平的。
在圖29中，在裝置晶圓102的背側上形成傳導性連接件106。傳導性連接件106電性連接到裝置晶圓102的特徵。在形成傳導性連接件106之前，可將裝置晶圓102的背側薄化。
在圖30中，通過單體化程序將裝置晶圓102及虛擬晶圓112同時單體化，從而形成積體電路晶粒50及虛擬半導體特徵128。可通過將裝置晶圓102放置在膠帶126上並沿例如位於裝置晶圓102的相鄰封裝區之間的切割道區進行鋸切來實現所述單體化。
圖31示出所得的經單體化裝置封裝100。由於裝置晶圓102及虛擬半導體特徵128被同時單體化，因而虛擬半導體特徵128的邊緣與積體電路晶粒50的邊緣是橫向共邊界的。換句話說，虛擬半導體特徵128的外側壁具有與積體電路晶粒50的外側壁相同的寬度。在所示實施例中，在所得的裝置封裝100中，通孔132的深度D4大於或等於凹槽114的深度D1，且通孔132從虛擬半導體特徵128的前側延伸到背側。通孔132的更大深度可改善虛擬半導體特徵128的導熱性。
在圖32中，通過將裝置封裝100安裝到封裝基板202來形成裝置封裝200。在一些實施例中，對傳導性連接件106進行回焊，以將裝置封裝100附裝到封裝基板202的結合墊204。可在裝置封裝100與封裝基板202之間形成環繞傳導性連接件106的底部填充劑206。由於積體電路晶粒50與虛擬半導體特徵128為相同的寬度，因而底部填充劑206不環繞積體電路晶粒50。
此外，在圖32中，將散熱器208A附裝到裝置封裝200。使用粘合劑210將散熱器208A粘附到封裝基板202。可在晶粒堆疊104、粘合劑124及虛擬半導體特徵128上施配熱介面材料212，從而將裝置封裝100與散熱器208A熱耦合。
圖33示出根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟。圖33是剖視圖。圖33所示實施例類似於圖32所示實施例，只不過通孔132的深度D4小於凹槽114的深度D1。因此，通孔132局部地延伸到虛擬半導體特徵128中。將通孔132形成為更淺的深度可降低製造成本。
圖34至圖37是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。圖34至圖37是剖視圖。在圖34至圖37所示實施例中，在裝置封裝100被單體化之前，在裝置封裝100上形成虛擬金屬化層134。虛擬金屬化層134改善裝置封裝100與散熱器208A之間的熱耦合。雖然是在圖18至圖24B所示實施例中說明形成虛擬金屬化層134，但應瞭解，可針對其中散熱器208A附裝到裝置封裝200的任何實施例形成虛擬金屬化層134。
在圖34中，在晶粒堆疊104、虛擬晶圓112及粘合劑124上形成虛擬金屬化層134。虛擬金屬化層134是在形成粘合劑124之後形成。虛擬金屬化層134可由具有比虛擬晶圓112的半導體材料高的導熱性的傳導性材料或金屬（例如金、銦、銅等）形成。可通過沉積晶種層且隨後將傳導性材料電鍍到所述晶種層上來形成虛擬金屬化層134。虛擬金屬化層134可與晶粒堆疊104、積體電路晶粒50及其他周圍裝置電性隔離。
在圖35中，通過單體化程序將裝置晶圓102、虛擬晶圓112及虛擬金屬化層134同時單體化，從而形成積體電路晶粒50及虛擬半導體特徵128。可通過將裝置晶圓102放置在膠帶126上並沿例如位於裝置晶圓102的相鄰封裝區之間的切割道區進行鋸切來實現所述單體化。
圖36示出所得的經單體化裝置封裝100。由於裝置晶圓102、虛擬晶圓112及虛擬金屬化層134被同時單體化，因而虛擬半導體特徵128的邊緣與積體電路晶粒50的邊緣及虛擬金屬化層134的邊緣是橫向共邊界的。換句話說，虛擬半導體特徵128的外側壁具有與積體電路晶粒50的外側壁及虛擬金屬化層134的外側壁相同的寬度。
在圖37中，通過將裝置封裝100安裝到封裝基板202來形成裝置封裝200。在一些實施例中，對傳導性連接件106進行回焊，以將裝置封裝100附裝到封裝基板202的結合墊204。可在裝置封裝100與封裝基板202之間形成環繞傳導性連接件106的底部填充劑206。由於積體電路晶粒50與虛擬半導體特徵128為相同的寬度，因而底部填充劑206不環繞積體電路晶粒50。
此外，在圖37中，將散熱器208A附裝到裝置封裝200。在虛擬金屬化層134上施配熱介面材料212。在圖34至圖37所示實施例中，熱介面材料212是金屬性熱介面材料，例如焊料膏、銦焊料膏等。使用粘合劑210將散熱器208A粘附到封裝基板202。可在虛擬金屬化層134上施配熱介面材料212，從而將裝置封裝100與散熱器208A熱耦合。在所示實施例中，散熱器208A可具有金塗層，且熱介面材料212可被回焊，從而與所述金塗層及虛擬金屬化層134的材料形成共熔化合物。
圖38示出根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟。圖38是剖視圖。在圖38所示實施例中，在裝置封裝100與散熱器208A的介面處形成虛擬傳導性特徵214。虛擬傳導性特徵214可進一步改善裝置封裝100與散熱器208A之間的熱耦合。雖然是在圖18至圖24B所示實施例中說明形成虛擬傳導性特徵214，但應瞭解，可針對其中散熱器208A附裝到裝置封裝200的任何實施例形成虛擬傳導性特徵214。
在圖38中，在裝置封裝100上形成粘合劑216。所述粘合劑位於晶粒堆疊104、粘合劑124及虛擬半導體特徵128上。可在裝置封裝100被單體化之前或之後在裝置封裝100上形成粘合劑216。粘合劑216可與粘合劑210類似，或可為不同的。虛擬傳導性特徵214形成在粘合劑216上，且由具有比虛擬半導體特徵128的材料高的導熱性的傳導性材料形成。舉例來說，虛擬傳導性特徵214可例如是焊料球，且可通過取放方法（pick and place method）來形成。虛擬傳導性特徵214可與晶粒堆疊104、積體電路晶粒50及其他周圍裝置電性隔離。隨後，在粘合劑216上且圍繞虛擬傳導性特徵214施配熱介面材料212。散熱器208A利用粘合劑210及熱介面材料212附裝到裝置封裝200。
此外，在圖38中，將散熱器208A附裝到裝置封裝200。在粘合劑216上施配熱介面材料212。在圖34至圖37所示實施例中，熱介面材料212是金屬性熱介面材料，例如焊料膏、銦焊料膏等。使用粘合劑210將散熱器208A粘附到封裝基板202。可在粘合劑216上施配熱介面材料212，從而將裝置封裝100與散熱器208A熱耦合。在所示實施例中，散熱器208A可具有金塗層，且熱介面材料212可被回焊，從而與所述金塗層及虛擬傳導性特徵214的材料形成共熔化合物。
各實施例均可實現優點。積體電路晶粒50中的虛擬半導體特徵128可具有足以説明移除由積體電路晶粒50產生的熱量中的某些熱量的導熱性。虛擬半導體特徵128的材料（例如，矽）是充裕的，且可比其他導熱性材料具有更低成本。在虛擬半導體特徵128中添加額外特徵（例如通孔132）可進一步提高虛擬半導體特徵128的導熱性，從而降低裝置封裝100的操作溫度。此外，例如虛擬金屬化層134及/或虛擬傳導性特徵214等的特徵可提高散熱器208A的導熱性。虛擬半導體特徵128可移除的熱量足以幫助防止熱量被陷滯在晶粒堆疊104下方，從而降低裝置封裝100的操作溫度並改善裝置封裝100的可靠性及電氣性能。
在實施例中，一種散熱方法包括：將晶粒堆疊放置在裝置晶圓的前側上；在所述裝置晶圓的背側上形成傳導性連接件；將所述裝置晶圓單體化以形成積體電路晶粒，所述晶粒堆疊設置在所述積體電路晶粒上；將所述積體電路晶粒放置在載體基板上；將虛擬晶圓的前側結合到所述積體電路晶粒，所述晶粒堆疊設置在所述虛擬晶圓的所述前側中的凹槽中；從所述載體基板剝離所述積體電路晶粒；以及將所述虛擬晶圓單體化以形成虛擬半導體特徵，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離。
在一些實施例中，所述散熱方法包括：在所述將所述虛擬晶圓單體化之前，將所述虛擬晶圓的背側薄化，直至所述凹槽被暴露出為止，從而形成延伸穿透所述虛擬晶圓的開口；以及在所述開口中形成粘合劑，所述粘合劑的頂表面、所述虛擬晶圓的頂表面及所述晶粒堆疊的頂表面是齊平的。在一些實施例中，所述散熱方法進一步包括：在所述將所述虛擬晶圓的所述前側結合到所述積體電路晶粒之前，在所述晶粒堆疊上形成粘合劑；以及將所述虛擬晶圓的所述前側放置在所述積體電路晶粒上，所述粘合劑填充所述凹槽。在一些實施例中，所述散熱方法進一步包括：利用所述傳導性連接件將所述積體電路晶粒結合到封裝基板；在所述封裝基板與所述積體電路晶粒之間形成底部填充劑，所述底部填充劑環繞所述傳導性連接件及所述積體電路晶粒；以及將散熱器附裝到所述封裝基板，所述散熱器被粘附到所述虛擬半導體特徵。
在實施例中，一種散熱方法包括：將晶粒堆疊放置在裝置晶圓的前側上；將虛擬晶圓的前側結合到所述裝置晶圓的所述前側，所述晶粒堆疊設置在所述虛擬晶圓的所述前側中的凹槽中；將所述虛擬晶圓的背側薄化，直至所述凹槽被暴露出為止，從而形成延伸穿透所述虛擬晶圓的開口；在所述開口中形成粘合劑，所述粘合劑的頂表面、所述虛擬晶圓的頂表面及所述晶粒堆疊的頂表面是齊平的；在所述裝置晶圓的背側上形成傳導性連接件；以及將所述裝置晶圓及所述虛擬晶圓同時單體化，所述裝置晶圓被單體化而形成積體電路晶粒，所述晶粒堆疊設置在所述積體電路晶粒上，所述虛擬晶圓被單體化而形成虛擬半導體特徵，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離。
在一些實施例中，所述散熱方法進一步包括：形成從所述虛擬晶圓的所述前側延伸到所述虛擬晶圓中的通孔。在一些實施例中，所述散熱方法進一步包括：在所述將所述裝置晶圓及所述虛擬晶圓單體化之前，在所述虛擬晶圓上形成虛擬金屬化層。在一些實施例中，所述散熱方法進一步包括：利用所述傳導性連接件將所述積體電路晶粒結合到封裝基板；在所述封裝基板與所述積體電路晶粒之間形成底部填充劑，所述底部填充劑環繞所述傳導性連接件及所述積體電路晶粒；以及將散熱器附裝到所述封裝基板，所述散熱器被粘附到所述虛擬半導體特徵。
在實施例中，一種散熱裝置包括：積體電路晶粒，具有第一側及與所述第一側相對的第二側；晶粒堆疊，位於所述積體電路晶粒的所述第一側上；虛擬半導體特徵，位於所述積體電路晶粒的所述第一側上，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離；第一粘合劑，設置在所述晶粒堆疊與所述虛擬半導體特徵之間；以及多個傳導性連接件，位於所述積體電路晶粒的所述第二側上。
在一些實施例中，所述虛擬半導體特徵的頂表面、所述晶粒堆疊的頂表面及所述第一粘合劑的頂表面是齊平的。在一些實施例中，所述虛擬半導體特徵橫向延伸越過所述積體電路晶粒的邊緣。在一些實施例中，所述虛擬半導體特徵的邊緣與所述積體電路晶粒的邊緣是共邊界的。在一些實施例中，所述第一粘合劑設置在所述晶粒堆疊上，且所述虛擬半導體特徵設置在所述第一粘合劑上。在一些實施例中，所述散熱裝置進一步包括：通孔，從所述積體電路晶粒的所述第一側延伸到所述虛擬半導體特徵中。在一些實施例中，所述通孔延伸穿透所述虛擬半導體特徵。在一些實施例中，所述通孔局部地延伸到所述虛擬半導體特徵中。在一些實施例中，所述散熱裝置進一步包括：封裝基板，所述傳導性連接件結合到所述封裝基板；以及支撐環，被粘附到所述封裝基板，所述支撐環環繞所述積體電路晶粒。在一些實施例中，所述散熱裝置進一步包括：封裝基板，所述傳導性連接件結合到所述封裝基板；散熱器，被粘附到所述封裝基板；以及熱介面材料，將所述散熱器粘附到所述虛擬半導體特徵。在一些實施例中，所述散熱裝置進一步包括：虛擬金屬化層，位於所述虛擬半導體特徵上，所述熱介面材料設置在所述虛擬金屬化層上。在一些實施例中，所述散熱裝置進一步包括：第二粘合劑，位於所述虛擬半導體特徵上；以及虛擬傳導性特徵，設置在所述第二粘合劑上，所述熱介面材料設置在所述第二粘合劑上且環繞所述虛擬傳導性特徵。
以上內容概述了若干實施例的特徵以使所屬領域中的技術人員可更好地理解本發明的各方面。所屬領域中的技術人員應瞭解，他們可易於使用本發明作為基礎來設計或修改其他程序及結構以施行本文所介紹實施例的相同目的及/或實現本文所介紹實施例的相同優點。所屬領域中的技術人員還應認識到，此種等效構造並不背離本發明的精神及範圍，且在不背離本發明的精神及範圍的條件下，他們可對本文作出各種改變、替代、及變更。
50‧‧‧積體電路晶粒
52‧‧‧基板
54‧‧‧裝置
56‧‧‧傳導性插塞
58‧‧‧層間介電質
60‧‧‧內連線
62‧‧‧晶粒連接件
64‧‧‧介電材料
66‧‧‧穿孔
100‧‧‧中間裝置封裝/裝置封裝
102‧‧‧裝置晶圓
102A‧‧‧裝置區
104‧‧‧晶粒堆疊
106‧‧‧傳導性連接件
108、126‧‧‧膠帶
110‧‧‧載體基板
112‧‧‧虛擬晶圓
114‧‧‧凹槽
116‧‧‧虛擬結合墊
118‧‧‧虛擬微凸塊/微凸塊
120‧‧‧可回焊材料
122‧‧‧開口
124、130、210、216‧‧‧粘合劑
128‧‧‧虛擬半導體特徵
132‧‧‧通孔
134‧‧‧虛擬金屬化層
200‧‧‧裝置封裝
202‧‧‧封裝基板
204‧‧‧結合墊
206‧‧‧底部填充劑
208A‧‧‧散熱器
208B‧‧‧支撐環
212‧‧‧熱介面材料
214‧‧‧虛擬傳導性特徵
D1、D3、D4‧‧‧深度
D2‧‧‧高度
W1、W3‧‧‧寬度
W2‧‧‧總寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A及圖1B說明裝置晶圓及積體電路晶粒的剖視圖。
圖2至圖12B是根據一些實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。
圖13至圖17B是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。
圖18至圖24B是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。
圖25至圖32是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。
圖33示出根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟。
圖34至圖37是根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟的各種視圖。
圖38示出根據一些其他實施例在用於形成裝置封裝的程序期間的中間步驟。

Claims (1)

  1. 一種散熱方法，包括： 將晶粒堆疊放置在裝置晶圓的前側上； 在所述裝置晶圓的背側上形成傳導性連接件； 將所述裝置晶圓單體化以形成積體電路晶粒，所述晶粒堆疊設置在所述積體電路晶粒上； 將所述積體電路晶粒放置在載體基板上； 將虛擬晶圓的前側結合到所述積體電路晶粒，所述晶粒堆疊設置在所述虛擬晶圓的所述前側中的凹槽中； 從所述載體基板剝離所述積體電路晶粒；以及 將所述虛擬晶圓單體化以形成虛擬半導體特徵，所述虛擬半導體特徵橫向環繞所述晶粒堆疊，所述虛擬半導體特徵與所述晶粒堆疊及所述積體電路晶粒電性隔離。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI741388B (zh) * 2019-07-29 2021-10-01 台灣積體電路製造股份有限公司 半導體封裝體及其製造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269682B2 (en) * 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
US10515867B2 (en) * 2017-11-14 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10312221B1 (en) 2017-12-17 2019-06-04 Advanced Micro Devices, Inc. Stacked dies and dummy components for improved thermal performance
US10573630B2 (en) * 2018-04-20 2020-02-25 Advanced Micro Devices, Inc. Offset-aligned three-dimensional integrated circuit
US11493713B1 (en) 2018-09-19 2022-11-08 Psiquantum, Corp. Photonic quantum computer assembly having dies with specific contact configuration and matched CTE
KR102619532B1 (ko) 2019-05-21 2024-01-02 삼성전자주식회사 반도체 패키지
US11621211B2 (en) * 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US20210280507A1 (en) * 2020-03-05 2021-09-09 Qualcomm Incorporated Package comprising dummy interconnects
TWI755281B (zh) 2021-02-18 2022-02-11 創意電子股份有限公司 散熱結構、半導體封裝裝置及半導體封裝裝置之製造方法
US20230116326A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Semiconductor package with tsv die
US20230136202A1 (en) * 2021-11-01 2023-05-04 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
WO2023091430A1 (en) * 2021-11-17 2023-05-25 Adeia Semiconductor Bonding Technologies Inc. Thermal bypass for stacked dies
US20230197563A1 (en) * 2021-12-17 2023-06-22 Advanced Micro Devices, Inc. Semiconductor chip device integrating thermal pipes in three-dimensional packaging
WO2024097375A2 (en) * 2022-11-03 2024-05-10 Board Of Regents, The University Of Texas System Tim-free heat spreader

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US8330262B2 (en) * 2010-02-02 2012-12-11 International Business Machines Corporation Processes for enhanced 3D integration and structures generated using the same
US10297550B2 (en) * 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8378480B2 (en) * 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI741388B (zh) * 2019-07-29 2021-10-01 台灣積體電路製造股份有限公司 半導體封裝體及其製造方法
US11728238B2 (en) 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof

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