CN109216208A - 散热方法 - Google Patents

散热方法 Download PDF

Info

Publication number
CN109216208A
CN109216208A CN201711401935.0A CN201711401935A CN109216208A CN 109216208 A CN109216208 A CN 109216208A CN 201711401935 A CN201711401935 A CN 201711401935A CN 109216208 A CN109216208 A CN 109216208A
Authority
CN
China
Prior art keywords
die
integrated circuit
dummy
stack
circuit die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711401935.0A
Other languages
English (en)
Inventor
余振华
陈明发
陈琮瑜
洪文兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109216208A publication Critical patent/CN109216208A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06519—Bonding areas having different functions including bonding areas providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1712—Layout
    • H01L2224/1715—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/17154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/17155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种散热装置包括：集成电路管芯，具有第一侧及与所述第一侧相对的第二侧；管芯堆叠，位于所述集成电路管芯的所述第一侧上；虚拟半导体特征，位于所述集成电路管芯的所述第一侧上，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离；第一粘合剂，设置在所述管芯堆叠与所述虚拟半导体特征之间；以及多个传导性连接件，位于所述集成电路管芯的所述第二侧上。

Description

散热方法
优先权声明及交叉参考
本申请主张在2017年6月30日提出申请的美国临时专利申请第62/527,770号的权利，所述美国临时专利申请的全文并入本文中供参考。
技术领域
本揭露的实施例是有关于一种散热方法。
背景技术
在对集成电路进行封装时，多个半导体管芯可通过结合被堆叠，且可结合到例如中介物(interposer)及封装衬底等的其他封装组件。所得的封装被称为三维集成电路(Three-Dimensional Integrated Circuit，3DIC)。在三维集成电路中，热量耗散是一项挑战。
在有效地耗散在三维集成电路的内管芯中产生的热量方面，可能存在瓶颈。在典型的三维集成电路中，在内管芯中产生的热量可必须被耗散到外组件后，所述热量才能被传导到散热器。然而，在经堆叠管芯与外组件之间，存在不能有效地传导热量的其他材料，例如底部填充剂、模塑化合物等。因此，热量可能被陷滞在底部经堆叠管芯的内区中，且因此引起尖锐的局部温度峰值(有时被称为热点(hot spot))。此外，因由高功率消耗管芯产生的热量所致的热点可对周围管芯引起热串扰(thermal crosstalk)问题，从而负面地影响周围管芯的性能及整个三维集成电路封装的可靠性。
发明内容
本揭露公开一种散热方法，其特征在于，包括：将管芯堆叠放置在装置晶片的前侧上；在所述装置晶片的背侧上形成传导性连接件；将所述装置晶片单体化以形成集成电路管芯，所述管芯堆叠设置在所述集成电路管芯上；将所述集成电路管芯放置在载体衬底上；将虚拟晶片的前侧结合到所述集成电路管芯，所述管芯堆叠设置在所述虚拟晶片的所述前侧中的凹槽中；从所述载体衬底剥离所述集成电路管芯；以及将所述虚拟晶片单体化以形成虚拟半导体特征，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离。
附图说明
结合附图阅读以下详细说明，会最佳地理解本发明的各方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A及图1B说明装置晶片及集成电路管芯的剖视图。
图2至图12B是根据一些实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。
图13至图17B是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。
图18至图24B是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。
图25至图32是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。
图33示出根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤。
图34至图37是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。
图38示出根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤。
附图标号说明
50：集成电路管芯
52：衬底
54：装置
56：传导性插塞
58：层间介电质
60：互连线
62：管芯连接件
64：介电材料
66：穿孔
100：中间装置封装/装置封装
102：装置晶片
102A：装置区
104：管芯堆叠
106：传导性连接件
108、126：胶带
110：载体衬底
112：虚拟晶片
114：凹槽
116：虚拟结合垫
118：虚拟微凸块/微凸块
120：可回焊材料
122：开口
124、130、210、216：粘合剂
128：虚拟半导体特征
132：通孔
134：虚拟金属化层
200：装置封装
202：封装衬底
204：结合垫
206：底部填充剂
208A：散热器
208B：支撑环
212：热界面材料
214：虚拟传导性特征
D1、D3、D4：深度
D2：高度
W1、W3：宽度
W2：总宽度
具体实施方式
以下公开内容提供用于实作本揭露的不同特征的许多不同的实施例或实例。以下阐述组件及构造的具体实例以简化本揭露内容。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有额外特征、从而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...下方(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所说明的一个元件或特征与另一(些)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
根据一些实施例，形成一种装置封装，其具有位于集成电路管芯上的管芯堆叠以及位于所述集成电路管芯上且环绕所述管芯堆叠的虚拟半导体特征。所述虚拟半导体特征与所述集成电路管芯及所述管芯堆叠电性隔离。所述虚拟半导体特征由具有高导热性的材料形成，且有助于避免在所述集成电路管芯与所述管芯堆叠的界面处(例如，在所述管芯堆叠的底部管芯中)发生热量积聚。避免热量积聚可改善装置封装的可靠性及电气性能。
图1A及图1B分别说明装置晶片102及在装置晶片102中形成的集成电路管芯50的剖视图。具体来说，集成电路管芯50可为在装置晶片102中形成的中介物、逻辑装置等，装置晶片102可包括不同的装置区102A，所述不同的装置区102A在后续步骤中被单体化以形成多个集成电路管芯50。集成电路管芯50包括衬底52、装置54、传导性插塞56、层间介电质(inter-layer dielectric，ILD)58、互连线60、管芯连接件62、介电材料64、及穿孔66。在一些实施例中，集成电路管芯50是逻辑装置等。在一些实施例中，集成电路管芯50是中介物等。
衬底52具有：前表面(例如，在图1A及图1B中面向上的表面)，有时被称为有源侧；以及后表面(例如，在图1A及图1B中面向下的表面)，有时被称为非有源侧。衬底52是装置晶片102的被单体化出的一部分(例如，来自装置区102A中的一者，以下进一步论述)。衬底52可为经掺杂或未经掺杂的半导体(例如硅)，或者可为绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。衬底52可包含其他半导体材料，例如：锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其组合。也可使用其他衬底，例如多层式衬底或梯度式衬底。
装置54可形成在衬底52的前侧中及/或衬底52的前侧上。装置54可为晶体管、二极管、电容器、电阻器等。在其中集成电路管芯50是逻辑管芯的实施例中，装置54包括有源装置。在其中集成电路管芯50是中介物的实施例中，装置54可为无源装置或可被省略，使得集成电路管芯50不含有源装置。传导性插塞56电性且实体地耦合到装置54。层间介电质58环绕装置54及传导性插塞56。
互连线60对装置54进行内连，以形成集成电路。互连线60可例如由位于衬底52的前侧上的介电层中的金属化图案形成。所述金属化图案包括在一个或多个介电层中形成的金属线及通孔。互连线60的金属化图案通过传导性插塞56电性耦合到装置54。
管芯连接件62可为传导性柱(例如，包含例如铜、铝、钨、镍或其合金等的金属)，且机械及电性耦合到互连线60。管芯连接件62可通过例如镀覆等形成。管芯连接件62对集成电路管芯50的相应集成电路进行电性耦合。
介电材料64位于集成电路管芯50的有源侧上，例如位于互连线60上。介电材料64横向包封管芯连接件62，且介电材料64与集成电路管芯50是横向共边界的。介电材料64是含硅介电层，并且可由氧化硅、SiON、SiN等形成，且可通过沉积工艺(例如化学气相沉积(chemical vapor deposition，CVD)、等离子增强化学气相沉积(plasma enhancedchemical vapordeposition，PECVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)等)来形成。介电材料64可为互连线60的最顶层。
穿孔66形成在半导体衬底中，且可为例如硅穿孔(through silicon via，TSV)。可通过施加适合的光刻胶并将其显影且随后蚀刻衬底52以产生硅穿孔开口来形成穿孔66。可给所述硅穿孔开口填充例如衬里(图中未示出)、障壁层(图中也未示出)及传导性材料。在实施例中，所述衬里可为介电材料(例如氮化硅、氧化硅、介电聚合物、这些材料的组合等)，且可通过例如化学气相沉积、氧化、物理气相沉积、原子层沉积等的工艺来形成。所述障壁层可包含例如氮化钛等的传导性材料，但作为另一选择，可利用例如氮化钽、钛、另一介电质等的其他材料。可使用化学气相沉积工艺(例如等离子增强化学气相沉积)来形成所述障壁层。然而，作为另一选择，可使用其他替代性工艺，例如溅镀、金属有机化学气相沉积(metal organicchemical vapor deposition，MOCVD)、或原子层沉积(ALD)。所述障壁层可被形成为覆形于硅穿孔开口的基本形状。所述传导性材料可为铜、铝、钨、合金、经掺杂多晶硅、其组合等。可通过沉积晶种层且随后将铜电镀到所述晶种层上、从而填充及过填充硅穿孔开口来形成所述传导性材料。一旦硅穿孔开口已被填充，便可通过例如化学机械抛光(chemical-mechanical polish，CMP)等的研磨工艺来移除硅穿孔开口以外的多余障壁层及多余传导性材料，但可使用任意适合的移除工艺。
图2至图12B是根据一些实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。图2至图12B是剖视图。在图2至图11中，通过将各种组件结合到装置晶片102来形成装置封装100。在实施例中，装置封装100是晶片上芯片(chip-on-wafer，CoW)封装，但应了解，各实施例可应用于其他三维集成电路封装。在图12A及图12B中，通过将装置封装100安装到衬底来形成装置封装200。在实施例中，装置封装200是衬底上晶片上芯片(chip-on-wafer-on-substrate，CoWoS)封装，但应了解，各实施例可应用于其他三维集成电路封装。图12A及图12B示出不同的实施例。
在图2中，在装置晶片102上形成有集成电路管芯50之后，将管芯堆叠104结合到装置晶片102的前侧。管芯堆叠104是在装置晶片102被单体化之前结合在每一装置区102A中。管芯堆叠104可为包括多个经堆叠及经内连存储器管芯的高带宽存储器(high bandwidthmemory，HBM)模块或混合存储器立方体(hybrid memory cube，HMC)模块。所述存储器管芯可为动态随机存取存储器(dynamic random access memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯等。管芯堆叠104的各层级可利用例如硅穿孔(TSV)、微凸块等的传导性特征(图中未示出)被内连。管芯堆叠104可通过例如混合键结(hybrid bonding)、熔融键结(fusion bonding)、焊接接合(solder joint)(例如，微凸块)等而结合到装置晶片102。
在其中装置晶片102中形成有例如逻辑装置等的集成电路装置的实施例中，在操作期间，热量可被陷滞在管芯堆叠104下方。逻辑装置可占每一装置封装100的功率消耗的一大部分；例如，逻辑装置可占每一装置封装100的功率消耗的高达90％。此外，管芯堆叠104可具有高功率密度。在其中管芯堆叠104是经堆叠静态随机存取存储器管芯的实施例中，管芯堆叠104可具有从50瓦(watt，W)/cm2至300W/cm2的功率密度。管芯堆叠104的高功率密度与装置晶片102的高功率消耗的组合可抑制从装置晶片102经由管芯堆叠104进行热量耗散。此可使热量被陷滞在管芯堆叠104中的最底管芯处，因为来自最底管芯的热量必须传播最远的距离(例如，穿过管芯堆叠104)。因此，热量可积聚在装置封装100中，而使装置封装100超过标称操作温度，从而使装置封装100的可靠性及电气性能降级。
在图3中，在装置晶片102的背侧上形成传导性连接件106。可在形成传导性连接件106之前将装置晶片102的背侧薄化。可通过化学机械抛光(CMP)工艺、研磨工艺等来实现所述薄化。传导性连接件106电性连接到装置晶片102的特征(例如，逻辑装置、中介物等)，且可为球栅阵列(ballgrid array，BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlledcollapse chip connection，C4)凸块、微凸块、由无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。在一些实施例中，通过首先通过例如蒸镀、电镀、印刷、焊料转移、植球等常用的方法形成一层焊料来形成传导性连接件106。一旦已在结构上形成一层焊料，便可执行回焊以将材料成形为所需的凸块形状。
在图4中，通过单体化工艺将装置晶片102(例如，参见图3)单体化成多个集成电路管芯50，以形成中间装置封装100。经单体化集成电路管芯50中的每一者结合到对应的管芯堆叠104。可通过将装置晶片102放置在胶带108上并沿例如位于装置晶片102的相邻装置区102A之间的切割道区进行锯切来实现所述单体化。在一些实施例中，所述单体化工艺包括锯切工艺、激光工艺或其组合。所述单体化工艺会将各封装区中的每一者与相邻的封装区单体化开。
在图5中，将包括集成电路管芯50及管芯堆叠104的中间装置封装100放置在载体衬底110上。载体衬底110可为玻璃载体衬底、陶瓷载体衬底等。载体衬底110也可为晶片等。
在图6中，制备虚拟晶片112。虚拟晶片112由半导体材料形成，且可为半导体衬底。所述半导体衬底可为块状半导体(bulk semiconductor)、绝缘体上半导体(SOI)衬底等，其可被掺杂(例如，以p型掺杂剂或n型掺杂剂)或未被掺杂。半导体材料在制作工艺中易于获得，且具有良好的导热性。举例来说，硅具有从120W·m-1·K-1至150W·m-1·K-1的导热性，从而使其成为良好的热量导体。在虚拟晶片112的前侧中图案化有凹槽114。凹槽114的图案对应于载体衬底110上的中间装置封装100的图案。凹槽114具有比集成电路管芯50的总宽度W2小且比管芯堆叠104的宽度W3大的宽度W1。凹槽114具有比管芯堆叠104的高度D2大的深度D1。可通过蚀刻工艺(例如适合的干蚀刻或湿蚀刻)来图案化出凹槽114。在实施例中，在虚拟晶片112上形成光刻胶材料并将所述光刻胶材料暴露于光，从而在所述光刻胶材料中形成与凹槽114的图案对应的图案。随后，可使用经图案化光刻胶作为蚀刻掩模来在虚拟晶片112中蚀刻凹槽114。在实施例中，虚拟晶片112不具有电功能，且不含有源装置及无源装置。
在图7A至图7C中，将虚拟晶片112的前侧放置在中间装置封装100上。图7A至图7C示出不同的实施例，且针对图7A所示实施例来说明后续处理步骤。由于管芯堆叠104、集成电路管芯50及凹槽114的相对宽度，管芯堆叠104被设置在凹槽114中，且集成电路管芯50接触虚拟晶片112。虚拟晶片112结合到每一中间装置封装100的集成电路管芯50。如上所述，虚拟晶片112可不具有电功能。此外，在虚拟晶片112与集成电路管芯50的界面处未形成有电结面(例如，p-n结面、金属-半导体结面等)。因此，虚拟晶片112可与管芯堆叠104的及集成电路管芯50的有源装置(例如，装置54)、以及其他周围装置电性隔离。虚拟晶片112可通过例如熔融键结、混合键结、微凸块等而结合到集成电路管芯50。
在其中虚拟晶片112是通过熔融键结而结合到集成电路管芯50的实施例(例如，图7A)中，使用氧化物层(例如介电材料64等)在虚拟晶片112与中间装置封装100之间形成共价键。在此类实施例中，介电材料64的与虚拟晶片112接触的部分可实质上不含管芯连接件62；例如，管芯连接件62可仅设置在管芯堆叠104下方。虚拟晶片112与中间装置封装100之间的界面可为硅-硅共价键结机制、硅-氧化物共价键结机制、氧化物-氧化物共价键结机制、或任何其他共价键结机制。可对集成电路管芯50及/或虚拟晶片112执行表面处理，从而在介电材料64的及/或虚拟晶片112的顶部中形成OH键。随后，将虚拟晶片112对准在中间装置封装100之上并压靠集成电路管芯50，以与介电材料64形成键。在压在一起之后，可将中间装置封装100及虚拟晶片112退火，以强化所述键。在退火期间，介电材料64的及/或虚拟晶片112的顶部中的OH键断裂，以在集成电路管芯50(例如，互连线60)与虚拟晶片112之间形成Si-O-Si键，从而强化集成电路管芯50与虚拟晶片112之间的键。
在其中虚拟晶片112是通过混合键结而结合到集成电路管芯50的实施例(例如，图7B)中，在虚拟晶片112中形成虚拟结合垫116。在此类实施例中，未设置在管芯堆叠104下方的管芯连接件62可为与集成电路管芯50的装置54电性隔离的虚拟结合垫；例如，只有设置在管芯堆叠104下方的管芯连接件62才可电性连接到装置54。如上所述，可执行表面处理。将中间装置封装100与虚拟晶片112对准(包括虚拟结合垫116与管芯连接件62)且彼此压靠，以形成弱键。如上所述，可执行退火工艺，以强化集成电路管芯50的介电特征及金属特征与虚拟晶片112之间的键。
在其中虚拟晶片112是通过微凸块而结合到集成电路管芯50的实施例(例如，图7C)中，可在集成电路管芯50上及虚拟晶片112的前侧上形成虚拟微凸块118。虚拟微凸块118可与集成电路管芯50的装置54电性隔离。当将虚拟晶片112放置在中间装置封装100上时，可将各虚拟微凸块118对准。随后，可使用可回焊材料120(例如焊料)将虚拟晶片112的微凸块118结合到集成电路管芯50的微凸块118。
在图8中，通过平面化工艺将虚拟晶片112薄化。所述平面化工艺可例如是化学机械抛光工艺、研磨工艺等。对虚拟晶片112的背侧执行所述平面化工艺，直至凹槽114延伸穿透虚拟晶片112为止，从而形成开口122。管芯堆叠104设置在开口122中。在所示实施例中，所述平面化工艺是在形成开口122之后停止，且开口122的深度D3大于管芯堆叠104的高度D2。在其他实施例中，在执行平面化工艺之后，虚拟晶片112的背侧与管芯堆叠104的顶表面齐平。
在图9中，在开口122中形成粘合剂124。粘合剂124可为模塑化合物、环氧树脂等，且可通过压缩模塑(compression molding)、转移模塑(transfermolding)、射出模塑(injection molding)等来施加。在开口122中形成粘合剂124，且可能会在管芯堆叠104及/或虚拟晶片112之上形成多余的量。随后，使粘合剂124固化。可执行可选的平面化工艺，以移除管芯堆叠104及/或虚拟晶片112之上的多余粘合剂124。在平面化之后，粘合剂124的顶表面、管芯堆叠104的顶表面及虚拟晶片112的顶表面是齐平的。
在图10中，执行载体衬底剥离，以从中间装置封装100拆离(剥离)载体衬底110。随后，通过单体化工艺将虚拟晶片112单体化，从而形成虚拟半导体特征128。可通过将虚拟晶片112及装置封装100放置在胶带126上并沿例如位于装置封装100中的相邻者之间的切割道区进行锯切来实现所述单体化。在一些实施例中，所述单体化工艺包括锯切工艺、激光工艺或其组合。经单体化封装是最终的装置封装100。
图11示出所得的经单体化装置封装100。在每一装置封装100中，虚拟半导体特征128环绕管芯堆叠104并接触集成电路管芯50。虚拟半导体特征128的边缘横向延伸越过集成电路管芯50的边缘。换句话说，虚拟半导体特征128的外侧壁具有比集成电路管芯50的宽度大的宽度。虚拟半导体特征128接触集成电路管芯50的顶表面的未被管芯堆叠104及粘合剂124覆盖的部分。在实施例中，虚拟半导体特征128接触集成电路管芯50的顶表面面积的至少大部分(例如，多于50％)。
如上所述，集成电路管芯50可为逻辑装置，且可占每一装置封装100的功率消耗的高达90％。因此，集成电路管芯50可占由每一装置封装100产生的热量的高达90％。此外，虚拟半导体特征128由为良好热量导体的半导体材料形成。由于虚拟半导体特征128接触集成电路管芯50的顶表面的至少大部分，因而虚拟半导体特征128可有助于移除由集成电路管芯50产生的热量中的某些热量。此可有助于防止热量被陷滞在管芯堆叠104下方，从而降低装置封装100的操作温度并改善装置封装100的可靠性及电气性能。
在图12A及图12B中，通过将装置封装100安装到封装衬底202来形成装置封装200。封装衬底202可由例如硅、锗、金刚石等的半导体材料形成。作为另一选择，也可使用例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些材料的组合等的化合物材料。另外，封装衬底202可为绝缘体上半导体衬底。一般来说，绝缘体上半导体衬底包含一层半导体材料，例如外延硅、锗、硅锗、绝缘体上硅(silicon-on-insulator，SOI)、绝缘体上硅锗(silicon germanium-on-insulator，SGOI)、或其组合。在一个替代性实施例中，封装衬底202是基于绝缘芯(例如玻璃纤维强化树脂芯)。一种示例性芯材料是玻璃纤维树脂，例如FR4。芯材料的替代方案包括双马来酰亚胺三嗪(bismaleimide-triazine，BT)树脂，或作为另一选择，包括其他印刷电路板(printed circuit board，PCB)材料或膜。可将例如味之素增层膜(Ajinomoto Build-up Film，ABF)等的增层膜或其他积层用于封装衬底202。
封装衬底202可包括有源装置及无源装置(图中未示出)。如所属领域中的普通技术人员将认识到，可使用各种各样的装置(例如晶体管、电容器、电阻器、这些装置的组合等)来产生装置封装200的设计的结构性及功能性要求。可使用任意适合的方法来形成所述装置。
封装衬底202还可包括金属化层及通孔(图中未示出)以及位于所述金属化层及通孔之上的结合垫204。所述金属化层可形成在有源装置及无源装置之上且被设计成将各种装置连接以形成功能性电路系统。所述金属化层可由交替的介电材料(例如，低介电常数介电材料)层及传导性材料(例如，铜)层形成(其中通孔将各传导性材料层内连)，且可通过任意适合的工艺(例如沉积、镶嵌、双重镶嵌等)来形成。在一些实施例中，封装衬底202实质上不含有源装置及无源装置。
在一些实施例中，对传导性连接件106进行回焊，以将装置封装100附装到结合垫204，从而将集成电路管芯50结合到封装衬底202。传导性连接件106将封装衬底202(包括封装衬底202中的金属化层)电性及/或实体地耦合到装置封装100。在一些实施例中，在安装在封装衬底202上之前，可将无源装置(例如，表面安装装置(surface mount device，SMD)，图中未说明)附装到装置封装100(例如，被结合到结合垫204)。在此类实施例中，所述无源装置可与传导性连接件106结合到装置封装100的同一表面。
传导性连接件106可在其被回焊之前上面先形成有环氧树脂助焊剂(图中未示出)，其中在装置封装100附装到封装衬底202之后，所述环氧树脂助焊剂中的环氧树脂部分中的至少某些存留下来。此种存留的环氧树脂部分可充当底部填充剂，以降低应力并保护因对传导性连接件106进行回焊而产生的接点。
可在装置封装100与封装衬底202之间形成环绕传导性连接件106及集成电路管芯50的底部填充剂206。底部填充剂206可在装置封装100被附装之后通过毛细管流动工艺(capillary flow process)而形成，或者可在装置封装100被附装之前通过适合的沉积方法而形成。
在图12A所示实施例中，将散热器208A附装到装置封装200。散热器208A可由具有高导热性的材料(例如钢、不锈钢、铜等、或其组合)形成。在一些实施例(以下论述)中，散热器208A涂布有另一金属(例如金)。散热器208A覆盖并环绕装置封装100。在一些实施例中，散热器208A是单一连续的材料。在一些实施例中，散热器208A包括可为相同材料或不同材料的多个片块。
散热器208A通过粘合剂210附装到封装衬底202。粘合剂210可为环氧树脂、胶等，且也可为导热性材料。散热器208A还通过热界面材料(thermal interface material，TIM)212附装到装置封装100。热界面材料212可为聚合物材料、焊料膏、铟焊料膏等，且可在散热器208A附装到装置封装200之前被施配在管芯堆叠104、粘合剂124及虚拟半导体特征128上。热界面材料212将装置封装100与散热器208A热耦合。
在图12B所示实施例中，将支撑环208B附装到装置封装200。在一些实施例中，支撑环208B可由具有高导热性的材料(例如钢、不锈钢、铜等、或其组合)形成。支撑环208B为装置封装200提供机械加强，且可防止装置封装200发生翘曲。支撑环208B通过粘合剂210附装到封装衬底202。
图13至图17B是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。图13至图17B是剖视图。
在图13中，在装置封装100被放置在载体衬底110上之后，在管芯堆叠104上形成粘合剂130。粘合剂130可为热界面材料(类似于热界面材料212)、管芯贴合膜(die attachfilm，DAF)等、或其组合。
在图14中，将虚拟晶片112放置在装置封装100上。在放置之后，管芯堆叠104及粘合剂130被设置在凹槽114中。放置虚拟晶片112会使粘合剂130摊铺开，使得粘合剂130填充凹槽114。具体来说，粘合剂130填充管芯堆叠104的各侧与虚拟晶片112的界定凹槽114的各侧之间的空隙。虚拟晶片112可以与以上针对图7A至图7C所论述的方式类似的方式结合到装置封装100。
在图15中，执行载体衬底剥离以从装置封装100拆离(剥离)载体衬底110。随后，通过单体化工艺将虚拟晶片112单体化，从而形成虚拟半导体特征128及装置封装100。由于凹槽114中形成有粘合剂130，因而不形成粘合剂124，且可省略各种平面化步骤。
图16示出所得的经单体化装置封装100。由于可省略平面化步骤，因而虚拟半导体特征128覆盖管芯堆叠104。此外，虚拟半导体特征128的边缘横向延伸越过集成电路管芯50的边缘。
在图17A及图17B中，通过将装置封装100安装到封装衬底202来形成装置封装200。在一些实施例中，对传导性连接件106进行回焊，以将装置封装100附装到封装衬底202的结合垫204。可在装置封装100与封装衬底202之间形成环绕传导性连接件106及集成电路管芯50的底部填充剂206。
在图17A所示实施例中，将散热器208A附装到装置封装200。使用粘合剂210将散热器208A粘附到封装衬底202。可在虚拟半导体特征128上施配热界面材料212，从而将装置封装100与散热器208A热耦合。
在图17B所示实施例中，将支撑环208B附装到装置封装200。使用粘合剂210将支撑环208B粘附到封装衬底202。支撑环208B为装置封装200提供机械加强，且可防止装置封装200发生翘曲。
图18至图24B是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。图18至图24B是剖视图。
在图18中，在装置晶片102被单体化成多个集成电路管芯50之前，将虚拟晶片112放置在装置晶片102上。管芯堆叠104被设置在虚拟晶片112的凹槽114中。虚拟晶片112的前侧结合到装置晶片102。虚拟晶片112可以与以上针对图7A至图7C所论述的方式类似的方式结合到装置晶片102。
在图19中，通过平面化工艺将虚拟晶片112薄化。对虚拟晶片112的背侧执行所述平面化工艺，直至凹槽114延伸穿透虚拟晶片112为止，从而形成开口122。
在图20中，在开口122中形成粘合剂124。可执行可选的平面化工艺，以移除管芯堆叠104及/或虚拟晶片112之上的多余粘合剂124。在平面化之后，粘合剂124的顶表面、管芯堆叠104的顶表面及虚拟晶片112的顶表面是齐平的。
在图21中，在装置晶片102的背侧上形成传导性连接件106。传导性连接件106电性连接到装置晶片102的特征。在形成传导性连接件106之前，可将装置晶片102的背侧薄化。
在图22中，通过单体化工艺将装置晶片102及虚拟晶片112同时单体化，从而形成多个集成电路管芯50及多个虚拟半导体特征128。可通过将装置晶片102放置在胶带126上并沿例如位于装置晶片102的相邻封装区之间的切割道区进行锯切来实现所述单体化。在一些实施例中，所述单体化工艺包括锯切工艺、激光工艺或其组合。
图23示出所得的经单体化装置封装100。由于装置晶片102及虚拟半导体特征128被同时单体化，因而虚拟半导体特征128的边缘与集成电路管芯50的边缘是横向共边界的。换句话说，虚拟半导体特征128的外侧壁具有与集成电路管芯50的外侧壁相同的宽度。
在图24A及图24B中，通过将装置封装100安装到封装衬底202来形成装置封装200。在一些实施例中，对传导性连接件106进行回焊，以将装置封装100附装到封装衬底202的结合垫204。可在装置封装100与封装衬底202之间形成环绕传导性连接件106的底部填充剂206。由于集成电路管芯50与虚拟半导体特征128为相同的宽度，因而底部填充剂206不环绕集成电路管芯50。
在图24A所示实施例中，将散热器208A附装到装置封装200。使用粘合剂210将散热器208A粘附到封装衬底202。可在管芯堆叠104、粘合剂124及虚拟半导体特征128上施配热界面材料212，从而将装置封装100与散热器208A热耦合。
在图24B所示实施例中，将支撑环208B附装到装置封装200。使用粘合剂210将支撑环208B粘附到封装衬底202。支撑环208B为装置封装200提供机械加强，且可防止装置封装200发生翘曲。
图25至图32是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。图25至图32是剖视图。在图25至图32所示实施例中，在虚拟晶片112中形成通孔132。通孔132的材料具有比虚拟晶片112的材料高的导热性，从而进一步改善虚拟晶片112的导热性。虽然是在图18至图24B所示实施例中说明形成通孔132，但应了解，可针对其中散热器208A附装到装置封装200的任何实施例在虚拟晶片112中形成通孔132。
在图25中，制备虚拟晶片112。在虚拟晶片112中形成通孔132。通孔132是从虚拟晶片112的前侧至少局部地向虚拟晶片112中延伸深度D4的硅穿孔(TSVs)。深度D4可小于凹槽114的深度D1，或者可等于或大于深度D1。
可通过向虚拟晶片112的前侧施加适合的光刻胶并将所述光刻胶显影且随后蚀刻虚拟晶片112以产生硅穿孔开口来形成通孔132。可给所述硅穿孔开口填充例如衬里(图中未示出)、障壁层(图中也未示出)及传导性材料。在实施例中，所述衬里可为介电材料(例如氮化硅、氧化硅、介电聚合物、这些材料的组合等)，且可通过例如化学气相沉积、氧化、物理气相沉积、原子层沉积等的工艺来形成。所述障壁层可包含例如氮化钛等的传导性材料，但作为另一选择，可利用例如氮化钽、钛、另一介电质等的其他材料。可使用化学气相沉积工艺(例如等离子增强化学气相沉积)来形成所述障壁层。然而，作为另一选择，可使用其他替代性工艺，例如溅镀、金属有机化学气相沉积(MOCVD)、或原子层沉积(ALD)。所述障壁层可被形成为覆形于硅穿孔开口的基本形状。所述传导性材料可为具有比虚拟晶片112的半导体材料高的导热性的金属。在实施例中，所述传导性材料包含铜，但作为另一选择，可利用例如铝、钨、合金、经掺杂多晶硅、其组合等其他适合的材料。可通过沉积晶种层且随后将铜电镀到所述晶种层上、从而填充及过填充硅穿孔开口来形成所述传导性材料。一旦硅穿孔开口已被填充，便可通过例如化学机械抛光等的研磨工艺来移除硅穿孔开口以外(例如，在虚拟晶片112的前侧上)的多余障壁层及多余传导性材料，但可使用任意适合的移除工艺。
在图26中，将虚拟晶片112翻转并放置在装置封装100上。管芯堆叠104被设置在凹槽114中，且集成电路管芯50接触虚拟晶片112。虚拟晶片112可以与以上针对图7A至图7C所论述的方式类似的方式结合到装置晶片102。在其中使用混合键结的实施例中，通孔132耦合到集成电路管芯50的金属特征(例如，管芯连接件62)。在此类实施例中，未设置在管芯堆叠104下方的管芯连接件62可为与集成电路管芯50的装置54电性隔离的虚拟结合垫；例如，只有设置在管芯堆叠104下方的管芯连接件62才可耦合到通孔132。
在图27中，通过平面化工艺将虚拟晶片112薄化。对虚拟晶片112的背侧执行所述平面化工艺，直至凹槽114延伸穿透虚拟晶片112为止，从而形成开口122。
在图28中，在开口122中形成粘合剂124。可执行可选的平面化工艺，以移除管芯堆叠104及/或虚拟晶片112之上的多余粘合剂124。在平面化之后，粘合剂124的顶表面、管芯堆叠104的顶表面及虚拟晶片112的顶表面是齐平的。
在图29中，在装置晶片102的背侧上形成传导性连接件106。传导性连接件106电性连接到装置晶片102的特征。在形成传导性连接件106之前，可将装置晶片102的背侧薄化。
在图30中，通过单体化工艺将装置晶片102及虚拟晶片112同时单体化，从而形成集成电路管芯50及虚拟半导体特征128。可通过将装置晶片102放置在胶带126上并沿例如位于装置晶片102的相邻封装区之间的切割道区进行锯切来实现所述单体化。
图31示出所得的经单体化装置封装100。由于装置晶片102及虚拟半导体特征128被同时单体化，因而虚拟半导体特征128的边缘与集成电路管芯50的边缘是横向共边界的。换句话说，虚拟半导体特征128的外侧壁具有与集成电路管芯50的外侧壁相同的宽度。在所示实施例中，在所得的装置封装100中，通孔132的深度D4大于或等于凹槽114的深度D1，且通孔132从虚拟半导体特征128的前侧延伸到背侧。通孔132的更大深度可改善虚拟半导体特征128的导热性。
在图32中，通过将装置封装100安装到封装衬底202来形成装置封装200。在一些实施例中，对传导性连接件106进行回焊，以将装置封装100附装到封装衬底202的结合垫204。可在装置封装100与封装衬底202之间形成环绕传导性连接件106的底部填充剂206。由于集成电路管芯50与虚拟半导体特征128为相同的宽度，因而底部填充剂206不环绕集成电路管芯50。
此外，在图32中，将散热器208A附装到装置封装200。使用粘合剂210将散热器208A粘附到封装衬底202。可在管芯堆叠104、粘合剂124及虚拟半导体特征128上施配热界面材料212，从而将装置封装100与散热器208A热耦合。
图33示出根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤。图33是剖视图。图33所示实施例类似于图32所示实施例，只不过通孔132的深度D4小于凹槽114的深度D1。因此，通孔132局部地延伸到虚拟半导体特征128中。将通孔132形成为更浅的深度可降低制造成本。
图34至图37是根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤的各种视图。图34至图37是剖视图。在图34至图37所示实施例中，在装置封装100被单体化之前，在装置封装100上形成虚拟金属化层134。虚拟金属化层134改善装置封装100与散热器208A之间的热耦合。虽然是在图18至图24B所示实施例中说明形成虚拟金属化层134，但应了解，可针对其中散热器208A附装到装置封装200的任何实施例形成虚拟金属化层134。
在图34中，在管芯堆叠104、虚拟晶片112及粘合剂124上形成虚拟金属化层134。虚拟金属化层134是在形成粘合剂124之后形成。虚拟金属化层134可由具有比虚拟晶片112的半导体材料高的导热性的传导性材料或金属(例如金、铟、铜等)形成。可通过沉积晶种层且随后将传导性材料电镀到所述晶种层上来形成虚拟金属化层134。虚拟金属化层134可与管芯堆叠104、集成电路管芯50及其他周围装置电性隔离。
在图35中，通过单体化工艺将装置晶片102、虚拟晶片112及虚拟金属化层134同时单体化，从而形成集成电路管芯50及虚拟半导体特征128。可通过将装置晶片102放置在胶带126上并沿例如位于装置晶片102的相邻封装区之间的切割道区进行锯切来实现所述单体化。
图36示出所得的经单体化装置封装100。由于装置晶片102、虚拟晶片112及虚拟金属化层134被同时单体化，因而虚拟半导体特征128的边缘与集成电路管芯50的边缘及虚拟金属化层134的边缘是横向共边界的。换句话说，虚拟半导体特征128的外侧壁具有与集成电路管芯50的外侧壁及虚拟金属化层134的外侧壁相同的宽度。
在图37中，通过将装置封装100安装到封装衬底202来形成装置封装200。在一些实施例中，对传导性连接件106进行回焊，以将装置封装100附装到封装衬底202的结合垫204。可在装置封装100与封装衬底202之间形成环绕传导性连接件106的底部填充剂206。由于集成电路管芯50与虚拟半导体特征128为相同的宽度，因而底部填充剂206不环绕集成电路管芯50。
此外，在图37中，将散热器208A附装到装置封装200。在虚拟金属化层134上施配热界面材料212。在图34至图37所示实施例中，热界面材料212是金属性热界面材料，例如焊料膏、铟焊料膏等。使用粘合剂210将散热器208A粘附到封装衬底202。可在虚拟金属化层134上施配热界面材料212，从而将装置封装100与散热器208A热耦合。在所示实施例中，散热器208A可具有金涂层，且热界面材料212可被回焊，从而与所述金涂层及虚拟金属化层134的材料形成共熔化合物。
图38示出根据一些其他实施例在用于形成装置封装的工艺期间的中间步骤。图38是剖视图。在图38所示实施例中，在装置封装100与散热器208A的界面处形成虚拟传导性特征214。虚拟传导性特征214可进一步改善装置封装100与散热器208A之间的热耦合。虽然是在图18至图24B所示实施例中说明形成虚拟传导性特征214，但应了解，可针对其中散热器208A附装到装置封装200的任何实施例形成虚拟传导性特征214。
在图38中，在装置封装100上形成粘合剂216。所述粘合剂位于管芯堆叠104、粘合剂124及虚拟半导体特征128上。可在装置封装100被单体化之前或之后在装置封装100上形成粘合剂216。粘合剂216可与粘合剂210类似，或可为不同的。虚拟传导性特征214形成在粘合剂216上，且由具有比虚拟半导体特征128的材料高的导热性的传导性材料形成。举例来说，虚拟传导性特征214可例如是焊料球，且可通过取放方法(pick and placemethod)来形成。虚拟传导性特征214可与管芯堆叠104、集成电路管芯50及其他周围装置电性隔离。随后，在粘合剂216上且围绕虚拟传导性特征214施配热界面材料212。散热器208A利用粘合剂210及热界面材料212附装到装置封装200。
此外，在图38中，将散热器208A附装到装置封装200。在粘合剂216上施配热界面材料212。在图34至图37所示实施例中，热界面材料212是金属性热界面材料，例如焊料膏、铟焊料膏等。使用粘合剂210将散热器208A粘附到封装衬底202。可在粘合剂216上施配热界面材料212，从而将装置封装100与散热器208A热耦合。在所示实施例中，散热器208A可具有金涂层，且热界面材料212可被回焊，从而与所述金涂层及虚拟传导性特征214的材料形成共熔化合物。
各实施例均可实现优点。集成电路管芯50中的虚拟半导体特征128可具有足以帮助移除由集成电路管芯50产生的热量中的某些热量的导热性。虚拟半导体特征128的材料(例如，硅)是充裕的，且可比其他导热性材料具有更低成本。在虚拟半导体特征128中添加额外特征(例如通孔132)可进一步提高虚拟半导体特征128的导热性，从而降低装置封装100的操作温度。此外，例如虚拟金属化层134及/或虚拟传导性特征214等的特征可提高散热器208A的导热性。虚拟半导体特征128可移除的热量足以帮助防止热量被陷滞在管芯堆叠104下方，从而降低装置封装100的操作温度并改善装置封装100的可靠性及电气性能。
在实施例中，一种散热方法包括：将管芯堆叠放置在装置晶片的前侧上；在所述装置晶片的背侧上形成传导性连接件；将所述装置晶片单体化以形成集成电路管芯，所述管芯堆叠设置在所述集成电路管芯上；将所述集成电路管芯放置在载体衬底上；将虚拟晶片的前侧结合到所述集成电路管芯，所述管芯堆叠设置在所述虚拟晶片的所述前侧中的凹槽中；从所述载体衬底剥离所述集成电路管芯；以及将所述虚拟晶片单体化以形成虚拟半导体特征，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离。
在一些实施例中，所述散热方法包括：在所述将所述虚拟晶片单体化之前，将所述虚拟晶片的背侧薄化，直至所述凹槽被暴露出为止，从而形成延伸穿透所述虚拟晶片的开口；以及在所述开口中形成粘合剂，所述粘合剂的顶表面、所述虚拟晶片的顶表面及所述管芯堆叠的顶表面是齐平的。在一些实施例中，所述散热方法进一步包括：在所述将所述虚拟晶片的所述前侧结合到所述集成电路管芯之前，在所述管芯堆叠上形成粘合剂；以及将所述虚拟晶片的所述前侧放置在所述集成电路管芯上，所述粘合剂填充所述凹槽。在一些实施例中，所述散热方法进一步包括：利用所述传导性连接件将所述集成电路管芯结合到封装衬底；在所述封装衬底与所述集成电路管芯之间形成底部填充剂，所述底部填充剂环绕所述传导性连接件及所述集成电路管芯；以及将散热器附装到所述封装衬底，所述散热器被粘附到所述虚拟半导体特征。
在实施例中，一种散热方法包括：将管芯堆叠放置在装置晶片的前侧上；将虚拟晶片的前侧结合到所述装置晶片的所述前侧，所述管芯堆叠设置在所述虚拟晶片的所述前侧中的凹槽中；将所述虚拟晶片的背侧薄化，直至所述凹槽被暴露出为止，从而形成延伸穿透所述虚拟晶片的开口；在所述开口中形成粘合剂，所述粘合剂的顶表面、所述虚拟晶片的顶表面及所述管芯堆叠的顶表面是齐平的；在所述装置晶片的背侧上形成传导性连接件；以及将所述装置晶片及所述虚拟晶片同时单体化，所述装置晶片被单体化而形成集成电路管芯，所述管芯堆叠设置在所述集成电路管芯上，所述虚拟晶片被单体化而形成虚拟半导体特征，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离。
在一些实施例中，所述散热方法进一步包括：形成从所述虚拟晶片的所述前侧延伸到所述虚拟晶片中的通孔。在一些实施例中，所述散热方法进一步包括：在所述将所述装置晶片及所述虚拟晶片单体化之前，在所述虚拟晶片上形成虚拟金属化层。在一些实施例中，所述散热方法进一步包括：利用所述传导性连接件将所述集成电路管芯结合到封装衬底；在所述封装衬底与所述集成电路管芯之间形成底部填充剂，所述底部填充剂环绕所述传导性连接件及所述集成电路管芯；以及将散热器附装到所述封装衬底，所述散热器被粘附到所述虚拟半导体特征。
在实施例中，一种散热装置包括：集成电路管芯，具有第一侧及与所述第一侧相对的第二侧；管芯堆叠，位于所述集成电路管芯的所述第一侧上；虚拟半导体特征，位于所述集成电路管芯的所述第一侧上，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离；第一粘合剂，设置在所述管芯堆叠与所述虚拟半导体特征之间；以及多个传导性连接件，位于所述集成电路管芯的所述第二侧上。
在一些实施例中，所述虚拟半导体特征的顶表面、所述管芯堆叠的顶表面及所述第一粘合剂的顶表面是齐平的。在一些实施例中，所述虚拟半导体特征横向延伸越过所述集成电路管芯的边缘。在一些实施例中，所述虚拟半导体特征的边缘与所述集成电路管芯的边缘是共边界的。在一些实施例中，所述第一粘合剂设置在所述管芯堆叠上，且所述虚拟半导体特征设置在所述第一粘合剂上。在一些实施例中，所述散热装置进一步包括：通孔，从所述集成电路管芯的所述第一侧延伸到所述虚拟半导体特征中。在一些实施例中，所述通孔延伸穿透所述虚拟半导体特征。在一些实施例中，所述通孔局部地延伸到所述虚拟半导体特征中。在一些实施例中，所述散热装置进一步包括：封装衬底，所述传导性连接件结合到所述封装衬底；以及支撑环，被粘附到所述封装衬底，所述支撑环环绕所述集成电路管芯。在一些实施例中，所述散热装置进一步包括：封装衬底，所述传导性连接件结合到所述封装衬底；散热器，被粘附到所述封装衬底；以及热界面材料，将所述散热器粘附到所述虚拟半导体特征。在一些实施例中，所述散热装置进一步包括：虚拟金属化层，位于所述虚拟半导体特征上，所述热界面材料设置在所述虚拟金属化层上。在一些实施例中，所述散热装置进一步包括：第二粘合剂，位于所述虚拟半导体特征上；以及虚拟传导性特征，设置在所述第二粘合剂上，所述热界面材料设置在所述第二粘合剂上且环绕所述虚拟传导性特征。
以上内容概述了若干实施例的特征以使所属领域中的技术人员可更好地理解本发明的各方面。所属领域中的技术人员应了解，他们可易于使用本发明作为基础来设计或修改其他工艺及结构以施行本文所介绍实施例的相同目的及/或实现本文所介绍实施例的相同优点。所属领域中的技术人员还应认识到，此种等效构造并不背离本发明的精神及范围，且在不背离本发明的精神及范围的条件下，他们可对本文作出各种改变、替代、及变更。

Claims (1)

1.一种散热方法，其特征在于，包括：
将管芯堆叠放置在装置晶片的前侧上；
在所述装置晶片的背侧上形成传导性连接件；
将所述装置晶片单体化以形成集成电路管芯，所述管芯堆叠设置在所述集成电路管芯上；
将所述集成电路管芯放置在载体衬底上；
将虚拟晶片的前侧结合到所述集成电路管芯，所述管芯堆叠设置在所述虚拟晶片的所述前侧中的凹槽中；
从所述载体衬底剥离所述集成电路管芯；以及
将所述虚拟晶片单体化以形成虚拟半导体特征，所述虚拟半导体特征横向环绕所述管芯堆叠，所述虚拟半导体特征与所述管芯堆叠及所述集成电路管芯电性隔离。
CN201711401935.0A 2017-06-30 2017-12-22 散热方法 Pending CN109216208A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762527770P 2017-06-30 2017-06-30
US62/527,770 2017-06-30
US15/800,349 US10483187B2 (en) 2017-06-30 2017-11-01 Heat spreading device and method
US15/800,349 2017-11-01

Publications (1)

Publication Number Publication Date
CN109216208A true CN109216208A (zh) 2019-01-15

Family

ID=64739034

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711401935.0A Pending CN109216208A (zh) 2017-06-30 2017-12-22 散热方法

Country Status (3)

Country Link
US (3) US10483187B2 (zh)
CN (1) CN109216208A (zh)
TW (1) TW201906025A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086443A (zh) * 2019-06-14 2020-12-15 台湾积体电路制造股份有限公司 封装体及其形成方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269682B2 (en) * 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
US10515867B2 (en) * 2017-11-14 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10312221B1 (en) 2017-12-17 2019-06-04 Advanced Micro Devices, Inc. Stacked dies and dummy components for improved thermal performance
US10573630B2 (en) * 2018-04-20 2020-02-25 Advanced Micro Devices, Inc. Offset-aligned three-dimensional integrated circuit
US11493713B1 (en) 2018-09-19 2022-11-08 Psiquantum, Corp. Photonic quantum computer assembly having dies with specific contact configuration and matched CTE
US11107799B1 (en) * 2018-12-21 2021-08-31 Psiquantum, Corp. Hybrid system including photonic and electronic integrated circuits and cooling plate
KR102619532B1 (ko) 2019-05-21 2024-01-02 삼성전자주식회사 반도체 패키지
US11621211B2 (en) * 2019-06-14 2023-04-04 Mediatek Inc. Semiconductor package structure
US11728238B2 (en) * 2019-07-29 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with heat dissipation films and manufacturing method thereof
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US20210280507A1 (en) * 2020-03-05 2021-09-09 Qualcomm Incorporated Package comprising dummy interconnects
TWI755281B (zh) 2021-02-18 2022-02-11 創意電子股份有限公司 散熱結構、半導體封裝裝置及半導體封裝裝置之製造方法
US20230116326A1 (en) * 2021-10-13 2023-04-13 Mediatek Inc. Semiconductor package with tsv die
US20230136202A1 (en) * 2021-11-01 2023-05-04 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
WO2023091430A1 (en) * 2021-11-17 2023-05-25 Adeia Semiconductor Bonding Technologies Inc. Thermal bypass for stacked dies
US20230197563A1 (en) * 2021-12-17 2023-06-22 Advanced Micro Devices, Inc. Semiconductor chip device integrating thermal pipes in three-dimensional packaging
WO2024097375A2 (en) * 2022-11-03 2024-05-10 Board Of Regents, The University Of Texas System Tim-free heat spreader

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
KR20100046760A (ko) * 2008-10-28 2010-05-07 삼성전자주식회사 반도체 패키지
US8330262B2 (en) * 2010-02-02 2012-12-11 International Business Machines Corporation Processes for enhanced 3D integration and structures generated using the same
US10297550B2 (en) * 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US8378480B2 (en) * 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086443A (zh) * 2019-06-14 2020-12-15 台湾积体电路制造股份有限公司 封装体及其形成方法

Also Published As

Publication number Publication date
US10483187B2 (en) 2019-11-19
US20200013698A1 (en) 2020-01-09
US10867885B2 (en) 2020-12-15
US20190006263A1 (en) 2019-01-03
US20200013697A1 (en) 2020-01-09
TW201906025A (zh) 2019-02-01
US10867884B2 (en) 2020-12-15

Similar Documents

Publication Publication Date Title
CN109216208A (zh) 散热方法
KR102183614B1 (ko) 열 확산 디바이스 및 방법
US11961811B2 (en) Semiconductor structures and method of manufacturing the same
CN102163596B (zh) 集成电路元件及其形成方法
CN107591387B (zh) 半导体封装件和形成该半导体封装件的方法
US11817410B2 (en) Integrated circuit package and method
CN113517269A (zh) 封装结构
EP3945565A1 (en) Packaged semiconductor device including liquid-cooled lid and methods of forming the same
US11848246B2 (en) Integrated circuit package and method
TWI830470B (zh) 包括用於散熱之單片矽結構之半導體裝置總成及製造其之方法
CN210692483U (zh) 一种封装结构
US20240006270A1 (en) Package with Improved Heat Dissipation Efficiency and Method for Forming the Same
CN116072625A (zh) 包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190115

WD01 Invention patent application deemed withdrawn after publication