CN104037153A - 3d封装件及其形成方法 - Google Patents

3d封装件及其形成方法 Download PDF

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Publication number
CN104037153A
CN104037153A CN201310239320.8A CN201310239320A CN104037153A CN 104037153 A CN104037153 A CN 104037153A CN 201310239320 A CN201310239320 A CN 201310239320A CN 104037153 A CN104037153 A CN 104037153A
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Prior art keywords
tube core
intermediary layer
connectors
face
substrate
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CN201310239320.8A
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CN104037153B (zh
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张进传
林俊成
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种封装件，包括中介层，中介层包括没有通孔的第一衬底、位于第一衬底上方的再分布线和位于再分布线上方并与再分布线电连接的多个第一连接件。第一管芯位于多个第一连接件上方并与多个第一连接件接合。第一管芯包括第二衬底和位于第二衬底中的通孔。第二管芯位于多个连接件上方并与多个连接件接合。第一管芯和第二管芯通过再分布线彼此电连接。多个第二连接件位于第一管芯和第二管芯上方。多个第二连接件通过第二衬底中的通孔电连接至多个第一连接件。本发明还公开了3D封装件的形成方法。

Description

3D封装件及其形成方法
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及封装件及其形成方法。
背景技术
在一些三维集成电路（3DIC）中，首先将器件管芯接合至中介层，然后将中介层进一步接合至封装衬底以形成封装件。需要消散器件管芯在这些操作期间所产生的热量。在传统的结构中，为了散热，将器件管芯的衬底附接至散热器，散热器的尺寸大于器件管芯和封装衬底的尺寸。因此，器件管芯所产生的热量扩散到更大的区域。将散热片附接至散热器以消散传导至散热器的热量。
通过热界面材料（TIM）将器件管芯附接至散热片，热界面材料可以包括环氧基材料。此外，可以将诸如硅颗粒的一些导热材料混合在环氧基材料中以提高TIM的导热性。通过另一TIM将散热片附接至散热器。由于这两种TIM的使用，降低了散热效率。
而且，传统的封装件还面临日益减小的厚度和提高封装件中的封装部件之间的通讯效率的挑战。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种封装件，包括：中介层，包括：第一衬底，所述第一衬底中没有通孔；再分布线，位于所述第一衬底上方；和多个第一连接件，位于所述再分布线上方并且与所述再分布线电连接；第一管芯，位于所述多个第一连接件上方并且与所述多个第一连接件接合，所述第一管芯包括：第二衬底；和通孔，位于所述第二衬底中；第二管芯，位于所述多个连接件上方并且与所述多个连接件接合，其中，所述第一管芯和所述第二管芯通过所述再分布线彼此电连接；以及多个第二连接件，位于所述第一管芯和所述第二管芯上方，所述多个第二连接件通过所述第二衬底中的所述通孔电连接至所述多个第一连接件。
在该封装件中，所述中介层中没有有源器件。
在该封装件中，所述中介层中没有无源器件。
该封装件进一步包括：模塑料，环绕所述第一管芯和所述第二管芯，所述模塑料的顶面与所述第一管芯的顶面齐平；以及介电层，位于所述第一管芯、所述第二管芯和所述模塑料上方，其中所述多个第二连接件位于所述介电层上方。
在该封装件中，所述第二管芯中没有通孔。
在该封装件中，所述第一管芯通过面对背接合而接合至所述中介层，所述第一管芯的背面接合至所述中介层的正面。
在该封装件中，所述第一管芯通过面对面接合而接合至所述中介层，所述第一管芯的正面接合至所述中介层的正面。
根据本发明的另一方面，提供了一种封装件，包括：中介层，所述中介层中没有有源器件，所述中介层包括：硅衬底，所述硅衬底中没有通孔；再分布线，位于所述硅衬底上方；和多个第一连接件，位于所述再分布线上方并且与所述再分布线电连接；第一管芯，位于所述多个连接件上方并且与所述多个连接件接合，所述第一管芯包括：第一半导体衬底；多个第一通孔，位于所述第一半导体衬底中；和金属柱，电连接至所述多个第一通孔；第二管芯，位于所述多个连接件上方并且与所述多个连接件接合，其中，所述第一管芯和所述第二管芯通过所述再分布线彼此电连接；模塑料，环绕所述第一管芯和所述第二管芯，所述模塑料的顶面与所述第一管芯的顶面齐平；以及多个第二连接件，位于所述第一管芯和所述第二管芯上方，所述多个第二连接件通过所述第一半导体衬底中的所述多个第一通孔和所述金属柱电连接至所述多个第一连接件。
在该封装件中，所述第一管芯的背面通过面对背接合而接合至所述中介层的正面，并且所述金属柱的顶面与所述模塑料的顶面齐平。
在该封装件中，所述第一管芯的正面通过面对面接合而接合至所述中介层的正面，并且所述多个第一通孔的顶面与所述模塑料的顶面齐平。
在该封装件中，所述第二管芯进一步包括：第二半导体衬底；以及多个第二通孔，穿透所述第二半导体衬底，部分所述多个第二连接件分通过所述多个第二通孔电连接至部分所述多个第一连接件，并且所述多个第一通孔和所述多个第二通孔的顶面相互齐平。
在该封装件中，所述第二管芯的顶面低于所述第一管芯的顶面，并且所述模塑料的一部分延伸至所述第二管芯的顶面上方并且与所述第二管芯的顶面接触。
在该封装件中，所述第一管芯包括逻辑管芯，并且所述第二管芯包括存储管芯。
在该封装件中，所述第一管芯进一步包括：与所述金属柱处于同一平面的聚合物层，所述聚合物层环绕所述金属柱，并且所述聚合物层的表面与所述金属柱的表面齐平。
根据本发明的又一方面，提供了一种方法，包括：在中介层晶圆的正面上接合第一管芯，所述中介层晶圆不包括位于所述中介层晶圆的第一衬底中的通孔，并且所述第一管芯包括位于所述第一管芯的第二衬底中的多个第一通孔；在所述中介层晶圆上方分配模塑料，在所述模塑料中模制所述第一管芯；实施平坦化以使所述模塑料的顶面与所述第一管芯的顶面齐平直到暴露所述第一管芯中的导电部件，所述导电部件电连接至所述中介层晶圆；在所述模塑料和所述第一管芯上方形成再分布线，所述再分布线电连接至所述导电部件；以及形成连接件以电连接至所述再分布线。
在该方法中，所述第一管芯通过面对面接合而接合至所述中介层晶圆，其中，在所述平坦化之后，所述多个第一通孔的顶面与所述模塑料的顶面齐平。
该方法进一步包括：在所述中介层晶圆的正面上接合第二管芯，在所述模塑料中模制所述第二管芯，所述第二管芯包括位于所述第二管芯的第二衬底中的多个第二通孔，并且在所述平坦化之后所述多个第二通孔的顶面与所述多个第一通孔的顶面齐平。
在该方法中，所述第一管芯利用嵌入所述第二衬底中的所述多个第一通孔接合至所述中介层晶圆，并且在所述平坦化中去除所述第二衬底位于所述多个第一通孔上方的部分。
在该方法中，所述第一管芯通过面对背接合而接合至所述中介层晶圆，并且在所述平坦化之后，所述第一管芯中的金属柱的顶面与所述模塑料的顶面齐平。
该方法进一步包括：减薄所述第一衬底；以及在减薄所述第一衬底的步骤之后，切割所述中介层晶圆。
附图说明
为了更充分地理解本发明和优点，现在将结合附图所进行以下描述作为参考，其中：
图1A至图1K是根据一些示例性实施例处于制造面对背封装件的中间阶段的截面图；
图2A至图2I是根据一些示例性实施例处于制造面对面异质封装件的中间阶段的截面图；
图3A至图3F是根据一些示例性实施例处于制造面对面异质封装件的中间阶段的截面图；以及
图4示出样本封装件（当通电时）的温度作为样本封装件中的CPU管芯的功率的函数。
具体实施方式
以下详细论述本发明的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例是示例性的，而不用于限制实施例的范围。
根据各种示例性实施例提供了一种封装件及其形成方法。示出了形成封装件的中间阶段。论述了实施例的变型例。在各个附图和所有示例性实施例中，相同的参考标号用于指定相同的元件。
图1A至图1K是根据一些示例性实施例处于制造面对背封装件的中间阶段的截面图，其中将中介层的正面接合至器件管芯的背面和/或存储管芯的背面。图1A至图1D示出了器件管芯100的形成。参考图1A，形成器件晶圆102。器件晶圆102包括在其中的多个相同的器件管芯100。器件晶圆102可以包括半导体衬底104，并且可以包括形成在半导体衬底104中的集成电路器件106和上面的互连结构108。为了清楚起见，在后续附图中没有示出集成电路器件106，但是它们仍然存在。半导体衬底104可以是硅衬底，或者可以由诸如硅锗、碳化硅、III-V族化合物半导体等的其他半导体材料形成。互连结构108包括用于互连集成电路器件106的金属线和通孔110。示意性地示出金属线和通孔110，没有示出其中的具体结构。集成电路器件106可以包括诸如晶体管的有源器件。因此，器件晶圆102可以是逻辑器件晶圆，其包括多个逻辑管芯100。为清楚起见，在后续的附图中没有示出集成电路器件106，但是它们仍然存在。
金属焊盘112形成在管芯100中并且通过金属线和通孔110电连接至集成电路器件106。金属焊盘112可以包括：铝、铜、镍或者它们的组合。介电层114形成在金属焊盘112上方。介电层114可以所具有的厚度T1大于约10μm的厚层，其中厚度T1可以介于约10μm和约50μm之间。介电层114的材料可以选自诸如阻焊剂、聚苯并恶唑（PBO）、苯并环丁烯（BCB）、模塑料等的聚合物。在可选实施例中，介电层114可以包括氧化硅、氮化硅等。
金属柱116形成在介电层114中并且电连接至金属焊盘112。在一些实施例中，金属柱116的底面与金属焊盘112的顶面接触。金属柱116可以包括铜，因此，在通篇描述中，可选地被称为铜柱116。然而，诸如镍和/或铝的其他导电材料也可以用于铜柱116中。铜柱116的高度H1还可以大于约10μm，并且可以介于约10μm和约50μm之间。在一些实施例中，铜柱116的顶面116a与介电层114的顶面114a基本上齐平。在其他实施例中，铜柱116的顶面116a高于顶面114a，使得铜柱116的部分凸出到顶面114a之上。通孔118（其是导电通孔）形成在衬底104中并且通过金属焊盘112以及金属线和通孔110电连接至金属柱116。在通篇描述中，通孔118可选地被称为衬底通孔（TSV）或者硅通孔。
接下来，参考图1B，例如，通过粘合剂122将晶圆102的正面安装在载具120上。例如，载具120可以是玻璃载具、陶瓷载具、有机载具。在一些示例性实施例中，粘合剂122可以是紫外线（UV）胶。然后，实施背面研磨以去除衬底104的多余部分直到暴露TSV118。接下来，如图1C所示，连接件130形成在衬底104的背面上并且电连接至TSV118。在一些实施例中，连接件130包括金属焊盘（线）124、金属柱126和焊球128。在衬底104的背面上形成附加再分布线（未示出），这些附加再分布线互连连接件130和TSV118。连接件130还可以具有诸如焊球的其他结构。
在形成连接件130之后，从载具120上卸下晶圆102。接下来，如图1D所示，将晶圆102切割开，从而使管芯100相互分离。在一些实施例中，为了切割晶圆102，在切割胶带132上附接晶圆102，并且当连接至切割胶带132时切割该晶圆102。然后将分离的管芯100与切割胶带132分离。
图1E示出中介层晶圆200，其包括再分布线202和连接至再分布线202的连接件204。示意性地示出再分布线202，没有示出其中的详细的结构。再分布线202可以包括分布在多层中的金属线，以及互连不同层的金属线的通孔。再分布线202和连接件204位于衬底206上方。连接件204可以包括铜柱、金属焊盘、焊料层和/或焊料等。在一些实施例中，衬底206包括硅衬底。在可选实施例中，衬底206是诸如玻璃衬底的介电衬底。
根据一些实施例，中介层晶圆200可以没有有源器件（诸如晶体管）和无源器件（诸如电感器、电阻器和电容器）。在可选实施例中，中介层晶圆200包括无源器件，但不包括有源器件。在其他可选实施例中，中介层晶圆200包括其中的有源器件和无源器件。中介层晶圆200不包括其中的TSV。因此，每个连接件204都通过再分布线202最终都可以连接至另一个连接件204。
参考图1F，管芯100和300接合至中介层晶圆200。虽然示出了一个管芯100和一个管芯300，但是可以存在接合至中介层晶圆200的多个相同的管芯100和多个相同的管芯300。管芯100的连接件130接合至中介层晶圆200的连接件204。中介层晶圆200的正面面对管芯100的背面，因此相应的接合被称为面对背接合。
而且，管芯300包括接合至中介层晶圆200的连接件204的连接件302。在一些实施例中，管芯300可以是存储管芯，但是管芯300还可以是逻辑管芯。在一些实施例中，管芯300包括存储器304，诸如动态随机存取存储器（DRAM）、静态随机存取存储器（SRAM）等。存储器304电连接至中介层晶圆200中的连接件204。因此，管芯100通过中介层晶圆200中的再分布线202和连接件204电互连至管芯300，并且电连接至存储器304。
图1G示出底部填充物20分配在中介层晶圆200和管芯100之间的间隙中以及中介层晶圆200和管芯300之间的间隙中。而且，模塑料22分配在管芯100、管芯300和中介层晶圆200上方以及管芯100和管芯300之间的间隙中。模塑料22还覆盖管芯100和管芯300的顶面。实施固化工艺以使底部填充物20和模塑料22凝固。在可选实施例中，用模塑底部填充物来取代底部填充物20和模塑料22。
参考图1H，在模塑料22上实施诸如研磨的平坦化直到暴露铜柱116以及可能暴露介电层114。因此，介电层114的顶面114a、铜柱116的顶面116a和模塑料22的顶面22a相互之间可以基本上齐平。由于研磨，没有模塑料22高于管芯100。当从顶部观察时，铜柱116被介电层114环绕并且与介电层114接触。此外，每一管芯100中的铜柱116和介电层114形成被模塑料22环绕的集成部件。
图1I示出导电部件26的形成，并且连接件32电连接至导电部件26。导电部件26可以包括铜、钨和/或镍等。在一些实施例中，在管芯100、300和模塑料22上方形成介电层33，随后图案化介电层33，使得暴露金属柱116。在介电层33和导电部件26上方形成介电层34。在一些实施例中，介电层33和34可以是聚合物层，并且可以包括聚酰亚胺、PBO等。在介电层34中形成开口以暴露导电部件26。然后，在开口中形成连接件32以连接至导电部件26。在一些实施例中，连接件32包括凸块下金属化层（UBM）29和位于UBM29上方的焊球30。在可选实施例中，连接件32可以具有诸如铜柱、预焊料层等的其他结构。因而连接件32可以通过导电部件26电连接至中介层晶圆200中的连接件204。而且，连接件32可以通过中介层晶圆200中的连接件204和再分布线202电连接至管芯300。
图1J中，例如通过研磨步骤减薄中介层晶圆200的衬底206。然后将晶圆200连接至切割胶带28，并且将中介层晶圆200和上面的管芯100、300切割成多个封装件35。每一个封装件35都包括一块中介层晶圆200，该块在下文中被称为中介层201。每一个封装件35也都包括通过中介层201互连的管芯100和管芯300。然后可以将封装件35与切割胶带28分离。
根据一些实施例，可以图案化中介层晶圆200的衬底206以形成沟槽220。在切割步骤之前，可以以晶圆级实施图案化，并且可以通过例如激光开槽、蚀刻等形成图案。还可以在减薄衬底206之前或之后形成该图案。在中介层201的底视图中沟槽220可以形成为栅格，因此衬底206的剩余部分形成被沟槽220环绕的多个突出物。因而衬底206具有良好的散热能力。在得到的封装件中，如图1K所示（还如图2I和3F所示），得到的中介层201可以包括或者可以不包括沟槽220和突出物。
图1K示出将封装件35接合至印刷电路板（PCB）36。根据实施例，连接件32是球栅阵列（BGA）球，因而可以直接接合至PCB36，而没有它们之间的封装衬底。而且，中介层201用作得到的封装件的散热元件，并且用作管芯100和管芯300之间的互连件。
图2A至图2I和图3A至图3F示出根据可选实施例处于形成封装件的中间阶段的截面图。除非另有指明，否则这些实施例中的部件的材料和形成方法与图1A至图1K所示的实施例中用类似的参考标号表示的类似部件的材料和形成方法实质上相同。因而，可以在图1A至图1K所示的实施例的描述中找到图2A至图2I和图3A至图3F所示的部件的形成工艺和材料的具体细节。
图2A和图2B示出管芯100的制备。参考图2A，形成器件晶圆102。器件晶圆102与图1A所示的器件晶圆实质上相同，因此此处不再重复器件晶圆102的具体细节。接下来，参考图2B，将器件晶圆102切割成管芯100。此时，还没有完成管芯100的形成，并且在后续的附图中示出了管芯100的其余的形成工艺的步骤。
图2C中，形成中介层晶圆200。中介层晶圆200与图1E所示的中介层晶圆实质上相同，因而此处不再重复中介层晶圆200的具体细节。在图2D中，管芯100和管芯300接合至中介层晶圆200，其中管芯100中的铜柱116和管芯300中的连接件302接合至中介层晶圆200。此外，多个管芯100和多个管芯300接合至中介层晶圆200，但是仅示出一个管芯100和一个管芯300。在这些实施例中，中介层晶圆200的正面面对着管芯100的正面，因而相应的接合被称为面对面接合。
接下来，如图2E所示，分配底部填充物20和模塑料22，其中模塑料22的顶面高于管芯100和管芯300。然后，如图2F所示，例如通过化学机械抛光（CMP）实施平坦化。实施CMP直到暴露TSV118的后端。在这些实施例中，可以存在位于管芯300上方的模塑料层22。在可选实施例中，在研磨之后，还暴露管芯300的背面。
参考图2G，形成导电部件26、介电层33、34和连接件32。因而连接件32可以通过TSV118电连接至中介层晶圆200中的连接件204。而且，连接件32可以通过中介层晶圆200中的连接件204和再分布线202电连接至管芯300。图2H和图2I示出减薄中介层晶圆200中的衬底206，中介层晶圆200附接在切割胶带28上，以及切割步骤。因此形成封装件35（图2H）。接下来，如图2I所示，封装件35接合至PCB36。
在图2I所示的实施例中，管芯300（其可以是存储管芯）不包括其中的TSV，因而连接件32和中介层201之间的电互连是通过管芯100而不是通过管芯300。在可选实施例中，TSV还可以形成在管芯300中，并且管芯100和管芯300都可以用作互连连接件32和中介层201的互连路径。图3A至图3G示出相应的形成工艺的中间阶段。
参考图3A，管芯100和300接合至中介层晶圆200。在这些实施例中，管芯100和管芯300的正面接合至中介层晶圆200的正面，因此相应的接合被称为面对面接合。TSV118嵌入衬底104中，并且在管芯300中TSV218嵌入衬底306中。衬底306可以是诸如硅衬底的半导体衬底。
接下来，参考图3B，分配并且固化底部填充物20和模塑料22，其中模塑料22的顶面高于管芯100和管芯300的顶面。然后，例如通过CMP实施平坦化。图3C示出了得到的结构。实施CMP直到暴露衬底104和306，并且继续进行CMP从而使得TSV118和218的后端都被暴露出来。
参考图3D，形成导电部件26、介电层33、34和连接件32。因而，连接件32可以电连接至中介层晶圆200中的连接件204。图3E和图3F示出减薄中介层晶圆200中的衬底206，中介层晶圆200附接在切割胶带28上，以及切割该结构。从而形成封装件35。接下来，如图3F所示，封装件35接合至PCB36。
在本发明的实施例中，中介层具有互连其上接合的管芯的功能。然而，中介层没有其中的TSV。因此，中介层没有电连接至位于管芯的相对面上的任何封装部件。因而，中介层可以用作散热元件。模拟结果显示中介层的散热能力与可以通过TIM附接至管芯的金属盖基本上相同。例如，图4示出3个样本封装件的模拟结果的比较。第一样本封装件包括图1K所示的结构，具有与接合至图1K中的中介层201的附加热焊盘以及附接至热焊盘的附加金属电磁干扰（EMI）屏蔽件。在第二样本封装件中，热界面材料和盖取代了图1K中的中介层201。在第三样本封装件中，模塑料层（其可以与模塑料22相同，参见图1G）取代了图1K中的中介层201。第一样本封装件、第二样本封装件和第三样本封装件的其余部件彼此都相同。图4示出了模拟结果，其中示出样本封装件的温度（当通电时）作为管芯100（图1K）的功率的函数，管芯100在模拟中为CPU管芯。第一样本封装件、第二样本封装件和第三样本封装件的结果分别示出为线402、404和406。结果显示第三样本封装件具有最高的温度，表明第三样本封装件在3个样本封装件中具有最差的散热能力。第一样本封装件和第二样本封装件的温度相互接近，表明本发明的实施例的封装件与采用金属盖的第二样本封装件具有一样好的散热能力。然而，第一样本封装件比第二样本封装件具有更好的金属布线能力。图4进一步示出随着CPU功率的增加，第一样本封装件和第二样本封装件仍然具有相互接近的散热能力。
此外，模拟结果显示当中介层中的衬底的厚度从775μm减少至250μm时，具有图1K、2I和图3F中的结构的相应的封装件的温度从约75℃增加至约77℃，这意味着在不牺牲封装件的散热能力的情况下可以显著减小封装件的总厚度。另外，还实施模拟以将包含金属EMI屏蔽件的样本封装件和不包含EMI屏蔽件的样本封装件进行比较，其中根据本发明的实施例模拟的样本封装件包括中介层（诸如图1K中的201）和CPU管芯（诸如图1K中的管芯100）。模拟结果显示包含EMI屏蔽件的样本封装件的温度可以在约74.8℃至约77.2℃的范围内（通电的封装件中具有CPU管芯）。作为比较，不包含EMI屏蔽件的样本封装件的温度可以在77.2℃至约79.2℃的范围内（通电的封装件中具有CPU管芯）。因此，当从封装件移除EMI屏蔽件时，封装件的温度增加仅在约2℃和约3℃之间的范围内。这表明包含中介层的封装件的散热能力仍然足够好，因此EMI屏蔽件对散热能力具有很小的影响。
根据一些实施例，一种封装件包括中介层，中介层包括其中没有通孔的第一衬底、位于第一衬底上方的再分布线以及位于再分布线上方并电连接至再分布线的多个第一连接件。第一管芯位于多个第一连接件上方并与多个第一连接件接合。第一管芯包括第二衬底和位于第二衬底中的通孔。第二管芯位于多个连接件上方并与多个连接件接合。第一管芯和第二管芯通过再分布线彼此电连接。多个第二连接件位于第一管芯和第二管芯上方。多个第二连接件通过第二衬底中的通孔电连接至多个第一连接件。
根据其他实施例，一种封装件包括其中没有有源器件的中介层。中介层包括其中没有通孔的硅衬底、位于硅衬底上方的再分布线以及位于再分布线上方并与其电连接的多个第一连接件。第一管芯位于多个连接件上方并与多个连接件接合。第一管芯包括第一半导体衬底、位于第一半导体衬底中的多个第一通孔以及电连接至多个第一通孔的金属柱。第二管芯位于多个连接件上方并与多个连接件接合，其中第一管芯和第二管芯通过再分布线彼此电连接。模塑料环绕第一管芯和第二管芯。模塑料的顶面与第一管芯的顶面齐平。多个第二连接件位于第一管芯和第二管芯上方。多个第二连接件通过第一半导体衬底中的多个第一通孔和金属柱电连接至多个第一连接件。
根据又一些实施例，一种方法包括将第一管芯接合至中介层晶圆的正面上。中介层晶圆没有位于中介层晶圆的第一衬底中的通孔。第一管芯包括位于第一管芯的第二衬底中的多个第一通孔。在中介层晶圆上方分配模塑料，其中嵌入在模塑料中模制第一管芯。实施平坦化以使模塑料的顶面与第一管芯的顶面齐平直到暴露第一管芯中的导电部件，其中导电部件电连接至中介层晶圆。在模塑料和第一管芯上方形成再分布线，其中再分布线电连接至导电部件。形成连接件以电连接至再分布线。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的构思和范围的情况下，进行各种改变、替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种封装件，包括：
中介层，包括：
第一衬底，所述第一衬底中没有通孔；
再分布线，位于所述第一衬底上方；和
多个第一连接件，位于所述再分布线上方并且与所述再分布线电连接；
第一管芯，位于所述多个第一连接件上方并且与所述多个第一连接件接合，所述第一管芯包括：
第二衬底；和
通孔，位于所述第二衬底中；
第二管芯，位于所述多个连接件上方并且与所述多个连接件接合，其中，所述第一管芯和所述第二管芯通过所述再分布线彼此电连接；以及
多个第二连接件，位于所述第一管芯和所述第二管芯上方，所述多个第二连接件通过所述第二衬底中的所述通孔电连接至所述多个第一连接件。
2.根据权利要求1所述的封装件，其中，所述中介层中没有有源器件。
3.根据权利要求2所述的封装件，其中，所述中介层中没有无源器件。
4.根据权利要求1所述的封装件，进一步包括：
模塑料，环绕所述第一管芯和所述第二管芯，所述模塑料的顶面与所述第一管芯的顶面齐平；以及
介电层，位于所述第一管芯、所述第二管芯和所述模塑料上方，其中所述多个第二连接件位于所述介电层上方。
5.根据权利要求1所述的封装件，其中，所述第二管芯中没有通孔。
6.根据权利要求1所述的封装件，其中，所述第一管芯通过面对背接合而接合至所述中介层，所述第一管芯的背面接合至所述中介层的正面。
7.根据权利要求1所述的封装件，其中，所述第一管芯通过面对面接合而接合至所述中介层，所述第一管芯的正面接合至所述中介层的正面。
8.一种封装件，包括：
中介层，所述中介层中没有有源器件，所述中介层包括：
硅衬底，所述硅衬底中没有通孔；
再分布线，位于所述硅衬底上方；和
多个第一连接件，位于所述再分布线上方并且与所述再分布线电连接；
第一管芯，位于所述多个连接件上方并且与所述多个连接件接合，所述第一管芯包括：
第一半导体衬底；
多个第一通孔，位于所述第一半导体衬底中；和
金属柱，电连接至所述多个第一通孔；
第二管芯，位于所述多个连接件上方并且与所述多个连接件接合，其中，所述第一管芯和所述第二管芯通过所述再分布线彼此电连接；
模塑料，环绕所述第一管芯和所述第二管芯，所述模塑料的顶面与所述第一管芯的顶面齐平；以及
多个第二连接件，位于所述第一管芯和所述第二管芯上方，所述多个第二连接件通过所述第一半导体衬底中的所述多个第一通孔和所述金属柱电连接至所述多个第一连接件。
9.根据权利要求8所述的封装件，其中，所述第一管芯的背面通过面对背接合而接合至所述中介层的正面，并且所述金属柱的顶面与所述模塑料的顶面齐平。
10.一种方法，包括：
在中介层晶圆的正面上接合第一管芯，所述中介层晶圆不包括位于所述中介层晶圆的第一衬底中的通孔，并且所述第一管芯包括位于所述第一管芯的第二衬底中的多个第一通孔；
在所述中介层晶圆上方分配模塑料，在所述模塑料中模制所述第一管芯；
实施平坦化以使所述模塑料的顶面与所述第一管芯的顶面齐平直到暴露所述第一管芯中的导电部件，所述导电部件电连接至所述中介层晶圆；
在所述模塑料和所述第一管芯上方形成再分布线，所述再分布线电连接至所述导电部件；以及
形成连接件以电连接至所述再分布线。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107180795A (zh) * 2016-03-11 2017-09-19 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
CN107680958A (zh) * 2016-08-02 2018-02-09 上海珏芯光电科技有限公司 射频微系统封装模块及其制造方法
CN108346635A (zh) * 2017-01-13 2018-07-31 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN109585312A (zh) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 扇出封装工艺中的对准凸块
US10748870B2 (en) 2015-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer COWOS structure
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
US11217555B2 (en) 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
WO2022110936A1 (zh) * 2020-11-26 2022-06-02 苏州矽锡谷半导体科技有限公司 一种功率元件封装结构及其制备方法
US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8933551B2 (en) 2013-03-08 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-packages and methods for forming the same
US8877554B2 (en) * 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9379041B2 (en) 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US10026671B2 (en) * 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10332841B2 (en) 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US11276667B2 (en) * 2016-12-31 2022-03-15 Intel Corporation Heat removal between top and bottom die interface
US10319670B2 (en) 2017-10-20 2019-06-11 Semiconductor Components Industries, Llc Package including multiple semiconductor devices
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10283461B1 (en) 2017-11-22 2019-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure and method forming same
US11075137B2 (en) 2018-05-02 2021-07-27 Semiconductor Components Industries, Llc High power module package structures
US10985134B2 (en) * 2018-11-09 2021-04-20 Nanya Technology Corporation Method and system of manufacturing stacked wafers
US11088041B2 (en) * 2019-09-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with shortened talking path
US20220077085A1 (en) * 2020-09-09 2022-03-10 Medtronic, Inc. Electronic package and implantable medical device including same
US11967538B2 (en) 2021-04-09 2024-04-23 Google Llc Three dimensional IC package with thermal enhancement

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW373308B (en) 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US6110806A (en) * 1999-03-26 2000-08-29 International Business Machines Corporation Process for precision alignment of chips for mounting on a substrate
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process
US6507115B2 (en) 2000-12-14 2003-01-14 International Business Machines Corporation Multi-chip integrated circuit module
SG106054A1 (en) * 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
JP4318417B2 (ja) * 2001-10-05 2009-08-26 ソニー株式会社 高周波モジュール基板装置
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
KR100923562B1 (ko) * 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US8106520B2 (en) * 2008-09-11 2012-01-31 Micron Technology, Inc. Signal delivery in stacked device
US8654119B2 (en) * 2009-08-17 2014-02-18 Mistretta Medical, Llc System and method for four dimensional angiography and fluoroscopy
US8803332B2 (en) 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
KR101037827B1 (ko) 2009-10-06 2011-05-30 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US8435835B2 (en) * 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
TW201308453A (zh) * 2011-08-15 2013-02-16 Ind Tech Res Inst 晶片封裝製程與晶片封裝結構
US8963334B2 (en) * 2011-08-30 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-die gap control for semiconductor structure and method
US8686570B2 (en) * 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
US8933551B2 (en) * 2013-03-08 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D-packages and methods for forming the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10748870B2 (en) 2015-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer COWOS structure
US11244924B2 (en) 2015-11-30 2022-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
CN107180795A (zh) * 2016-03-11 2017-09-19 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
CN107180795B (zh) * 2016-03-11 2019-09-06 台湾积体电路制造股份有限公司 包括电压调节器的集成扇出封装件及其形成方法
US10497668B2 (en) 2016-03-11 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US11063016B2 (en) 2016-03-11 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
CN107680958A (zh) * 2016-08-02 2018-02-09 上海珏芯光电科技有限公司 射频微系统封装模块及其制造方法
CN107680958B (zh) * 2016-08-02 2020-01-24 上海珏芯光电科技有限公司 射频微系统封装模块及其制造方法
CN108346635A (zh) * 2017-01-13 2018-07-31 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US11342255B2 (en) 2017-01-13 2022-05-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN108346635B (zh) * 2017-01-13 2021-10-15 台湾积体电路制造股份有限公司 半导体结构及其制造方法
US11217555B2 (en) 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
CN109585312B (zh) * 2017-09-29 2021-11-30 台湾积体电路制造股份有限公司 扇出封装工艺中的对准凸块
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WO2022110936A1 (zh) * 2020-11-26 2022-06-02 苏州矽锡谷半导体科技有限公司 一种功率元件封装结构及其制备方法
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US11955396B2 (en) 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12046525B2 (en) 2020-11-27 2024-07-23 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly

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