CN108140632B - 一种芯片 - Google Patents

一种芯片 Download PDF

Info

Publication number
CN108140632B
CN108140632B CN201580078921.2A CN201580078921A CN108140632B CN 108140632 B CN108140632 B CN 108140632B CN 201580078921 A CN201580078921 A CN 201580078921A CN 108140632 B CN108140632 B CN 108140632B
Authority
CN
China
Prior art keywords
chip
metal layer
carrier
rewiring
packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580078921.2A
Other languages
English (en)
Other versions
CN108140632A (zh
Inventor
符会利
张晓东
林志荣
马志強
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN108140632A publication Critical patent/CN108140632A/zh
Application granted granted Critical
Publication of CN108140632B publication Critical patent/CN108140632B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

一种芯片，其包括载体(220)、重布线结构(240)和多个封装功能模块(260)，所述多个封装功能模块均有至少一部分被胶体(262)包裹，并被并行固定在所述重布线结构上，所述重布线结构被固定在所述载体上，所述重布线结构中包括一层或多层重布线金属层(242)，所述重布线金属层将所述多个封装功能模块与所述载体通信连接，所述重布线结构中还包括一层或多层互连金属层(244)，所述互连金属层与至少两个封装功能模块通信连接，以在至少两个封装功能模块间提供信号通路。在所述芯片中，两个封装功能模块被并行放置到载体上，并通过重布线结构来建立彼此之间的信号通路，因此不存在由叠加引起的散热问题，而且能够有效地保证封装功能模块间的信号通路的长度不会过长。

Description

一种芯片
技术领域
本发明实施例涉及芯片技术，尤其涉及一种将多个封装功能模块并行封装的芯片。
背景技术
随着半导体工艺的精进以及芯片功能的提升，一个芯片中能够装载越来越多的集成电路。基于产业和工业制造上的需求，应用于芯片中的集成电路被搭载在各种各样的裸芯片中。随着工艺的发展和出于于更高功能的需求，将两个或两个以上裸芯片封装在一起的封装方式越来越受到业界的重视。
封装在一个芯片中的多个裸芯片并不是独立工作的。不同的裸芯片之间存在数据交互的需求，而数据通路的长度又会对芯片的性能有较大的影响，因此如何缩短裸芯片间数据通讯的通道长度也就变成了业界中的一道重要课题。目前业界存在着一种3D集成封装技术，如图1所示，芯片100的载体11上承载有晶圆级封装(Water-Level Packaging，以下简称WLP)18。所述WLP18中包括裸芯片12、包裹在裸芯片12周围的胶体14，以及形成于裸芯片12和胶体14表面的重布线层15。所述重布线层15的底部设有凸点17。所述重布线层15和凸点17构成了裸芯片12与载体11之间的信号通路。
所述芯片100还包括承载在WLP18顶部的WLP28。与WLP18类似，所述WLP28中包括裸芯片22、胶体24、重布线层25以及凸点27。所述WLP18的顶部设有重布线层19，所述WLP18的胶体14中设有垂直互连通道(Vertical Interconnect System)13。所述WLP28的重布线层25和凸点27。通过所述重布线层25中的金属层、凸点27、WLP18的重布线层19中的金属层、硅穿孔13以及所述WLP18中的重布线层15，所述WLP28与所述WLP18之间建立起信号通路。
在3D封装技术中，通过将两个WLP叠加在一起能有效地缩短两个裸片之间的信号通道的长度，但这也带来了新的问题。首先，两个WLP叠加在一起会带来较为严重的散热问题；其次硅穿孔的工艺难度较高，带来了较大的工艺成本。
发明内容
有鉴于此，本发明实施例提供一种能够实现裸芯片间短距离互联但不会带来散热问题的芯片。
本发明实施例第一方面提供一种芯片，其包括载体、重布线结构和多个封装功能模块，所述多个封装功能模块均有至少一部分被胶体包裹，并被并行固定在所述重布线结构上，所述重布线结构被固定在所述载体上，所述重布线结构中包括一层或多层重布线金属层，所述重布线金属层将所述多个封装功能模块与所述载体通信连接，所述重布线结构中还包括一层或多层互连金属层，所述互连金属层与至少两个封装功能模块通信连接，以在至少两个封装功能模块间提供信号通路。
在第一种可能的实现方式中，所述重布线结构的主体由绝缘材料构成，所述互连金属层在所述主体内与所述重布线金属层相独立。
结合第一方面和第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述多个封装功能模块上设有管脚，所述管脚被排布于所述封装功能模块和重布线结构之间，并与所述重布线金属层或所述互连金属层电性连接。
结合第一方面、第一方面的第一种可能的实现方式或第一方面的第二种可能的实现方式中，在第三种可能的实现方式中，所述重布线结构的主体设有凸点阵列，所述凸点阵列与所述载体以及所述重布线金属层电性连接。
结合第一方面，以及第一方面的第三种可能的实现方式中，在第四种可能的实现方式中，在所述重布线结构和所述载体之间、所述凸点阵列的间隙和周围填充有填充胶。
结合第一方面，以及从第一方面的第一种可能的实现方式到第一方面的第四种可能的实现方式中的任意一种实现方式，在第五种可能的实现方式中，所述载体的底部设有焊盘或者连接器。
结合第一方面，以及从第一方面的第一种可能的实现方式到第一方面的第五种可能的实现方式中的任意一种实现方式，在第六种可能的实现方式中，所述多个封装功能模块与所述载体相背离的一侧裸露在胶体外。
结合第一方面，以及从第一方面的第六种可能的实现方式，在第七种可能的实现方式中，所述多个封装功能模块的与所述载体相背离的一侧表面涂覆有导热胶，且所述芯片还包括散热片，所述散热片贴附在所述多个封装功能模块的与所述载体相背离的一侧的表面。
结合第一方面，以及第一方面的第七种可能的实现方式，在第八种可能的实现方式中，所述散热片包括贴附于所述多个封装功能模块的顶部的第一部，以及环绕所述多个封装功能模块、并被粘合剂固定在所述载体的表面上的第二部。
结合第一方面，以及从第一方面的第一种可能的实现方式到第一方面的第五种可能的实现方式中的任意一种，在第九种可能的实现方式中，所述芯片还包括环形散热片，所述散热片环绕所述封装功能模块设置，并被粘合剂固定在载体上。
结合第一方面，以及从第一方面的第一种可能的实现方式到第一方面的第九种可能的实现方式中的任意一种，在第十种可能的实现方式中，所述互连金属层中包括第一互连金属层和第二互连金属层，所述第一互连金属层的一部分和第二互连金属层的一部分互相平行，在所述第一互连金属层和第二互连金属层的相互平行的部分之间设有参考金属层，所述参考金属层与所述重布线结构中的其他金属层绝缘。
结合第一方面，以及从第一方面的第一种可能的实现方式到第一方面的第十种可能的实现方式中的任意一种，在第十一种可能的实现方式中，所述封装功能模块可以是下列中的任意一种：裸芯片、堆栈裸芯片和经过封装芯片。
在本发明实施例提供的芯片中，两个封装功能模块被并行放置到载体上，并通过重布线结构来建立彼此之间的信号通路。不存在由叠加引起的散热问题，而且能够有效地保证封装功能模块间的信号通路的长度不会过长。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1所示为现有技术的一种芯片的截面视图；
图2所示为本发明实施例的芯片的截面视图；
图3a和图3b所示为本发明实施例的芯片中的裸芯片的管脚通过互连金属层进行互连的视图。
图4所示为本发明又一实施例的芯片的截面视图；
图5所示为本发明第三实施例中的芯片的截面视图；
图6a-6d所示为本发明实施例中装备了各种类型散热片的芯片的截面视图；以及
图7所示为本发明实施例的装备了环形散热片的芯片的截面视图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供一种新形式的芯片。在本发明中，多个裸芯片(Die)被并行封装在芯片的载体表面，在重布线结构中则直接搭建裸芯片之间的数据通路。通过这种方式，一方面能够有效缩短裸芯片间的数据通路的长度；另一方面由于没有堆叠芯片间的互相影响，能够获得更好的散热效果。
图2所示为本发明第一实施例提供的芯片200的示意图。芯片200包括载体220，重布线结构240和多个裸芯片260，在本发明实施例中多个裸芯片是指两个或两个以上裸芯片，比如图1中所示的芯片即包括两个裸芯片。所述多个裸芯片260被并行固定在所述重布线结构240的顶部。而所述重布线结构240则被固定在所述载体220的顶部。
在本发明实施例中，封装在一个芯片中的多个裸芯片可以为同质芯片，也可以为异质芯片，比如可以将模拟裸芯片和数字裸芯片封装在一起；也可以将在不同晶圆工艺节点下生产的裸芯片封装在一起；或者将不同功能的裸芯片封装在一起。在本发明实施例中至少两个裸芯片260被胶体262包裹，并被并行固定在所述重布线结构240的顶部。图1中所示的重布线结构240为矩形结构，其顶部平坦，而在实际应用中可能会出现不规则形状的重布线结构240，从而使得用于固定裸芯片260的顶部会存在高低差，而本发明实施例中所述的将至少两个裸芯片260并行固定在重布线结构240的顶部并不意味着裸芯片260需要平行布置，而仅仅是指在芯片中有至少两个裸芯片之间不存在叠加关系，而是被“平等地”固定在所述重布线结构240的表面。
所述重布线结构240的主体由绝缘材料构成，其内部和表面穿插有一个或多个重布线金属层242。所述重布线金属层242逐层排布成一个或多个树型结构，相邻层之间通过镀通孔250进行电性连接。处于所述重布线结构240顶部的重布线金属层与所述裸芯片260的信号管脚贴附在一起。所述重布线结构240的底部则布设有凸点阵列245，从而以焊锡的方式将所述重布线结构240固定在载体220上，并在裸芯片260和载体220之间形成信号通路。在在重布线结构240中，多个重布线金属层242组成多个树型结构，每个树型结构由多个重布线金属层242以及重布线金属层之间的镀通孔组成。这些树型结构在重布线结构240的内部彼此不连接，它们各自联通对应的裸芯片的信号管脚和重布线结构240底部的凸点，从而在重布线结构内部构成不同的信号路径。
进一步的，可以在所述重布线结构240和所述载体之间填充填充胶(Underfill)262，这样有助于缓解焊球上的应力，提高封装的可靠性。
在本发明实施例中，所述重布线结构240还包括一个或多个互连金属层244。所述互联金属层244在重布线结构240的中与重布线金属层242相互独立，即互联金属层与重布线金属层在重布线结构240中不相接。所述互联金属层也不与重布线结构240底部的凸点联通。所述互连金属层244中的任意一个通过镀通孔分别直接或间接的与两个不同的裸芯片260的管脚电性连接，以在两个裸芯片之间建立信号通路。
本发明提供的芯片通过将裸芯片260并行设置在重布线结构240上，避免了裸芯片叠加带来的散热问题。同时，通过互连金属层244的设计使得裸芯片间直接通过重布线结构240进行数据通信，工艺简单，且设计难度低，有效地降低了工艺成本。
进一步的，在可选择的实施例中，如图1和图2所示，所述互连金属层244包括用于连接两个裸芯片的不同管脚的第一互连金属层2442和第二互连金属层2444。所述第一互连金属层2442的一部分和第二互连金属层2444的一部分在所述重布线结构240中相互靠近且平行，这样的话，第一互连金属层2442和第二互连金属层244间可能会产生信号串扰，影响信号传输质量。要解决这一问题，可以在所述重布线结构240内部、第一互连金属层2442和第二互连金属层2444之间设置与两个互连金属层平行的参考金属层2446，所述参考金属层2446被重布线结构的介质层包围，所述参考金属层与重布线结构中的其他金属层绝缘。
本发明实施例提供的芯片中的裸芯片和重构布线层可以通过以下工艺制造：
步骤1：通过晶圆切割的方式在原始晶圆上切割出至少两个裸芯片；
步骤2：将切割出来的裸芯片重构(Reconstitution)在预定大小尺寸的承载体上。
需要注意的是，裸芯片间的间距会影响裸芯片之间的高密度互连的性能，在工艺允许的情况下，尽量缩短裸芯片间的间距，比如50um以下。
步骤3：通过模塑的方式形成胶体对裸芯片进行包裹。
在胶体将裸芯片包裹之后需要通过一定的工艺处理方法使得裸芯片与重布线结构相对应的一侧裸露出来。比如，使用研磨的方法；或者在模塑的过程中通过临时载体遮住裸芯片的相应位置，待包裹完成后直接去掉载体即可。
步骤4：通过重布线(Redistribution)工艺在裸芯片的与重布线结构相对应的一侧上制作出重布线结构。
其中，重布线结构的主体介质可以为绝缘的、可曝光显影的有机介质构成，比如聚酰亚胺(Polyimide，简称PI)，聚对苯撑苯并双口恶唑(Poly-p-phenylenebenzobisthiazole，简称PBO)或环氧树脂基的聚合物(Epoxy Based Polymer)。而重布线金属层和互连金属层则可以在主体介质的基础上通过溅射、电镀等工艺制作，使用的材料可以为铜。金属层的最小线宽线距可分别为线宽2um/线距2um至线宽1um/线距1um或更小。而在该主体介质上可以制作镀铜孔从而实现不同重布线金属层之间的互连，镀铜孔的孔(Via)和孔盘(Via Land)的直径分别可达5um/10um或更小。
待裸片、胶体和重布线结构被生成之后，可以采用热风重熔(Mass Reflow)或热压键合(Thermo Compression Bonding)等方式将重布线结构贴合在基板上。底部填充胶可以根据需要在重布线结构与基板之间施加，来缓解重布线结构的凸点上的应力，以提高封装的可靠性。基板可以为多层基板，通过激光钻孔Laser Drill或机械钻孔Mechanical Drill并镀铜等方式实现层之间的信号互通。基板的底部布设有焊盘，以通过钎料球(SolderBall)与PCB接合。在其他实施方式中，基板底部也可以通过可插拔连接器(Socket)的方式与PCB接合。
多层基板的采用，可以显著增加封装的布线资源，并且通过尺寸规格较大的基板能够实现更大的管脚数，改善封装的电源完整性，同时还可大幅度改善封装的板级可靠性。在此基础上，本发明中通过重布线结构中的多层重布线金属层的利用，能够降低对基板的层数上的需求，进而降低封装的成本。
在实际应用中，裸芯片除了贴近重布线结构的一侧可能都在胶体的包裹下。不过，为了进一步提高散热效率，可以对裸芯片远离重布线结构的一侧进行暴露处理，比如研磨(Grinding)，以使裸芯片远离重布线结构的一侧暴露出来，提高散热效率。具体如图4所示。当然也可以在对裸芯片包裹时，使用载体来避免裸芯片的这一侧被胶体覆盖。
为了更进一步的提高散热效率，可以如图5所示，在裸芯片远离重布线结构的一侧表面上涂上导热胶，然后贴上散热片30。图5所示的散热片为帽型结构，其整体弯折且末段被粘合剂粘贴于载体220上。通过这种形状的散热片，一方面可以促进裸片热量的散发；另一方面，将所有裸芯片一并包裹住，作为进一步的限位，能有效地提高封装结构的稳定性。当然，散热片的形状其实可以有其他各种形式。比如，图6a所示的散热片为一体成型的的锻造式散热片，如图6b所示的散热片则为由通过后期加工手段将至少两部分散热金属片结合在一起的两片式散热片。图6c则是在图6a或者图6b的散热片的基础上通过凸台垫高了贴附于裸芯片的部分。
更或者，如图6d所示，还可以使用环形散热片(Ring Lid)，在这种情况下裸芯片远离重布线结构的一层仍需要暴露出胶体之外，而环形散热片环绕裸芯片排布并被粘合剂固定在载体上。在主板上应用时，裸芯片暴露一侧和环形散热片顶部一侧可以贴外置散热器，从而获得较好的散热效果。
在上述各实施例中，一直都以对两个或两个以上的裸芯片的封装为例进行说明，但实际上本发明的芯片不限于仅对裸芯片进行封装，可以用于各种待封装的封装功能模块中，该待封装的封装功能模块可以为上述实施例中的裸芯片，也可以为堆栈裸芯片(StackDies)构成的功能性模组，甚至是已经经过一次封装的“芯片”。如图7所示的就是基于本发明实施例中所述的封装结构的又一类型芯片的示意图。在该芯片500中包括承载在重布线结构400上的裸芯片560和堆栈裸芯片580。可以理解，在可选择的实施方式中，本发明实施例的芯片中封装的功能模块可以为各种类型的功能模块间的任意组合，比如裸芯片和堆栈裸芯片，裸芯片和至少经过一次封装的芯片，堆栈裸芯片和至少经过一次封装的芯片。而且，在芯片中封装的功能模块的数量也可以根据需要进行调整，而不仅局限于上述实施例中的仅并行封装两个功能模块(裸芯片)。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

1.一种芯片，其特征在于，包括载体、重布线结构和多个封装功能模块，所述多个封装功能模块均有至少一部分被胶体包裹，并被并行固定在所述重布线结构上，所述重布线结构被固定在所述载体上，所述重布线结构中包括一层或多层重布线金属层，所述重布线金属层将所述多个封装功能模块与所述载体通信连接，所述重布线结构中还包括一层或多层互连金属层，所述互连金属层在所述重布线结构上与至少两个封装功能模块通信连接，以在至少两个封装功能模块间提供信号通路,
所述互连金属层中包括第一互连金属层和第二互连金属层，所述第一互连金属层的一部分和第二互连金属层的一部分互相平行，在所述第一互连金属层和第二互连金属层的相互平行的部分之间设有参考金属层，所述参考金属层与所述重布线结构中的其他金属层绝缘，所述封装功能模块是下列中的任意一种：裸芯片、堆栈裸芯片和经过封装的芯片。
2.如权利要求1所述的芯片，其特征在于，所述重布线结构的主体由绝缘材料构成，所述互连金属层在所述主体内与所述重布线金属层相独立。
3.如权利要求1或2所述的芯片，其特征在于，所述多个封装功能模块的朝向所述重布线结构的表面上设有管脚，所述管脚与所述重布线金属层或所述互连金属层电性连接。
4.如权利要求1所述的芯片，其特征在于，所述重布线结构的主体设有凸点阵列，所述凸点阵列与所述载体以及所述重布线金属层电性连接。
5.如权利要求4所述的芯片，其特征在于，在所述重布线结构和所述载体之间、所述凸点阵列的间隙和周围填充有填充胶。
6.如权利要求1所述的芯片，其特征在于，所述载体的底部设有焊盘或者连接器。
7.如权利要求1所述的芯片，其特征在于，所述多个封装功能模块与所述载体相背离的一侧裸露在胶体外。
8.如权利要求7所述的芯片，其特征在于，所述多个封装功能模块的与所述载体相背离的一侧表面涂覆有导热胶，且所述芯片还包括散热片，所述散热片贴附在所述多个封装功能模块的与所述载体相背离的一侧的表面。
9.如权利要求8所述的芯片，其特征在于，所述散热片包括贴附于所述多个封装功能模块的顶部的第一部，以及环绕所述多个封装功能模块、并被粘合剂固定在所述载体的表面上的第二部。
10.如权利要求1所述的芯片，其特征在于，所述芯片还包括环形散热片，所述散热片环绕所述封装功能模块设置，并被粘合剂固定在载体上。
CN201580078921.2A 2015-04-14 2015-04-14 一种芯片 Active CN108140632B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/076562 WO2016165074A1 (zh) 2015-04-14 2015-04-14 一种芯片

Publications (2)

Publication Number Publication Date
CN108140632A CN108140632A (zh) 2018-06-08
CN108140632B true CN108140632B (zh) 2020-08-25

Family

ID=57125607

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580078921.2A Active CN108140632B (zh) 2015-04-14 2015-04-14 一种芯片

Country Status (6)

Country Link
US (1) US10475741B2 (zh)
EP (1) EP3255668A4 (zh)
KR (1) KR102008854B1 (zh)
CN (1) CN108140632B (zh)
BR (1) BR112017018820A2 (zh)
WO (1) WO2016165074A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106684066B (zh) * 2016-12-30 2020-03-10 华为技术有限公司 一种封装芯片及基于封装芯片的信号传输方法
US11101209B2 (en) 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US20200168527A1 (en) * 2018-11-28 2020-05-28 Taiwan Semiconductor Manfacturing Co., Ltd. Soic chip architecture
US11908758B2 (en) 2020-12-29 2024-02-20 Samsung Electronics Co., Ltd. Semiconductor package including dual stiffener
CN112802764B (zh) * 2020-12-31 2024-03-26 上海易卜半导体有限公司 封装件及其形成方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1158006A (zh) * 1995-11-30 1997-08-27 洛克希德马汀公司 具有降低应力成模衬底部分的挠性层的高密度互连电路模件
CN2591772Y (zh) * 2002-12-26 2003-12-10 威盛电子股份有限公司 芯片封装结构
CN101256997A (zh) * 2008-03-05 2008-09-03 日月光半导体制造股份有限公司 可降低封装应力的封装构造
CN101315919A (zh) * 2007-07-30 2008-12-03 日月光半导体制造股份有限公司 芯片封装结构及其工艺
CN101593734A (zh) * 2008-05-27 2009-12-02 联发科技股份有限公司 倒装芯片封装及半导体芯片封装
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
DE10250538B4 (de) * 2002-10-29 2008-02-21 Infineon Technologies Ag Elektronisches Bauteil als Multichipmodul und Verfahren zu dessen Herstellung
JP4413174B2 (ja) * 2004-09-01 2010-02-10 三洋電機株式会社 アンテナ一体型回路装置
US7326592B2 (en) * 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
JP4072697B2 (ja) * 2006-05-02 2008-04-09 セイコーエプソン株式会社 半導体装置
US7910385B2 (en) * 2006-05-12 2011-03-22 Micron Technology, Inc. Method of fabricating microelectronic devices
US7535110B2 (en) * 2006-06-15 2009-05-19 Marvell World Trade Ltd. Stack die packages
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7767496B2 (en) * 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8120186B2 (en) * 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
TWI362732B (en) * 2008-04-07 2012-04-21 Nanya Technology Corp Multi-chip stack package
US8310051B2 (en) 2008-05-27 2012-11-13 Mediatek Inc. Package-on-package with fan-out WLCSP
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
TWI387077B (zh) * 2008-06-12 2013-02-21 Chipmos Technologies Inc 晶粒重新配置之封裝結構及其方法
US7659145B2 (en) 2008-07-14 2010-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
KR20100056247A (ko) * 2008-11-19 2010-05-27 삼성전자주식회사 접착층을 구비하는 반도체 패키지
JP5503208B2 (ja) * 2009-07-24 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP5801531B2 (ja) * 2009-10-16 2015-10-28 ルネサスエレクトロニクス株式会社 半導体パッケージ及びその製造方法
US9024431B2 (en) * 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8115293B2 (en) * 2009-12-08 2012-02-14 Stats Chippac Ltd. Integrated circuit packaging system with interconnect and method of manufacture thereof
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8535980B2 (en) 2010-12-23 2013-09-17 Stmicroelectronics Pte Ltd. Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
US8389333B2 (en) 2011-05-26 2013-03-05 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
CN107720689A (zh) * 2011-06-30 2018-02-23 村田电子有限公司 系统级封装器件的制造方法和系统级封装器件
JP5741306B2 (ja) * 2011-08-10 2015-07-01 富士通株式会社 電子装置及びその製造方法
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9691706B2 (en) 2012-01-23 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip fan out package and methods of forming the same
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US20130249101A1 (en) 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US20130256883A1 (en) 2012-03-27 2013-10-03 Intel Mobile Communications GmbH Rotated semiconductor device fan-out wafer level packages and methods of manufacturing rotated semiconductor device fan-out wafer level packages
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8878360B2 (en) 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US9165887B2 (en) * 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
GB2509296B (en) * 2012-09-25 2016-10-26 Cambridge Silicon Radio Ltd Composite reconstituted wafer structures
US8624376B1 (en) 2012-10-10 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure without through assembly vias
US8987918B2 (en) * 2013-03-14 2015-03-24 Intel Corporation Interconnect structures with polymer core
US8927412B1 (en) * 2013-08-01 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package and method of formation
TWI582913B (zh) * 2013-08-02 2017-05-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9006584B2 (en) * 2013-08-06 2015-04-14 Texas Instruments Incorporated High voltage polymer dielectric capacitor isolation device
US9153560B2 (en) * 2014-01-22 2015-10-06 Qualcomm Incorporated Package on package (PoP) integrated device comprising a redistribution layer
US9252135B2 (en) * 2014-02-13 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9455158B2 (en) * 2014-05-30 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
CN104064551B (zh) 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备
US9305877B1 (en) * 2014-10-30 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package with through substrate vias
US9659863B2 (en) * 2014-12-01 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, multi-die packages, and methods of manufacture thereof
US9484307B2 (en) * 2015-01-26 2016-11-01 Advanced Semiconductor Engineering, Inc. Fan-out wafer level packaging structure
US10600759B2 (en) * 2016-01-12 2020-03-24 Advanced Semiconductor Engineering, Inc. Power and ground design for through-silicon via structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1158006A (zh) * 1995-11-30 1997-08-27 洛克希德马汀公司 具有降低应力成模衬底部分的挠性层的高密度互连电路模件
CN2591772Y (zh) * 2002-12-26 2003-12-10 威盛电子股份有限公司 芯片封装结构
CN101315919A (zh) * 2007-07-30 2008-12-03 日月光半导体制造股份有限公司 芯片封装结构及其工艺
CN101256997A (zh) * 2008-03-05 2008-09-03 日月光半导体制造股份有限公司 可降低封装应力的封装构造
CN101593734A (zh) * 2008-05-27 2009-12-02 联发科技股份有限公司 倒装芯片封装及半导体芯片封装
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装

Also Published As

Publication number Publication date
EP3255668A1 (en) 2017-12-13
CN108140632A (zh) 2018-06-08
EP3255668A4 (en) 2018-07-11
BR112017018820A2 (zh) 2018-04-24
US10475741B2 (en) 2019-11-12
KR20170117528A (ko) 2017-10-23
WO2016165074A1 (zh) 2016-10-20
KR102008854B1 (ko) 2019-08-08
US20180025973A1 (en) 2018-01-25

Similar Documents

Publication Publication Date Title
US10068879B2 (en) Three-dimensional stacked integrated circuit devices and methods of assembling the same
US9412678B2 (en) Structure and method for 3D IC package
CN116169110A (zh) 一种芯片及封装方法
TWI496270B (zh) 半導體封裝件及其製法
US20130277855A1 (en) High density 3d package
CN108140632B (zh) 一种芯片
US9847284B2 (en) Stacked wafer DDR package
US20130058067A1 (en) System with a high power chip and a low power chip having low interconnect parasitics
TW202245206A (zh) 晶圓級堆疊晶片封裝及製造其之方法
CN104037153A (zh) 3d封装件及其形成方法
KR101605600B1 (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
CN104517930A (zh) 半导体封装
CN104377171A (zh) 具有中介层的封装件及其形成方法
US9786588B2 (en) Circuit substrate and package structure
US10490506B2 (en) Packaged chip and signal transmission method based on packaged chip
CN104867908A (zh) 倒装芯片堆叠封装
CN110581107A (zh) 半导体封装及其制造方法
TWI416700B (zh) 晶片堆疊封裝結構及其製造方法
US20120168936A1 (en) Multi-chip stack package structure and fabrication method thereof
JP5767695B2 (ja) 半導体装置
US8546187B2 (en) Electronic part and method of manufacturing the same
CN116646335A (zh) 一种封装互联结构、制备方法及电子系统
US20180102346A1 (en) Semiconductor device
WO2014171403A1 (ja) 半導体装置
JP2013110264A (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant