CN104867908A - 倒装芯片堆叠封装 - Google Patents
倒装芯片堆叠封装 Download PDFInfo
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- CN104867908A CN104867908A CN201410283489.8A CN201410283489A CN104867908A CN 104867908 A CN104867908 A CN 104867908A CN 201410283489 A CN201410283489 A CN 201410283489A CN 104867908 A CN104867908 A CN 104867908A
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- 239000010937 tungsten Substances 0.000 description 1
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Abstract
本发明提供一种倒装芯片堆叠封装,一中介层应用于该倒装芯片堆叠封装中,用以连接一第一芯片与一第二芯片,该中介层包括:一第一接合面及对应的一第二接合面;多个导电贯孔贯穿第一接合面及第二接合面;一第一散热金属层配置于第一接合面上;以及一第二散热金属层配置于第二接合面上。其中第一散热金属层与第二散热金属层与导电贯孔电性隔离,且相邻的导电贯孔之间,在第一接合面上具有第一散热金属层,在第二接合面上具有第二散热金属层。第一芯片配置于第一接合面上,第二芯片配置于第二接合面上,第一芯片与第二芯片是借由导电贯孔电性连接。
Description
技术领域
本发明是有关于一种堆叠封装,且特别是有关于一种以倒装芯片方式,可以提高散热效果的倒装芯片堆叠封装。
背景技术
随着电子产品的轻薄化,半导体芯片的积集度与高密度半导体封装的需求也对应提高。堆叠芯片半导体封装(stacked chip package),系统级封装(system inpackage),可以将多个芯片容纳于一封装中,提高封装密度,因此近年来被广泛地应用于许多电子产品中。在半导体封装技术中,倒装芯片技术(flip chip)使得芯片的接点可以阵列式排列,对于高脚位数的芯片提供与封装基板间极佳的接合方式。而这些高积集度的芯片与高密度的封装结构,在操作时会产生相对更多的热能,因此如何解决半导体封装的散热问题,一直是个重要课题。
已知半导体封装的散热方式,通常会在封装外部增设一散热片,比如一散热金属片配置于封装外部,以达到散热的需求,然而,该种散热方式运用于堆叠芯片的封装结构时,底层芯片的散热效率则相对顶层芯片较差。
发明内容
本发明的目的之一就是在于提供一种倒装芯片堆叠封装,直接利用中介层形成散热结构,提供低热阻的散热途径。
根据本发明的上述及其他目的,提供一种倒装芯片堆叠封装,包括:一封装基板、一第一芯片、一中介层以及一第二芯片。封装基板具有一内表面及对应的一外表面,内表面具有至少一内接点,外表面具有至少一外接点,内接点与外接点电性连接。第一芯片具有一第一有源表面及对应的一第一背面,第一有源表面具有至少一第一接点,第一背面至少具有一第二接点,第一接点与第二接点电性连接,第一芯片以第一有源表面贴附于内表面,使得第一接点与内接点电性连接。中介层具有一第一接合面及对应的一第二接合面,中介层具有至少一导电贯孔贯穿第一接合面及第二接合面,第一接合面具有一第一散热金属层,第二接合面具有一第二散热金属层,其中第一散热金属层与第二散热金属层与导电贯孔电性隔离,中介层的第一接合面与第一背面贴合,并使得导电贯孔与第二接点电性连接。第二芯片具有一第二有源表面,第二有源表面具有至少一第三接点,第二芯片以第二有源表面贴附于第二接合面,使得第三接点与导电贯孔电性连接。
在本发明的一个或多个实施例中,第二芯片更包括对应第二有源表面的一第二背面,倒装芯片堆叠封装更包括一散热片配置于第二背面上,且与第二散热金属层连接。
在本发明的一个或多个实施例中,中介层的第一接合面与第一背面贴合,使得第一散热金属层与第一背面导热性接合。
在本发明的一个或多个实施例中,第一芯片与封装基板是以倒装芯片方式接合,且第一有源表面与内表面之间更包括一第一底填材料。
在本发明的一个或多个实施例中,第二芯片与中介层是以倒装芯片方式接合,且该第二有源表面与第二表面之间更包括一第二底填材料。
在本发明的一个或多个实施例中,倒装芯片堆叠封装更包括一焊球配置于外接点上且与外接点电性连接。
根据本发明的上述及其他目的,提出一种倒装芯片堆叠封装,包括:一中介层,一第一芯片,以及一第二芯片。中介层具有一第一接合面及对应的一第二接合面,中介层具有多个导电贯孔贯穿第一接合面及第二接合面,第一接合面上具有一第一散热金属层,第二接合面上具有一第二散热金属层,其中,第一接合面及第二接合面上相邻的导电贯孔之间分别具有第一散热金属层及第二散热金属层,以及第一散热金属层及第二散热金属层分别与导电贯孔电性隔离。第一芯片具有一第一表面,第一表面具有多个第一接点,第一芯片以第一表面贴附于第一接合面,使得第一接点分别与导电贯孔电性连接,且第一表面与第一散热金属层导热性接合。第二芯片具有一第二表面,第二表面具有多个第二接点,第二芯片以第二表面贴附于第二接合面,使得第二接点分别与导电贯孔电性连接,且第二表面与第二散热金属层导热性接合。
在本发明的一个或多个实施例中,第一芯片更具有对应第一表面的一第三表面,且第三表面具有多个第三接点,每一第三接点分别与对应的第一接点其中之一电性连接,其中第一芯片以第三表面与一封装基板,以倒装芯片方式接合,且第三接点与封装基板电性连接。
在本发明的一个或多个实施例中,第一芯片更具有对应第一表面的一第三表面,且第三表面具有多个第三接点,每一第三接点分别与对应的第一接点其中之一电性连接,倒装芯片堆叠封装更包括:一第二中介层,具有一第三接合面及对应的一第四接合面,中介层具有多个第一导电贯孔贯穿第三接合面及第四接合面,第三接合面具有一第三散热金属层,第四接合面具有一第四散热金属层,其中第三散热金属层与第四散热金属层与第一导电贯孔电性隔离,且相邻的第一导电贯孔之间,在第三接合面上具有第三散热金属层,在第四接合面上具有第四散热金属层,且第一芯片以第三表面贴附于第三接合面,使得第三接点分别与第一导电贯孔电性连接,且该第三表面与第三散热金属层导热性接合。
在本发明的一个或多个实施例中,第一芯片与一封装基板接合,且第二芯片与另一中介层接合。
根据本发明的上述及其他目的,提出一种中介层,用以连接一第一芯片与一第二芯片,中介层包括:一第一接合面及对应的一第二接合面;多个导电贯孔贯穿第一接合面及第二接合面;一第一散热金属层配置于第一接合面上;以及一第二散热金属层配置于第二接合面上。其中第一散热金属层与第二散热金属层与导电贯孔电性隔离,且在相邻的导电贯孔之间,在第一接合面上具有第一散热金属层,在第二接合面上具有第二散热金属层。第一芯片配置于第一接合面上,第二芯片配置于第二接合面上,第一芯片与第二芯片是借由导电贯孔电性连接。
在本发明的一个或多个实施例中,第一芯片及第二芯片与中介层导热性接合。
本发明的倒装芯片堆叠封装,在堆叠的芯片之间插入中介层,且在中介层上形成散热金属层,可以直接利用中介层形成散热结构,提供芯片低热阻的散热途径。借此,可以明显改善倒装芯片堆叠封装的散热效率,且结构简单,可以降低制造成本。
附图说明
图1至图4绘示依照本发明一实施例的一种倒装芯片堆叠封装制造方法各步骤的剖面示意图。
图5绘示依照本发明另一实施例的一种倒装芯片堆叠封装的剖面示意图。
图6绘示依照本发明再一实施例的一种倒装芯片堆叠封装的剖面示意图。
图7绘示依照本发明一实施例,一种倒装芯片堆叠封装的中介层的俯视示意图。
图8绘示依照本发明一实施例,一种倒装芯片堆叠封装的中介层的俯视示意图。
关于本发明的优点,精神与特征,将以实施例并参照所附附图,进行详细说明与讨论。值得注意的是,为了让本发明能更容易理解,后附的附图仅为示意图,相关尺寸并非以实际比例绘示。
【附图标记说明】
100:封装基板 122:第一散热金属层
100A:内表面 124:第二散热金属层
100B:外表面 126:导电贯孔
102:内接点 128:导电凸块
104:外接点 130:第二芯片
110:第一芯片 130A:第二有源表面
110A:第一有源表面 130B:第二背面
110B:第一背面 132:第三接点
112:第一接点 134:底填材料
114:第二接点 136:焊球
116:底填材料 140:芯片
120:中介层 150:中介层
120A:第一接合面 160:散热片
120B:第二接合面 162:导热胶
具体实施方式
为了让本发明的优点,精神与特征可以更容易且明确地了解,后续将以实施例并参照所附附图进行详述与讨论。值得注意的是,这些实施例仅为本发明代表性的实施例,其中所举例的特定方法,装置,条件,材质等并非用以限定本发明或对应的实施例。
请参照图1至图4,图1至图4绘示依照本发明一实施例的一种倒装芯片堆叠封装制造方法各步骤的剖面示意图。本发明的倒装芯片堆叠封装的制造方法系包括下列步骤:首先请先参照图1,提供一封装基板100,封装基板100具有一内表面100A及对应的一外表面100B,内表面100A具有多个内接点102,外表面100B具有多个外接点104,每一内接点102分别与外接点104其中之一电性连接。详细而言,封装基板100可以为印刷电路基板(PCB substrate),比如由多层的环氧树脂(epoxy)绝缘层及图案化铜箔层(patterned copper foil),交互叠合而成,而其中有导电贯孔(conductive via)或导电盲孔(conductive blind via)连接各图案化铜箔层。因此内接点102,比如为焊垫(bonding pad)可以借由图案化铜箔层,导电贯孔及导电盲孔,电性连接外接点104,比如为焊球垫(solder ballpad)。
请参照图2,接着进行一倒装芯片工艺,将第一芯片110以倒装芯片的方式与封装基板100进行接合。第一芯片110具有一第一有源表面110A及对应的一第一背面110B,第一有源表面110A具有第一接点112,第一背面110B具有第二接点114,第一接点112与第二接点114电性连接,第一芯片110以第一有源表面110A贴附于内表面100A,使得第一接点112与内接点102电性连接。详细而言,第一芯片110在第一有源表面110A上会形成多个焊垫(bondingpad,未绘示),比如以阵列方式排列,并在其上分别生成导电凸块(conductivebump),以形成图2中的第一接点112。而第一背面110B上的第二接点114,比如是如上所述的焊垫,系通过第一芯片110内部的金属内连线与第一接点112电性连接。为了防止芯片与封装基板之间的热膨胀系数差异所造成的热应力,影响第一接点112(导电凸块)的可靠度,较佳是进行一底填步骤(under-filling),填入一底填材料116于第一芯片110与封装基板100之间,以保护导电凸块。
请参照图3,接着进行中介层120与第一芯片110的接合。中介层120具有一第一接合面120A及对应的一第二接合面120B,中介层120具有至少一导电贯孔126贯穿第一接合面120A及第二接合面120B。第一接合面120A具有一第一散热金属层122,第二接合面120B具有一第二散热金属层124,其中第一散热金属层122与第二散热金属层124与导电贯孔126电性隔离。中介层120的第一接合面120A与第一背面110B贴合,并使得导电贯孔126与第二接点114电性连接。详细来说,中介层120的材质比如是硅,或者其他半导体或绝缘材质,较佳是具有与芯片相近热膨胀系数的材质。而导电贯孔126可以利用直通硅晶穿孔技术(Through Silicon Via,TSV)形成导电贯孔126,比如在中介层120形成多个贯穿孔,然后再填入导电材料,比如是金属材料,包括铜、铝、钨、钛、钴、铬及其组合等,以形成导电贯孔126。其中形成贯穿孔的方法包括光刻蚀刻,而填入导电材料的方法包括物理气相沉积(PVD)、电镀等。而第一散热金属层122及第二散热金属层124可以利用电镀的方式形成,其材质比如是铜或铁镍合金,或者其他金属材料,较佳是具有高导热系数的金属材料。导电贯孔126是借由导电凸块128与第一芯片110的第二接点114电性连接。同样地,可以进行一底填步骤(under-filling),填入一底填材料118于第一芯片110与中介层120之间,以保护导电凸块128。
请参照图4,接着堆叠第二芯片130在中介层120上。第二芯片130具有一第二有源表面130A,第二有源表面130A具有至少一第三接点132,第二芯片130以第二有源表面130A贴附于第二表面120B,使得第三接点132与导电贯孔126电性连接。详细而言,第二芯片130在第二有源表面130A上会形成多个焊垫(bonding pad,未绘示),比如以阵列方式排列,并在其上分别生成导电凸块(conductive bump),以形成图4中的第三接点132。同样地,可以进行一底填步骤(under-filling),填入一底填材料134于第二芯片130与中介层120之间,以保护导电凸块。本发明的倒装芯片堆叠封装更包括一焊球136配置于外接点104上,且与外接点104电性连接,以利倒装芯片堆叠与外部的印刷电路板(或主机板)电性连接。
值得一提的是,底填材料118,134较佳是导热性较好的材料,借此中介层120第一接合面120A可以与第一芯片110的第一背面110B导热性接合,亦即第一散热金属层122与第一芯片110的第一背面110B导热性接合。同样地,第二散热金属层124与第二芯片130的第二有源表面130A导热性接合。因此,第一芯片110与第二芯片130在操作时所产生的热,可以借由中介层120的第一散热金属层122,第二散热金属层124散热。
请同时参照图7,图7绘示依照本发明一实施例,一种倒装芯片堆叠封装的中介层的俯视示意图。上述实施例中,中介层120中第一散热金属层122,第二散热金属层124的配置方式可以是如图7所示。第二散热金属层124配置于中介层120的外围,而与导电贯孔126间隔一适当距离,第一散热金属层122的配置亦然。然而较佳的是第一散热金属层122可以与第一芯片110在中介层120上的垂直投影有部分重叠,亦即底填材料118可以连接第一芯片110及第一散热金属层122,以利导热。同样地,第二散热金属层124可以与第二芯片130在中介层120上的垂直投影有部分重叠,亦即底填材料134可以连接第二芯片130及第二散热金属层124,以利导热。
请参照图8,图8绘示依照本发明一实施例,一种倒装芯片堆叠封装的中介层的俯视示意图。上述实施例中,中介层120中第一散热金属层122,第二散热金属层124的配置方式可以是如图8所示。第二散热金属层124配置于中介层120的整个表面(第二接合面120B),而与每个导电贯孔126保持一间距,而形成电性隔离,第一散热金属层122的配置亦然。借此,第一芯片110或第二芯片130通过底填材料118,134连接第一散热金属层122,第二散热金属层124的面积更大,可以更加提高散热效果。
请参照图5,图5绘示依照本发明另一实施例的一种倒装芯片堆叠封装的剖面示意图。虽然上述实施例中仅以二个芯片的堆叠作为实例,熟习该技术者应知,可以依照实际需求堆叠多个芯片。以图5为例,封装基板100上依序堆叠芯片110、中介层120、芯片140、中介层150及芯片130。其中芯片110、中介层120及芯片130的结构与接合方式都与上述实施例相似,在此不再赘述。至于芯片140的结构与芯片110相似,芯片140与中介层120的接合方式,跟芯片110与封装基板100接合方式相似;芯片140与中介层150接合方式,跟芯片110与中介层120接合方式相似,在此不再赘述。而中介层150的结构与中介层120相似,其与芯片140及芯片130的接合方式,与上述实施例中,中介层120与芯片110,芯片130接合方式相似,在此不再赘述。
请参照图6,图6绘示依照本发明再一实施例的一种倒装芯片堆叠封装的剖面示意图。在本发明的一个或多个实施例中,第二芯片130更包括对应第二有源表面130A的一第二背面130B,倒装芯片堆叠封装更包括一散热片160配置于第二背面130B上,且与第二散热金属层124连接。其中,散热片160可以通过导热胶162与第二背面130B及第二散热金属层124贴合,借此除了可以提供第二芯片130的保护外,还可以有助于第二芯片130,中介层120的散热,增加整体倒装芯片堆叠封装的散热效能。本实施例中其他部分的结构与工艺,与图1至图4的实施例中类似,因此在此不再赘述。
综上所述,本发明的倒装芯片堆叠封装,在堆叠的芯片中,每二个相邻的芯片之间插入一中介层,且在中介层上形成散热金属层,并与邻接的芯片导热性接合,芯片即可以直接利用中介层形成散热结构,提供芯片低热阻的散热途径。借此,可以明显改善倒装芯片堆叠封装的散热效率,且结构简单,可以降低制造成本。
借由以上较佳具体实施例的详述,是希望能更加清楚描述本发明的特征与精神,而并非以上述所揭露的较佳具体实施例来对本发明的范畴加以限制。相反地,其目的是希望能涵盖各种改变及具相等性的安排于本发明所欲申请的专利范围的范畴内。虽然本发明已以实施方式揭露如上,然其并非用以限定本发明,任何熟习此技艺者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰,因此本发明的保护范围当视权利要求书所界定者为准。
Claims (12)
1.一种倒装芯片堆叠封装,其特征在于,包括:
一封装基板,具有一内表面及对应的一外表面,该内表面具有至少一内接点,该外表面具有至少一外接点,该内接点与该外接点电性连接;
一第一芯片,具有一第一有源表面及对应的一第一背面,该第一有源表面具有至少一第一接点,该第一背面具有至少一第二接点,该第一接点与该第二接点电性连接,该第一芯片以该第一有源表面贴附于该内表面,使得该第一接点与该内接点电性连接;
一中介层,具有一第一接合面及对应的一第二接合面,该中介层具有至少一导电贯孔贯穿该第一接合面及该第二接合面,该第一接合面具有一第一散热金属层,该第二接合面具有一第二散热金属层,其中该第一散热金属层与该第二散热金属层与该导电贯孔电性隔离,该中介层的该第一接合面与该第一背面贴合,并使得该导电贯孔与该第二接点电性连接;以及
一第二芯片,具有一第二有源表面,该第二有源表面具有至少一第三接点,该第二芯片以该第二有源表面贴附于该第二接合面,使得该第三接点与该导电贯孔电性连接。
2.如权利要求1所述的倒装芯片堆叠封装,其特征在于,该第二芯片更包括对应该第二有源表面的一第二背面,该倒装芯片堆叠封装更包括一散热片配置于该第二背面上,且与该第二散热金属层连接。
3.如权利要求1所述的倒装芯片堆叠封装,其特征在于,该中介层的该第一接合面与该第一背面贴合,使得该第一散热金属层与该第一背面导热性接合。
4.如权利要求1所述的倒装芯片堆叠封装,其特征在于,该第一芯片与该封装基板是以倒装芯片方式接合,且该第一有源表面与该内表面之间更包括一第一底填材料。
5.如权利要求1所述的倒装芯片堆叠封装,其特征在于,该第二芯片与该中介层是以倒装芯片方式接合,且该第二有源表面与该第二接合面之间更包括一第二底填材料。
6.如权利要求1所述的倒装芯片堆叠封装,其特征在于,更包括一焊球配置于该外接点上且与该外接点电性连接。
7.一种倒装芯片堆叠封装,其特征在于,包括:
一中介层,具有一第一接合面及对应的一第二接合面,该中介层具有多个导电贯孔贯穿该第一接合面及该第二接合面,该第一接合面上具有一第一散热金属层,该第二接合面上具有一第二散热金属层,其中,第一接合面及第二接合面上相邻的该多个导电贯孔之间分别具有该第一散热金属层及该第二散热金属层,以及该第一散热金属层及该第二散热金属层分别与该导电贯孔电性隔离;
一第一芯片,具有一第一表面,该第一表面具有多个第一接点,该第一芯片以该第一表面贴附于该第一接合面,使得该多个第一接点分别与该多个导电贯孔电性连接,且该第一表面与该第一散热金属层导热性接合;以及
一第二芯片,具有一第二表面,该第二表面具有多个第二接点,该第二芯片以该第二表面贴附于该第二接合面,使得该多个第二接点分别与该多个导电贯孔电性连接,且该第二表面与该第二散热金属层导热性接合。
8.如权利要求7所述的倒装芯片堆叠封装,其特征在于,该第一芯片更具有对应该第一表面的一第三表面,且该第三表面具有多个第三接点,每一该多个第三接点分别与对应的该多个第一接点其中之一电性连接,其中该第一芯片以该第三表面与一封装基板,以倒装芯片方式接合,且该多个第三接点与该封装基板电性连接。
9.如权利要求7所述的倒装芯片堆叠封装,其特征在于,该第一芯片更具有对应该第一表面的一第三表面,且该第三表面具有多个第三接点,每一该多个第三接点分别与对应的该多个第一接点其中之一电性连接,该倒装芯片堆叠封装更包括:
一第二中介层,具有一第三接合面及对应的一第四接合面,该中介层具有多个第一导电贯孔贯穿该第三接合面及该第四接合面,该第三接合面具有一第三散热金属层,该第四接合面具有一第四散热金属层,其中该第三散热金属层与该第四散热金属层与该多个第一导电贯孔电性隔离,且相邻的该多个第一导电贯孔之间,在该第三接合面上具有该第三散热金属层,在该第四接合面上具有该第四散热金属层,且该第一芯片以该第三表面贴附于该第三接合面,使得该多个第三接点分别与该多个第一导电贯孔电性连接,且该第三表面与该第三散热金属层导热性接合。
10.如权利要求7所述的倒装芯片堆叠封装,其特征在于,该第一芯片与一封装基板接合,且该第二芯片与另一中介层接合。
11.一种中介层,用以连接一第一芯片与一第二芯片,其特征在于,该中介层包括:
一第一接合面及对应的一第二接合面;
多个导电贯孔贯穿该第一接合面及该第二接合面;
一第一散热金属层配置于该第一接合面上;以及
一第二散热金属层配置于该第二接合面上,其中该第一散热金属层与该第二散热金属层与该多个导电贯孔电性隔离,且相邻的该多个导电贯孔之间,在该第一接合面上具有该第一散热金属层,在该第二接合面上具有该第二散热金属层;
其中该第一芯片配置于该第一接合面上,第二芯片配置于该第二接合面上,该第一芯片与该第二芯片是借由该多个导电贯孔电性连接。
12.如权利要求11所述的中介层,其特征在于,该第一芯片及该第二芯片与该中介层导热性接合。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105428251A (zh) * | 2015-12-16 | 2016-03-23 | 南通富士通微电子股份有限公司 | 半导体堆叠封装方法 |
CN106449566A (zh) * | 2016-11-26 | 2017-02-22 | 南通沃特光电科技有限公司 | 一种冷却器的制造方法 |
CN111276473A (zh) * | 2018-12-04 | 2020-06-12 | Qorvo美国公司 | 用于扇出式封装的具有背面互连线的单片微波集成电路 |
CN111968963A (zh) * | 2019-05-20 | 2020-11-20 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
CN115799196A (zh) * | 2023-02-07 | 2023-03-14 | 季华实验室 | 一种芯片封装结构、方法以及电子设备 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10163856B2 (en) * | 2015-10-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated circuit structure and method of forming |
US9984995B1 (en) | 2016-11-13 | 2018-05-29 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
TWI638442B (zh) * | 2017-05-26 | 2018-10-11 | 瑞昱半導體股份有限公司 | 電子裝置及其電路基板 |
KR20240000507U (ko) * | 2021-07-29 | 2024-03-15 | 마벨 아시아 피티이 엘티디. | 적층형 집적 회로의 3차원 패키지에서 열 방출 및 전기적 견고성 개선 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101097906A (zh) * | 2006-06-29 | 2008-01-02 | 海力士半导体有限公司 | 具有垂直形成的热沉的层叠封装 |
US20080237844A1 (en) * | 2007-03-28 | 2008-10-02 | Aleksandar Aleksov | Microelectronic package and method of manufacturing same |
CN102339800A (zh) * | 2010-07-20 | 2012-02-01 | Lsi公司 | 叠层互连的吸热装置 |
TW201238015A (en) * | 2011-03-02 | 2012-09-16 | Siliconware Precision Industries Co Ltd | Inner layer heat-dissipating board and multi-chip stack package structure having inner layer heat-dissipating board and fabrication method thereof |
-
2014
- 2014-02-21 TW TW103105778A patent/TW201533882A/zh unknown
- 2014-06-23 CN CN201410283489.8A patent/CN104867908A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101097906A (zh) * | 2006-06-29 | 2008-01-02 | 海力士半导体有限公司 | 具有垂直形成的热沉的层叠封装 |
US20080237844A1 (en) * | 2007-03-28 | 2008-10-02 | Aleksandar Aleksov | Microelectronic package and method of manufacturing same |
CN102339800A (zh) * | 2010-07-20 | 2012-02-01 | Lsi公司 | 叠层互连的吸热装置 |
TW201238015A (en) * | 2011-03-02 | 2012-09-16 | Siliconware Precision Industries Co Ltd | Inner layer heat-dissipating board and multi-chip stack package structure having inner layer heat-dissipating board and fabrication method thereof |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105428251A (zh) * | 2015-12-16 | 2016-03-23 | 南通富士通微电子股份有限公司 | 半导体堆叠封装方法 |
CN106449566A (zh) * | 2016-11-26 | 2017-02-22 | 南通沃特光电科技有限公司 | 一种冷却器的制造方法 |
CN111276473A (zh) * | 2018-12-04 | 2020-06-12 | Qorvo美国公司 | 用于扇出式封装的具有背面互连线的单片微波集成电路 |
CN111968963A (zh) * | 2019-05-20 | 2020-11-20 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
CN115799196A (zh) * | 2023-02-07 | 2023-03-14 | 季华实验室 | 一种芯片封装结构、方法以及电子设备 |
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