TWI525723B - 晶片封裝體結構及其形成方法 - Google Patents

晶片封裝體結構及其形成方法 Download PDF

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Publication number
TWI525723B
TWI525723B TW103146215A TW103146215A TWI525723B TW I525723 B TWI525723 B TW I525723B TW 103146215 A TW103146215 A TW 103146215A TW 103146215 A TW103146215 A TW 103146215A TW I525723 B TWI525723 B TW I525723B
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Taiwan
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chip package
package structure
conductive
conductive member
circuit board
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TW103146215A
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English (en)
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TW201530667A (zh
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林子閎
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聯發科技股份有限公司
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Description

晶片封裝體結構及其形成方法
本發明係有關於晶片封裝體結構及其製法，且特別是有關於具有多半導體晶片(multiple semiconductor dies)之晶片封裝體結構。
晶片封裝體結構除了保護晶片使免受環境汙染之外，還對封裝於其中之晶片提供連接介面。堆疊封裝結構(例如，封裝體疊封裝體(package-on-package，PoP))已變得更為普及。
已發展新封裝技術來增進半導體元件之堆疊密度與效能。這些相對新穎的半導體元件封裝技術面臨著製作挑戰。
有鑑於此，本發明提供一種晶片封裝體結構及其形成方法。
本發明一實施例提供一種晶片封裝體結構，其包括：一晶片封裝體，位於一印刷電路板之上；複數個導電構件，位於該晶片封裝體與該印刷電路板之間；以及至少一導熱構件，位於該晶片封裝體與該印刷電路板之間，其中該導熱構件具有一熱傳導係數，高於每一該些導電構件之熱傳導係數。
本發明一實施例提供一種晶片封裝體結構的形成方法，其包括：提供一晶片封裝體；提供一印刷電路板；以及藉由複數個導電構件及至少一導熱構件而將該晶片封裝體接合至該印刷電路板，其中該導熱構件具有一熱傳導係數，高於每一該些導電構件之熱傳導係數。
採用本發明的晶片封裝體結構，半導體晶片於運作期間所產生之熱能可藉由導熱構件而導出，因此，可增進晶片封裝體結構之可靠度及效能。
10、20‧‧‧晶片封裝體結構
100、100’‧‧‧晶片封裝體
102‧‧‧基底
104、106A、106B‧‧‧導電接墊
108A、108B‧‧‧半導體晶片
109A、109B‧‧‧導電構件
110‧‧‧封膠材料層
111‧‧‧導電結構
112‧‧‧印刷電路板
113‧‧‧表面
114‧‧‧導電接墊
116‧‧‧導電構件
118‧‧‧導熱構件
119‧‧‧側壁表面
120、122‧‧‧連接層
200‧‧‧晶片封裝體
202‧‧‧基底
204、206‧‧‧導電接墊
108、208A、208B‧‧‧半導體晶片
209A、209B‧‧‧銲線
210‧‧‧封膠材料層
212‧‧‧導電構件
W1、W2‧‧‧寬度
第1圖顯示根據本發明一些實施例之晶片封裝體結構的剖面圖。
第2圖顯示根據本發明一些實施例之晶片封裝體結構的剖面圖。
第3A-3D圖顯示根據本發明一些實施例之晶片封裝體結構中基底與導電接墊的上視圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在敘述中，第一製程與第二製程之進行，可包括第二製程於第一製程之後立刻進行之實施例，亦可包括其他附加製程於第一製程與第二製程之間進行之實施例。許多元件可能被任意地繪製 成不同的尺寸比例。這僅是為了簡化與清楚化。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
以下，敘述了實施例之一些變化。在不同的圖式與實施例敘述中，相似的標號可用以標示相似的元件。
第1圖顯示根據本發明一些實施例之晶片封裝體結構10的剖面圖。在一些實施例中，提供晶片封裝體100。在一些實施例中，晶片封裝體100包括基底102。基底102可包括介電材料，例如有機材料。在一些實施例中，有機材料包括具有玻璃纖維的聚丙烯(polypropylene，PP)、環氧樹脂(epoxy resin)、聚醯亞胺(polyimide)、氰酸酯(cyanate ester)、其他適合的材料、或前述之組合。在一些其他實施例中，基底102包括半導體材料，例如是矽。
如第1圖所示，在一些實施例中，導電接墊104及導電接墊106A與106B形成在基底102之相反的表面上及/或表面中。每一導電接墊104係電性連接至相應的導電接墊106A或106B。在一些實施例中，基底102中形成有導電線路(conductive lines)及/或導電通路(conductive vias)。導電線路及/或導電通路形成了在基底102相反表面上之導電接墊之間的電性連接。
在一些實施例中，晶片封裝體100包括一或更多的半導體晶片，例如是半導體晶片108A及108B。半導體晶片108A及108B係設置於基底102之上。在一些實施例中，半導體晶片108A及108B具有不同的功能。在一些其他實施例中，半導體 晶片108A及108B具有相似的功能。在一些實施例中，導電構件109A及109B分別形成於基底102與半導體晶片108A及108B之間。每一導電構件109A及109B電性連接至相應的導電接墊104。
在一些實施例中，晶片封裝體100包括形成於基底102上之封膠材料層(molding compound layer)110。封膠材料層110圍繞半導體晶片108A及108B，並保護半導體晶片108A及108B，使免於受損及/或被汙染。
如第1圖所示，在一些實施例中，提供印刷電路板112。印刷電路板112包括複數個導電接墊114，其形成於印刷電路板112之表面113之上或之中。之後，如第1圖所示，在一些實施例中，藉由複數個導電構件116及一或更多的導熱構件118而將晶片封裝體100接合至印刷電路板112。
在一些實施例中，導電構件116包括焊料凸塊(solder bumps)、焊料球(solder balls)、其他適合的導電結構、或前述之組合。在一些實施例中，導電構件116具有彎曲的側壁表面(curved sidewall surface)，如第1圖所示。在一些實施例中，導熱構件118具有較導電構件116還高的熱傳導係數(thermal conductivity)。在一些實施例中，導熱構件118包括金屬薄片(metal foil)。例如，金屬薄片包括銅薄片(copper foil)。在一些其他實施例中，金屬薄片包括鋁薄片或鋁箔(aluminum foil)。在一些實施例中，導熱構件118具有大抵平坦(substantially planar)之側壁表面119。在一些實施例中，側壁表面119大抵垂直(substantially perpendicular)於印刷電路板 112之表面113。在一些實施例中，導熱構件118具有寬度W1，其大於導電構件116之寬度W2。
如第1圖所示，在一些實施例中，於晶片封裝體100與導熱構件118之間形成連接層122，並於導熱構件118與印刷電路板112之間形成連接層120。在一些實施例中，將導熱構件118(例如，金屬薄片)取起並放置於導電接墊106B之上。在一些實施例中，導熱構件118係藉由連接層122而接合至晶片封裝體100上。例如，導熱構件118係透過連接層122而與導電接墊106B接合。之後，如第1圖所示，在一些實施例中，將導熱構件118接合至印刷電路板112上。例如，導熱構件118係透過連接層120而與導電接墊114接合。
在一些實施例中，連接層122及120係由相同的焊料材料(solder material)所製成。在一些其他實施例中，連接層122及120係由不同的焊料材料所製成。在一些實施例中，連接層122具有較連接層120還高的熔點。在一些情形中，晶片封裝體100與印刷電路板112之間的接合可能需重工(rework)。若連接層122具有較連接層120還高之熔點，可在藉由加熱晶片封裝體以移除印刷電路板112之後，使導熱構件118維持與晶片封裝體100相連。在一些實施例中，連接層122具有約攝氏229度之熔點，而連接層120具有約攝氏220度之熔點。在一些實施例中，連接層122及120皆由錫(Sn)、銀(Ag)、及銅(Cu)之合金所製成。在一些實施例中，連接層122由SAC405(Sn-4.0Ag-0.5Cu,wt%)所製成。在一些實施例中，連接層120由SAC305(Sn-3.0Ag-0.5Cu,wt%)所製成。
在一些實施例中，連接層122及120具導電性。在一些實施例中，導熱構件118電性連接至導電接墊106B。在一些實施例中，導電接墊106B為晶片封裝體100之電源接墊(power pad)。在一些其他實施例中，導電接墊106B為晶片封裝體100之接地接墊(ground pad)。
在一些實施例中，半導體晶片108A及108B於運作期間所產生之熱能可藉由導熱構件118而導出。因此，可增進晶片封裝體結構10之可靠度及效能。
本發明之實施例具有許多變化。在一些實施例中，晶片封裝體結構包括多個晶片封裝體。第2圖顯示根據一些實施例之晶片封裝體結構20的剖面圖。晶片封裝體結構20包括設置於晶片封裝體100’上之晶片封裝體200。在一些實施例中，晶片封裝體200透過導電構件212而接合至晶片封裝體100’。導電構件212例如包括焊料凸塊。
在一些實施例中，晶片封裝體200包括基底202。基底202可包括介電材料，例如是有機材料。在一些實施例中，有機材料包括具有玻璃纖維的聚丙烯(polypropylene，PP)、環氧樹脂(epoxy resin)、聚醯亞胺(polyimide)、氰酸酯(cyanate ester)、其他適合的材料、或前述之組合。在一些其他實施例中，基底202包括半導體材料，例如是矽。
如第2圖所示，在一些實施例中，導電接墊204及導電接墊206形成在基底202之相反的表面上及/或表面中。每一導電接墊204係電性連接至相應的導電接墊206。在一些實施例中，基底202中形成有導電線路(conductive lines)及/或導電 通路(conductive vias)。導電線路及/或導電通路形成了在基底202相反表面上之導電接墊之間的電性連接。
在一些實施例中，晶片封裝體200包括一或更多的半導體晶片，例如是半導體晶片208A及208B。半導體晶片208A及208B係設置於基底202之上。在一些實施例中，半導體晶片208A及208B具有不同的功能。在一些其他實施例中，半導體晶片208A及208B具有相似的功能。在一些實施例中，銲線209A用以形成半導體晶片208A與相應導電接墊204之間的電性連接。在一些實施例中，銲線209B用以形成半導體晶片208B與相應導電接墊204之間的電性連接。
在一些實施例中，晶片封裝體200包括形成於基底202上之封膠材料層(molding compound layer)210。封膠材料層210圍繞半導體晶片208A及208B，並保護半導體晶片208A及208B，使免於受損及/或被汙染。
晶片封裝體100’相似於晶片封裝體100。在一些實施例中，晶片封裝體100’包括數個導電結構111，其穿過封膠材料層110。導電結構111形成導電接墊104與導電構件212之間的電性連接。
相似於顯示於第1圖之實施例，如第2圖所示，在一些實施例中，晶片封裝體100’藉由導電構件116及導熱構件118而接合至印刷電路板112。在一些實施例中，半導體晶片108、208A、及208B於運作期間所產生之熱能可藉由導熱構件118而導出。因此，可增進晶片封裝體結構20之可靠度及效能。
本發明之實施例具有許多變化。例如，多個導熱 構件係形成於晶片封裝體與印刷電路板之間，例如像第1圖所示之結構。或者，可僅有一導熱構件形成於晶片封裝體與印刷電路板之間，例如像第2圖所示之結構。導熱構件之形狀、分布、及尺寸可有許多變化。第3A-3D圖顯示根據本發明一些實施例之晶片封裝體結構中基底與導電接墊的上視圖。
第3A圖顯示基底102及導電接墊106A及106B的上視圖，其亦代表形成於其上之導熱構件118及導電構件116的分布情形。在一些實施例中，晶片封裝體結構包括單一個導電接墊106B，其具有正方形剖面。在這些情形下，導熱構件118亦具有正方形剖面。
如第3B圖所示，在一些實施例中，晶片封裝體包括複數個導電接墊106B。在這些情形中，晶片封裝體包括複數個導熱構件118。在一些實施例中，這些導熱構件118係排列成陣列(array)。在一些實施例中，這些導熱構件118的形狀及/或尺寸大抵彼此相同。在一些實施例中，每一導熱構件118為正方形。例如，有九個正方形導熱構件118排列成陣列。
如第3C圖所示，在一些實施例中，晶片封裝體結構包括數個導電接墊106B，且其係排列成陣列。在一些實施例中，這些導電接墊106B的形狀及/或尺寸大抵彼此相同。例如，導電接墊106B為正方形且具大抵相同之尺寸。在這些情形下，導熱構件118亦排列成陣列，且為正方形。在一些其他實施例中，晶片封裝體結構包括更多或更少的導熱構件。例如，晶片封裝體結構包括十六個排列成陣列之導熱構件。在一些實施例中，導熱構件中之一些係電性連接至晶片封裝體中之電源接墊， 而導熱構件中之另一些係電性連接至晶片封裝體中之接地接墊。
如第3D圖所示，在一些實施例中，晶片封裝體結構包括數個導電接墊106B，且其具有不同的形狀及/或尺寸。導電接墊106B可設置於更多熱能可能產生的位置。在這些情形下，導熱構件118亦具有不同的形狀及/或尺寸。導熱構件118亦位於特定地點以導出熱能。
本發明實施例形成一或更多的導熱構件於晶片封裝體與印刷電路板之間。可使用金屬薄片(例如，銅薄片)作為導熱構件。歸因於導熱構件，半導體晶片於運作期間所產生之熱能可被導出。因此，可增進晶片封裝體結構之可靠度及效能。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶片封裝體結構
100‧‧‧晶片封裝體
102‧‧‧基底
104、106A、106B‧‧‧導電接墊
108A、108B‧‧‧半導體晶片
109A、109B‧‧‧導電構件
110‧‧‧封膠材料層
112‧‧‧印刷電路板
113‧‧‧表面
114‧‧‧導電接墊
116‧‧‧導電構件
118‧‧‧導熱構件
119‧‧‧側壁表面
120、122‧‧‧連接層
W1、W2‧‧‧寬度

Claims (20)

  1. 一種晶片封裝體結構，包括：一晶片封裝體，位於一印刷電路板之上；複數個導電構件，位於該晶片封裝體與該印刷電路板之間；以及至少一導熱構件，位於該晶片封裝體與該印刷電路板之間，其中該導熱構件具有一熱傳導係數，高於每一該些導電構件之熱傳導係數；其中，該導熱構件電性連接至該晶片封裝體之導電接墊以及電性連接至該印刷電路板之導電接墊，並且位於該該晶片封裝體之導電接墊與該印刷電路板之導電接墊之間。
  2. 如申請專利範圍第1項所述之晶片封裝體結構，其中該些導電構件包括焊料凸塊、焊料球、或前述之組合。
  3. 如申請專利範圍第1項所述之晶片封裝體結構，其中該導熱構件包括一金屬薄片。
  4. 如申請專利範圍第1項所述之晶片封裝體結構，其中該導熱構件包括一銅薄片。
  5. 如申請專利範圍第1項所述之晶片封裝體結構，更包括：一第一連接層，位於該導熱構件與該晶片封裝體之間；以及一第二連接層，位於該導熱構件與該印刷電路板之間。
  6. 如申請專利範圍第5項所述之晶片封裝體結構，其中該第一連接層及該第二連接層係由一焊料材料所製成。
  7. 如申請專利範圍第5項所述之晶片封裝體結構，其中該第一 連接層及該第二連接層係由不同的焊料材料所製成。
  8. 如申請專利範圍第7項所述之晶片封裝體結構，其中該第一連接層之熔點高於該第二連接層之熔點。
  9. 如申請專利範圍第1項所述之晶片封裝體結構，其中該晶片封裝體之導電接墊為該晶片封裝體之一電源接墊。
  10. 如申請專利範圍第1項所述之晶片封裝體結構，其中該晶片封裝體之導電接墊為該晶片封裝體之一接地接墊。
  11. 如申請專利範圍第1項所述之晶片封裝體結構，其中該至少一導熱構件包括複數個導熱構件。
  12. 如申請專利範圍第11項所述之晶片封裝體結構，其中該些導熱構件排列成一陣列。
  13. 如申請專利範圍第11項所述之晶片封裝體結構，其中每一該些導熱構件具有一正方形剖面。
  14. 如申請專利範圍第1項所述之晶片封裝體結構，其中該導熱構件之寬度大於每一該些導電構件。
  15. 如申請專利範圍第1項所述之晶片封裝體結構，更包括一第二晶片封裝體，位於該晶片封裝體之上。
  16. 如申請專利範圍第1項所述之晶片封裝體結構，其中該晶片封裝體包括複數個半導體晶片。
  17. 如申請專利範圍第1項所述之晶片封裝體結構，其中該導熱構件具有一側壁表面，大抵垂直於該印刷電路板之一表面。
  18. 一種晶片封裝體結構的形成方法，包括：提供一晶片封裝體；提供一印刷電路板；以及 藉由複數個導電構件及至少一導熱構件而將該晶片封裝體接合至該印刷電路板，其中該導熱構件具有一熱傳導係數，高於每一該些導電構件之熱傳導係數；其中，該導熱構件電性連接至該晶片封裝體之導電接墊以及電性連接至該印刷電路板之導電接墊，並且位於該該晶片封裝體之導電接墊與該印刷電路板之導電接墊之間。
  19. 如申請專利範圍第18項所述之晶片封裝體結構的形成方法，更包括：藉由一第一連接層而將該導熱構件接合至該晶片封裝體；以及在該導熱構件接合至該晶片封裝體之後，藉由一第二連接層而將該導熱構件接合至該印刷電路板。
  20. 如申請專利範圍第19項所述之晶片封裝體結構的形成方法，其中該第一連接層之熔點高於該第二連接層之熔點。
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