TWI619223B - 堆疊的半導體封裝以及其之製造方法 - Google Patents

堆疊的半導體封裝以及其之製造方法 Download PDF

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Publication number
TWI619223B
TWI619223B TW104133175A TW104133175A TWI619223B TW I619223 B TWI619223 B TW I619223B TW 104133175 A TW104133175 A TW 104133175A TW 104133175 A TW104133175 A TW 104133175A TW I619223 B TWI619223 B TW I619223B
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semiconductor package
adhesive member
interposer
substrate
terminals
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TW104133175A
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English (en)
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TW201618267A (zh
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朴東久
朴傑森
金錦雄
元秋亨
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艾馬克科技公司
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Publication of TW201618267A publication Critical patent/TW201618267A/zh
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Abstract

一種堆疊的半導體封裝以及一種製造其之方法。例如且非限制性的，此揭露內容的各種特點係提供一種半導體封裝，其中一上方的中介體及/或封裝係利用一包括導電的微粒的黏著構件以電性及機械地耦接至一下方的封裝。

Description

堆疊的半導體封裝以及其之製造方法
本發明關於堆疊的半導體封裝以及其之製造方法。
相關申請案的交互參照/納入作為參考
本申請案係參照到2014年10月8日向韓國智慧財產局申請且名稱為"堆疊的半導體裝置以及製造其之方法"的韓國專利申請案號10-2014-0135819、主張其之優先權，並且主張其之益處，該韓國專利申請案的內容係藉此以其整體被納入在此作為參考。
現有的用於形成例如是包括一堆疊在一下方的封裝上的上方的中介體及/或上方的封裝之堆疊的半導體封裝的各種半導體裝置之方法是不足的，例如其係不必要地昂貴而且/或是產生一具有過大的尺寸之半導體封裝。而透過習知及傳統的方式與如同在本申請案之參考圖式的其餘部分中所闡述的本揭露內容之比較，此種習知及傳統的方式之進一步的限制及缺點對於具有此項技術的技能者而言將會變成是明顯的。
此揭露內容的各種特點係提供一種堆疊的半導體封裝以及一種用於製造其之方法。例如且非限制性的，此揭露內容的各種特點係提 供一種半導體封裝，其中一上方的中介體及/或封裝係利用一包括導電的微粒的黏著構件以電性及機械地耦接至一下方的封裝。
100‧‧‧下方的半導體封裝
102‧‧‧帶狀基板
104‧‧‧半導體晶片
106‧‧‧導電的凸塊
108‧‧‧堆疊的球體
109‧‧‧焊料球體
110‧‧‧模製化合物樹脂
112‧‧‧穿模貫孔(TMV)
120‧‧‧用於堆疊的IO端子
200‧‧‧中介體
202‧‧‧導電的墊
204‧‧‧貫孔孔洞
206‧‧‧球體焊盤
208‧‧‧連接球體
210‧‧‧黏著構件
212‧‧‧導電的微粒
300‧‧‧上方的半導體封裝
302‧‧‧輸入/輸出(IO)端子
304‧‧‧球體焊盤
圖1係展示根據本揭露內容的各種特點的一種堆疊的半導體封裝的橫截面圖。
圖2係展示描繪根據本揭露內容的各種特點的一種製造一堆疊的半導體封裝之方法的橫截面圖。
圖3係展示根據本揭露內容的各種特點的一種用於在一下方的封裝上利用一包括導電的微粒的黏著構件以堆疊一上方的中介體及/或封裝之方法。
圖4係展示根據本揭露內容的各種特點的一種堆疊的半導體封裝的橫截面圖。
圖5係展示根據本揭露內容的各種特點的一種堆疊的半導體封裝的橫截面圖。
以下的討論是藉由提供本揭露內容的例子來提出本揭露內容的特點。此種例子並非限制性的，並且因此本揭露內容的各種特點之範疇不應該是必然受限於所提供的例子之任何特定的特徵。在以下的討論中，該措辭"例如"、"譬如"以及"範例的"並非限制性的，並且大致與"舉例且非限制性的"、"例如且非限制性的"、及類似者為同義的。
如同在此所利用的，"及/或"是表示在表列中藉由"及/或"所 加入的項目中的任一個或是多個。舉例而言，"x及/或y"是表示該三個元素的集合{(x)、(y)、(x,y)}中的任一元素。換言之，"x及/或y"是表示"x及y中的一或兩者"。作為另一例子的是，"x、y及/或z"是表示該七個元素的集合{(x)、(y)、(z)、(x,y)、(x,z)、(y,z)、(x,y,z)}中的任一元素。換言之，"x、y及/或z"是表示"x、y及z中的一或多個"。
在此所用的術語只是為了描述特定例子之目的而已，因而並不欲限制本揭露內容。如同在此所用的，單數形係欲亦包含複數形，除非上下文另有清楚相反的指出。進一步將會理解到的是，當該些術語"包括"、"包含"、"具有"、與類似者用在此說明書時，其係指明所述特點、整數、步驟、操作、元件及/或構件的存在，但是並不排除一或多個其它特點、整數、步驟、操作、元件、構件及/或其之群組的存在或是添加。
將會瞭解到的是，儘管該些術語第一、第二、等等可被使用在此以描述各種的元件，但是這些元件不應該受限於這些術語。這些術語只是被用來區別一元件與另一元件而已。因此，例如在以下論述的一第一元件、一第一構件或是一第一區段可被稱為一第二元件、一第二構件或是一第二區段，而不脫離本揭露內容的教示。類似地，各種例如是"上方"、"下方"、"側邊"與類似者的空間的術語可以用一種相對的方式而被用在區別一元件與另一元件。然而，應該瞭解的是構件可以用不同的方式加以定向，例如一半導體裝置可被轉向側邊，因而其"頂"表面是水平朝向的，並且其"側"表面是垂直朝向的，而不脫離本揭露內容的教示。此外，該術語"之上"將會在該文件中被利用來表示"之上"以及"在正上方"(例如，其並沒有介於中間的層)。
在圖式中，各種的尺寸(例如，層厚度、寬度、等等)可能會為了舉例說明的清楚起見而被誇大。此外，相同的元件符號係被利用以指稱各種例子的所有討論中之相似的元件。
本揭露內容的各種特點係提供一種堆疊的半導體封裝以及其之製造方法。例如，本揭露內容的各種特點係提供一種堆疊的半導體封裝以及一種製造其之方法，其中在一下方的半導體封裝與一中介體(或是一上方的半導體封裝的基板)之間的接合線的尺寸以及在兩者之間的可接合性(bondability)可以利用一包括導電的微粒的黏著構件而被增大。
在減少各種電子裝置的重量及尺寸並且增高其速度、功能及效能的趨勢下，安裝在該電子裝置中的半導體裝置是需要呈現高的可靠度。於是，已經有開發出各種半導體封裝，其包含晶圓級晶片尺寸封裝；晶片堆疊的封裝，其係被配置成使得附接至一中介體的晶片係被安裝在一基板之上；堆疊式封裝(POP)，其係被配置成使得封裝係被堆疊在一中介體的頂端及底部上；等等。一範例的封裝係被展示在圖5，其係展示根據本揭露內容的各種特點的一種堆疊的半導體封裝的橫截面圖。
在圖5中，元件符號100係指明一下方的半導體封裝，元件符號300係指明一上方的半導體封裝，並且元件符號200係指明一中介體，該中介體200係將該下方的半導體封裝100以及上方的半導體封裝300彼此導電地連接。
在一範例的實施方式中，為了製造該下方的半導體封裝100，一帶狀基板102(或是基板的面板)係被設置，其中複數個形成半導體封裝的區域係以等距的間隔被形成在其之橫斷(或是橫向)及/或縱長的方向 上，並且至少一半導體晶片104(或是晶粒)係附接至該帶狀基板102的形成半導體封裝的區域的每一個的一中心區域。該半導體晶片104可以用各種方式的任一種來附接至該基板102。例如，該半導體晶片104可以利用導電的凸塊106或是各種導電的互連結構的任一種來附接至該基板102。
堆疊的球體108例如可以被熔接在一被形成在該半導體晶片104周圍的週邊區域，例如是在該基板102的一邊緣區域之導電的圖案上。該堆疊的球體108例如可被使用於將該基板102電連接至該中介體200。
該基板102的上表面可以利用一模製化合物樹脂110(或是其它囊封材料)來加以模製或者是囊封，藉此該半導體晶片104以及堆疊的球體108係被密封(例如，全體或是部份地)，以便於被保護而與外部隔離。該模製化合物樹脂110例如可以底膠填充該半導體晶片104，且/或一個別的底膠填充材料可以底膠填充該半導體晶片104。例如，為了強化由該半導體晶片104所產生的熱耗散至外部，該模製化合物樹脂110的上表面可被形成(例如，原先被形成、被向下研磨、等等)為與半導體晶片104的上表面齊平的(或是共面的)，因而該半導體晶片104的上表面係從該模製化合物樹脂110露出至外部。
例如是具有一預設深度的穿模貫孔(TMV)112可被形成在該模製化合物110中，以露出該些堆疊的球體108。該些TMV 112可以利用例如是雷射處理(例如，剝蝕)的各種方式的任一種來加以形成在該模製化合物樹脂110的上表面中。例如，該些穿模貫孔112可被形成至該些堆疊的球體108從該模製化合物樹脂110露出所在的深度。
該中介體200例如可以導電地堆疊在該下方的半導體封裝 100的穿模貫孔112上。
該中介體200可包括各種特徵的任一種。例如，該中介體200可以是由一印刷電路板(PCB)所形成的、可以是由一種矽材料所形成的(例如是在晶圓廠製程的生產線後端中等等)、可以是由介電材料及導電材料的層所形成的(例如，在一後晶圓廠封裝製程中等等)、等等。該中介體200例如可以提供在該下方的半導體封裝100與上方的半導體封裝300之間的電性(或是導電的)連接。例如，該中介體200可包括導電的墊202(或是其它的互連結構或接點)以用於連接至該上方的半導體封裝300。
如同在圖5中所繪，該中介體200可被配置成使得該些導電的墊202(其係連接至該上方的半導體封裝300的輸入/輸出(IO)端子302)從該中介體200的上表面被露出、或是在該上表面上，並且球體焊盤(land)206(其係藉由該貫孔孔洞204及/或導電線路(未顯示)以連接至該些導電的墊202)係被形成在該中介體200的下表面上。注意到的是，各種的互連結構或接點的任一種都可被利用。
連接球體208例如可以被熔接(例如，焊接、等等)在該中介體200的球體焊盤206上。該些連接球體208例如可以被堆疊在該下方的半導體封裝100的穿模貫孔112中之堆疊的球體108上，並且接著可以被熔接在一起，藉此達成該中介體200在該下方的半導體封裝100上的電連接及堆疊。
該上方的半導體封裝300的IO端子302例如可以被熔接(例如，焊接、等等)在該中介體200的導電的墊202上，因而該上方的半導體封裝300係被堆疊在該中介體200上。
注意到的是，對於將該上方的半導體封裝300堆疊在導電的墊202上而言為替代及/或額外的是，一或多個半導體晶片可以被堆疊在該中介體200的導電的墊202上並且附接至導電的墊202。
例如可以連接至一電子裝置的主機板之焊料球體109可以被熔接在該下方的半導體封裝100的基板102的下表面露出的球體焊盤上，藉此形成一堆疊式封裝的結構，該結構係被配置成使得該下方及上方的半導體封裝100、300係藉由該中介體200來加以堆疊。
根據此揭露內容的各種特點，可以對於以上論述的範例的封裝做成一些修改，其之非限制性的例子係在此加以提供。
首先例如，在各種的實施方式中，一空的空間可能會餘留在該下方的半導體封裝100的模製化合物樹脂110的上表面與該中介體200的下表面之間。此種空間例如可能會讓在該下方的半導體封裝100與中介體200之間的黏著劣化。
其次例如，一種類型的例如是環氧樹脂的絕緣黏著劑可以在堆疊該中介體200之前，被施加在該半導體晶片104的上表面上。在一範例情節中，該環氧樹脂可能會在該中介體200被堆疊在該下方的半導體封裝100上時，因為所施加的作用以將該半導體晶片與中介體彼此黏合的壓力而廣泛地散佈。然而，因為在該模製化合物樹脂110的上表面(其可被形成為與該半導體晶片104齊平的)與該中介體200的下表面之間的空的空間，因而在該下方的半導體封裝100與中介體200之間的黏著可能會劣化。
第三例如，當在一用於該下方的半導體封裝100以及中介體200被堆疊時將該些連接球體208以及堆疊的球體108彼此熔接(例如，焊 接、等等)的回焊製程中產生熱時，可能會沒有額外的構件來保持該下方的半導體封裝100以及中介體200平坦的，並且因此該下方的半導體封裝100以及中介體200的每一個的邊緣部分可能會由於不同之個別的熱膨脹係數而翹曲。由於此種翹曲，一種其中該些連接球體208以及堆疊的球體108彼此分離的錯誤可能會發生。
於是，本揭露內容的各種特點係提供解決以上所關心的事項之一種堆疊的半導體封裝及/或製造其之方法。例如，一種堆疊的半導體封裝以及一種製造其之方法係被提供，例如其中一下方的半導體封裝以及一中介體可以利用一包括(或包含)導電的微粒的黏著構件來彼此導電地連接而且同時加以黏著，藉此使得在該下方的半導體封裝與中介體之間的電性信號的傳輸變得容易，並且增加在該下方的半導體封裝與中介體之間的接合線的尺寸以及在兩者之間的可接合性。
例如，在一範例的實施方式中，一種堆疊的半導體封裝係被提出，其係包括：一下方的半導體封裝，該下方的半導體封裝係包括一基板；一半導體晶片，其係附接至該基板的一上表面的一中心；用於堆疊的IO端子，其係附接至該基板的上表面的一邊緣部分；以及一模製化合物樹脂或是其它的囊封材料，其係用於模覆(over-molding)該基板以便於露出該些用於堆疊的IO端子的上表面，同時密封該半導體晶片以及該些用於堆疊的IO端子的至少一部分；以及一中介體，其係導電地連接至該下方的半導體封裝的IO端子並且堆疊在該下方的半導體封裝上，其中一包括(或包含)導電的微粒的黏著構件係被設置在該下方的半導體封裝的一上表面與該中介體的一下表面之間，使得該下方的半導體封裝的IO端子以及該中介體的導 電的墊係藉由該黏著構件的導電的微粒來彼此導電地連接，並且同時該下方的半導體封裝以及該中介體係藉由該黏著構件的黏著來彼此接合。例如，該下方的半導體封裝以及中介體的非導電的部分可以藉由和被利用來接合該下方的半導體封裝以及中介體的導電的部分相同的黏著構件來加以接合。
例如可以附接至該中介體的一整個下表面的黏著構件例如是在將該中介體堆疊在該下方的半導體封裝上之際，被接合至該下方的半導體封裝的上表面。注意到的是，在該堆疊之前，該黏著構件可以是附接至該中介體及/或該下方的半導體封裝的任一個(或是都未附接的)。
該黏著構件例如可以被提供為一包括(或包含)導電的微粒並且具有一預設厚度的膜。或者是，該黏著構件可被提供為一包括(或包含)導電的微粒的膏。該黏著構件例如可以包括具有各種尺寸及/或材料的任一種之導電的微粒。例如，該導電的微粒可包括金、石墨、被塗覆導電材料的絕緣體微粒、等等。該導電的微粒可包括各種尺寸的任一種(例如，5μm、4-6μm、3-10μm、等等)。該導電的微粒例如可以代表該黏著構件的一個低百分比，例如是總含量的1-5%。該黏著構件的厚度可包括各種厚度的任一種(例如，15-25μm、20-30μm、等等)。
該些用於堆疊的IO端子例如可以包括導電柱或柱體。例如，該些IO端子可包括以一細微的間距(例如，<130μm、<100μm、等等)間隔開的導電柱或柱體(例如，銅柱或柱體、等等)。
此外，本揭露內容的另一特點係提供一種製造一堆疊的半導體封裝之方法，其係包括：將一半導體晶片導電地附接至一基板的一上表 面的一中心；將用於堆疊的IO端子導電地附接至該基板的上表面的一邊緣(或週邊)部分；利用一模製化合物樹脂(或是其它的囊封材料)來模覆該基板，以便於密封該半導體晶片以及該些用於堆疊的IO端子；均勻地研磨該模製化合物樹脂的一上表面，以便於露出該些用於堆疊的IO端子；將一包括導電的微粒的黏著構件附接至一中介體的一下表面；以及將該中介體堆疊在一下方的半導體封裝上，使得附接至該中介體的該黏著構件係導電地附接至該下方的半導體封裝的一上表面。注意到的是，該黏著構件亦可以是在該中介體的設置之前附接至該下方的半導體封裝。
例如，在附接該些用於堆疊的IO端子中，以一細微的間距間隔開的複數個銅柱或柱體可以導電地附接至一被形成在該基板的上表面的邊緣部分之導電的圖案。然而，注意到的是，此揭露內容的範疇並不限於此種端子配置。
在一範例的實施方式中，在堆疊該中介體中，該下方的半導體封裝的IO端子以及該中介體的導電的墊係藉由該黏著構件的導電的微粒來彼此導電地連接，並且同時該下方的半導體封裝以及該中介體係藉由該黏著構件的黏著來彼此接合。例如，相同的黏著構件可以將該下方的半導體封裝以及該中介體的導電及非導電的部分兩者分別彼此接合。
在堆疊該中介體中，熱以及壓力兩者例如可以是同時被施加至該黏著構件，以將該下方的半導體封裝以及該中介體彼此接合。
此外，本揭露內容的又一特點係提供一種堆疊的半導體封裝，其係包括：一下方的半導體封裝，該下方的半導體封裝係包括一基板；一半導體晶片，其係附接至該基板的一上表面的一中心；用於堆疊的IO端 子，其係附接至該基板的上表面的一邊緣部分；以及一模製化合物樹脂(或是其它的囊封材料)，其係用於模覆該基板以便於露出該些用於堆疊的IO端子的上表面，同時密封該半導體晶片以及該些用於堆疊的IO端子；以及一上方的半導體封裝，其係導電地連接至該下方的半導體封裝的IO端子並且被堆疊在該下方的半導體封裝上，其中一包括(或包含)導電的微粒的黏著構件係被設置在該下方的半導體封裝的一上表面與該上方的半導體封裝的一下表面之間，使得該下方的半導體封裝的IO端子以及該上方的半導體封裝的球體焊盤係藉由該黏著構件的導電的微粒來彼此導電地連接，並且同時該下方的半導體封裝以及該上方的半導體封裝係藉由該黏著構件的黏著來彼此接合。例如，該上方及下方的半導體封裝之導電的部分以及非導電的部分可以利用相同的黏著構件來分別加以彼此接合。
此外，本揭露內容的又一特點係提供一種製造一堆疊的半導體封裝之方法，其係包括：將一半導體晶片導電地附接至一基板的一上表面的一中心；將用於堆疊的IO端子導電地附接至該基板的上表面的一邊緣部分；利用一模製化合物樹脂來模覆該基板，以便於密封該半導體晶片以及該些用於堆疊的IO端子；均勻地研磨該模製化合物樹脂的一上表面，以便於露出該些用於堆疊的IO端子；附接一包括(或包含)導電的微粒的黏著構件至一上方的半導體封裝的一下表面；以及將該上方的半導體封裝堆疊在一下方的半導體封裝上，使得附接至該上方的半導體封裝的該黏著構件係導電地附接至該下方的半導體封裝的一上表面。注意到的是，該黏著構件也可以例如是在該堆疊之前，附接至該下方的半導體封裝的上表面。
根據本揭露內容的各種特點的一種堆疊的半導體封裝及/或 製造其之方法可以提供一些優點的任一者。
首先例如，一下方的半導體封裝以及一中介體可以利用一包括導電的微粒的黏著構件來彼此導電地連接並且同時黏著，藉此使得在該下方的半導體封裝與中介體之間藉由該些導電的微粒的電性信號的傳輸變得容易。
其次例如，包括導電的微粒的黏著構件可以附接至該下方的半導體封裝的整個上表面以及該中介體的整個下表面，因此增加在該下方的半導體封裝與該中介體之間的接合線的尺寸，並且強化在兩者之間的可接合性。
第三例如，由於在該下方的半導體封裝與該中介體之間的接合線的尺寸被增大並且在兩者之間的可接合性被強化，因此該中介體以及該下方的半導體封裝可以藉由該黏著構件而被保持，因此防止該中介體以及該下方的半導體封裝的邊緣部分由於在製程中的熱而翹曲。
第四例如，當包括導電的微粒的黏著構件被使用時，該些用於將該中介體堆疊在該下方的半導體封裝上的IO端子可以是由在一細微的間距(例如，<130μm、<100μm、等等)下的導電的(例如，銅、等等)柱或柱體所形成的。
第五例如，儘管一習知的堆疊式封裝是透過複數個製程來加以製造，其包含將堆疊的球體附接在該下方的半導體封裝上、將連接球體附接在該中介體上、在該模製化合物樹脂中藉由雷射處理來形成穿模貫孔以便於露出該些堆疊的球體、等等，但是根據此揭露內容的各種特點，研磨該模製化合物樹脂以露出該導電柱並且接著藉由該黏著構件來將該中介 體導電地連接在該導電柱上係有效率地加以實行，藉此減少製程的數目。
本揭露內容的各種特點之特徵在於一包括(或包含)導電的微粒的黏著構件的使用係使得在一下方的半導體封裝與一中介體之間的電性信號的傳輸變得容易(例如，在不造成互連的特點之間的短路下)，並且亦增加在該下方的半導體封裝與該中介體之間的接合線的尺寸以及在兩者之間的可接合性。
例如，一種被配置成使得一下方的半導體封裝以及一中介體係利用一包括導電的微粒的黏著構件加以堆疊之堆疊式封裝係在此說明性地加以敘述，但是此揭露內容的範疇並不限於此。例如，各種被導電地連接在單一封裝中的組成部件(或構件)，其包含一基板以及一基板、一基板以及一半導體晶片、一半導體晶片以及一半導體晶片、等等，都可以利用包括導電的微粒的黏著構件來加以導電地連接。
圖1係展示根據本揭露內容的各種特點的一種堆疊的半導體封裝的橫截面圖，並且圖2係展示描繪根據本揭露內容的各種特點的一種製造一堆疊的半導體封裝之方法的橫截面圖。
在圖1及2中，元件符號100係指明一下方的半導體封裝，並且元件符號200係指明一中介體，該中介體200係將該下方的半導體封裝100以及一上方的半導體封裝彼此導電地連接。
在一範例的實施方式中，為了製造該下方的半導體封裝100，一帶狀基板102(例如，一面板的基板)係被設置，其中複數個形成半導體封裝的區域例如可以用等距的間隔在其橫向及縱長方向上加以形成，並且一半導體晶片104係被堆疊在該帶狀基板102的形成半導體封裝的區域的 每一個的中心上並且附接至該中心。該半導體晶片104例如可以用各種方式的任一種且/或利用各種互連結構的任一種來附接至該基板102。例如，該半導體晶片104可以利用導電的凸塊106來附接至該基板102，例如是用以提供電性信號的交換。
用於堆疊的IO端子120(例如，各種互連結構的任一種)可以被熔接(例如，電鍍、焊接、等等)在一導電的圖案上，該導電的圖案係被形成在該半導體晶片104周圍的一週邊區域，例如是在該基板102的邊緣或週邊區域中。注意到的是，此揭露內容的範疇並不限於此種端子配置。用於堆疊的IO端子120例如可被使用於電連接至該中介體200。
例如，用於堆疊的IO端子120可包括具有細微的間距間隔(例如，<130μm、<100μm、等等)的導電柱(例如，銅柱或柱體、等等)。該些IO端子120例如可以藉由電鍍、引線接合、附接預先形成的柱、等等來加以形成。該些導電柱(或是柱體)例如可以包括垂直的側壁，此係容許有比導電球體所可能有的間隔為更密集的間隔。
該基板102的上表面例如可以是被囊封的。在一範例的實施方式中，該基板102的上表面可以利用一模製化合物樹脂110(或是其它的囊封材料)而被模製，因而該半導體晶片104以及用於堆疊的IO端子120係被密封(例如，全部或是部分被密封)，以便於被保護而與外部隔離。例如，為了強化由該半導體晶片104所產生的熱耗散至外部，該模製化合物樹脂110的上表面可被調整以與該半導體晶片104的上表面齊平的，因而該半導體晶片104的上表面係從該模製化合物樹脂110被露出到外部。
接著，當該範例的中介體200被堆疊在該下方的半導體封裝 100上時，其係導電地連接至用於堆疊的IO端子120以達成電性信號的交換。為此目的，該模製化合物樹脂110的上表面例如可以均勻地加以研磨，使得用於堆疊的IO端子120的上表面被露出至該模製化合物樹脂110的外部。該半導體晶片104的頂表面例如也可以在此時被露出及/或研磨。
一包括(或包含)導電的微粒212的黏著構件210係被附接至該中介體200的下表面。例如，包括導電的微粒212的黏著構件210係被堆疊在該中介體200的下表面以及該下方的半導體封裝100的上表面上並且附接至其，以便於將該下方的半導體封裝100以及該中介體200彼此導電地連接。注意到的是，該黏著構件210可以在耦接至該下方的半導體封裝100之前耦接至該中介體200，但是此並不是必要的情形。
該黏著構件210例如可以是以一包括(或包含)導電的微粒並且具有一預設的厚度之聚合物膜的形式來加以提供、或是該黏著構件210係以一包括(或包含)導電的微粒之聚合物膏的形式來加以提供。例如，該黏著構件210可包括一非等向性導電的膜及/或膏。如同在此論述的，該些導電的微粒可包括各種特徵的任一種。例如，該些導電的微粒可包括金球、碳球、覆蓋導體的塑膠球、等等。同樣例如的是，該些導電的微粒可包括各種尺寸的任一種(例如，5μm、4-6μm、3-10μm、等等的直徑或長度)。另外例如的是，該些導電的粒子可以是可壓縮的。在一範例的實施方式中，該些導電的微粒例如可以構成該膜或膏的1-5%，此例如是在將不會電連接的相鄰的互連特點之間提供絕緣。同樣如同在此論述的，該導電膏的厚度可包括各種厚度的任一種(例如，15-25μm、20-30μm、等等)。
該黏著構件210例如可以是附接至該中介體200的整個下表 面，並且接著在該中介體200被堆疊在該下方的半導體封裝100上時，可以被黏著至該下方的半導體封裝100的上表面(例如，整個上表面、等等)。注意到的是，該黏著構件210可以替代地在被黏著至該中介體之前，先黏著至該下方的半導體封裝100的上表面。
在一範例情節中，具有附接至其的黏著構件210之中介體200係被堆疊在該下方的半導體封裝100的上表面上而且附接至該上表面，因而藉由該黏著構件210的黏著來將該下方的半導體封裝100以及該中介體200彼此接合，同時亦藉由該黏著構件210的導電的微粒212來將該下方的半導體封裝100的IO端子120導電地連接至該中介體200的球體焊盤206。如同在此所解說的，在該黏著構件210中的導電的微粒212的密度可以是足夠小的，使得許多此種導電的微粒可以被捕陷在互連結構(例如，球體焊盤、IO端子、等等)之間，以在兩者之間形成一充分導電的路徑，但是在不應該是電連接的相鄰的互連結構之間並不提供一導電的路徑。
在將該中介體200堆疊在該下方的半導體封裝100上之際，該下方的半導體封裝100以及中介體200係藉由該黏著構件210的黏著來彼此接合，並且再者，如同在圖3中所繪，該下方的半導體封裝100的IO端子120係藉由該黏著構件210的導電的微粒212來導電地連接至該中介體200的球體焊盤206，該黏著構件210例如是被壓在該些端子120與球體焊盤206之間。
例如，當該中介體200被堆疊時，熱及壓力兩者可以同時施加至該黏著構件210，以將該下方的半導體封裝100以及中介體200彼此接合。例如，當具有膜或膏形式的黏著構件210藉由熱而被熔化時，該下方 的半導體封裝100以及中介體200係加以彼此接合。再者，如同在圖3中所繪，該黏著構件210的導電的微粒212將會藉由所施加的壓力來將該下方的半導體封裝100的IO端子120導電地連接至該中介體200的球體焊盤206。
以此種方式，該下方的半導體封裝100以及中介體200可以利用包括導電的微粒212的黏著構件210而被彼此導電地連接並且同時加以黏著，因而藉由該些導電的微粒212以使得在該下方的半導體封裝100與中介體200之間的電性信號的傳輸變得容易。再者，由於該黏著構件210可以附接至該下方的半導體封裝100的整個上表面以及附接至該中介體200的整個下表面，因此在該下方的半導體封裝100與中介體200之間的接合線的尺寸可被增大，並且在兩者之間的可接合性可以被強化，藉此防止該中介體以及該下方的半導體封裝的邊緣部分翹曲。
在另一範例的實施方式中，如同在圖4中所繪，一上方的半導體封裝300可以利用包括該導電的微粒212的黏著構件210來直接堆疊在該下方的半導體封裝100上，其例如是取代藉由該中介體來將該上方的半導體封裝堆疊於其上。圖4的範例實施方式可以和任何在此論述的其它實施方式(例如，相關於圖1-3、圖5)、其之個別的討論、等等共用任一或是所有的特徵。
該範例實施方式係提供一下方的半導體封裝100，其係包括一基板102；一半導體晶片104，其係附接至該基板102的上表面的中心；用於堆疊的IO端子120，其係附接至該基板102的上表面的邊緣部分；以及一模製化合物樹脂110，其係用於模覆該基板102，使得用於堆疊的IO端子120的上表面係被露出，同時密封該半導體晶片104以及用於堆疊的IO 端子120。再者，一包括導電的微粒212的黏著構件210可以附接至該下方的半導體封裝100的上表面。
接著，一上方的半導體封裝(例如，一具有球體焊盤的球格陣列封裝)係被接合至該黏著構件210的上表面。
藉由該黏著構件210的導電的微粒212，該下方的半導體封裝100的IO端子120(或是其它的互連結構)以及該上方的半導體封裝300的球體焊盤304(或是其它的互連結構)可以彼此導電地連接，並且同時，該下方的半導體封裝100以及上方的半導體封裝300可以藉由該黏著構件210的黏著而被彼此接合。注意到的是，各種互連結構的任一種都可被利用(例如，球體焊盤、墊、柱、等等)。
當包括(或包含)導電的微粒的黏著構件以此種方式被使用時，該上方的半導體封裝可以導電地連接至該下方的半導體封裝並且可以同時被接合至其，最終藉由該些導電的微粒以使得在該下方的半導體封裝與上方的半導體封裝之間的電性信號的傳輸變得容易。例如，該上方及下方的半導體封裝的導電及非導電的部分兩者都可以利用相同的黏著構件來加以耦接。
總之，此揭露內容的各種特點係提供一種堆疊的半導體封裝以及一種用於製造其之方法。例如且非限制性的，此揭露內容的各種特點係提供一種半導體封裝，其中一上方的中介體及/或封裝係利用一包括導電的微粒的黏著構件來電性及機械地耦接至一下方的封裝。儘管先前的內容已經參考某些特點以及例子來加以敘述，但是熟習此項技術者將會理解到可以做成各種的改變並且等同物可被用來取代，而不脫離該揭露內容的範 疇。此外，可以做成許多修改以將一特定的情況或材料適配於該揭露內容的教示，而不脫離其範疇。因此，所欲的是該揭露內容並不受限於所揭露的特定例子，而是該揭露內容將會包含所有落入所附的申請專利範圍的範疇內之例子。
100‧‧‧下方的半導體封裝
102‧‧‧帶狀基板
104‧‧‧半導體晶片
106‧‧‧導電的凸塊
109‧‧‧焊料球體
110‧‧‧模製化合物樹脂
120‧‧‧用於堆疊的IO端子
200‧‧‧中介體
202‧‧‧導電的墊
204‧‧‧貫孔孔洞
206‧‧‧球體焊盤
210‧‧‧黏著構件
212‧‧‧導電的微粒

Claims (20)

  1. 一種堆疊的半導體封裝，其係包括：一下方的半導體封裝，其係包括：一基板；一半導體晶片，其係附接至該基板的一上表面的一中心區域；複數個端子，其係附接至該基板的上表面的在該中心區域周圍的一週邊區域並且從該週邊區域向上延伸；以及一模製化合物，其係覆蓋該基板的上表面、該半導體晶片的側表面的至少一部分以及該些端子的每一個的一側表面的至少一部分，其中該些端子的每一個的至少一上表面係從該模製化合物露出；以及一中介體，其係包括在一下表面上的複數個接點；以及一黏著構件，其係將該中介體的下表面接合至該下方的半導體封裝的一上表面，其中該黏著構件係包括導電的微粒，該些導電的微粒係導電地耦接該下方的半導體封裝的該些端子的每一個以及該中介體的該些接點中的一個別的接點，以及其中該黏著構件直接接觸該中介體的該些接點的側表面。
  2. 如申請專利範圍第1項之堆疊的半導體封裝，其中該黏著構件係附接至該中介體的一整個下表面。
  3. 如申請專利範圍第2項之堆疊的半導體封裝，其中該黏著構件係附接至該下方的半導體封裝的一整個上表面。
  4. 如申請專利範圍第1項之堆疊的半導體封裝，其中該中介體包括一上 方的半導體封裝的一基板。
  5. 如申請專利範圍第1項之堆疊的半導體封裝，其中該黏著構件的該些導電的微粒具有比該黏著構件的厚度的三分之一還小的最大尺寸。
  6. 如申請專利範圍第1項之堆疊的半導體封裝，其中該黏著構件直接接觸該中介體的一基板。
  7. 如申請專利範圍第1項之堆疊的半導體封裝，其中在該些端子中的相鄰的端子之間，該黏著構件係包括並不將該些端子中的該些相鄰的端子彼此電耦接之導電的微粒。
  8. 如申請專利範圍第1項之堆疊的半導體封裝，其中該半導體晶片的一頂表面係從該模製化合物露出，並且該黏著構件係將該中介體的一下表面接合至該半導體晶片的頂表面。
  9. 一種堆疊的半導體封裝，其係包括：一下方的半導體封裝，其係包括：一基板；一半導體晶片，其係附接至該基板的一上表面的一中心區域；複數個端子，其係附接至該基板的上表面的在該中心區域周圍的一週邊部分，並且從該週邊部分向上延伸；以及一模製化合物，其係覆蓋該基板的上表面、該半導體晶片的側表面的至少一部分以及該些端子的每一個的一側表面的至少一部分，其中該些端子的每一個的至少一上表面係從該模製化合物露出；一中介體，其係包括在一下表面上的複數個接點；一黏著構件，其係將該中介體的該下表面接合至該下方的半導體封裝 的一上表面，其中該黏著構件係包括導電的微粒，該些導電的微粒係導電地耦接該下方的半導體封裝的該些端子的每一個以及該中介體的該些接點中的一個別的接點，其中該黏著構件具有在該中介體的該些接點正下方的垂直厚度，該垂直厚度比在該中介體的該些接點之間且在該中介體正下方的該黏著構件的垂直厚度還大。
  10. 如申請專利範圍第9項之堆疊的半導體封裝，其中該黏著構件係附接至該中介體的一整個下表面。
  11. 如申請專利範圍第10項之堆疊的半導體封裝，其中該黏著構件係附接至該下方的半導體封裝的一整個上表面。
  12. 如申請專利範圍第9項之堆疊的半導體封裝，其中該中介體包括一上方的半導體封裝的一基板。
  13. 如申請專利範圍第9項之堆疊的半導體封裝，其中該黏著構件的該些導電的微粒具有比該黏著構件的厚度的三分之一還小的最大尺寸。
  14. 如申請專利範圍第9項之堆疊的半導體封裝，其中該黏著構件直接接觸該中介體的一基板。
  15. 如申請專利範圍第9項之堆疊的半導體封裝，其中在該些端子中的相鄰的端子之間，該黏著構件係包括並不將該些端子中的該些相鄰的端子彼此電耦接之導電的微粒。
  16. 如申請專利範圍第9項之堆疊的半導體封裝，其中該半導體晶片的一頂表面係從該模製化合物露出，並且該黏著構件係將該中介體的下表面接合至該半導體晶片的頂表面。
  17. 一種堆疊的半導體封裝，其係包括：一下方的半導體封裝，其係包括一互連結構，該互連結構在一上表面上從一囊封材料露出；一中介體，其係包括在一下表面上的一互連結構；以及一黏著構件，其係將該中介體的下表面接合至該下方的半導體封裝的一上表面，其中該黏著構件係包括導電的微粒，該些導電的微粒係導電地耦接該下方的半導體封裝的該互連結構以及該中介體的該互連結構，其中該黏著構件的該些導電的微粒具有比在該中介體的互連結構與相的中介體的互連結構之間的間距的十分之一還小的最大尺寸。
  18. 如申請專利範圍第17項之堆疊的半導體封裝，其中該黏著構件係被附接至該中介體的整個下表面。
  19. 如申請專利範圍第17項之堆疊的半導體封裝，其中該黏著構件係包括一包括該些導電的微粒的黏著膜。
  20. 如申請專利範圍第17項之堆疊的半導體封裝，其中在該下方的半導體封裝的該互連結構與該下方的半導體封裝的一相鄰該互連結構的第二互連結構之間，該黏著構件係包括並不電耦接該互連結構以及該第二互連結構之導電的微粒。
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US20180180808A1 (en) * 2016-12-22 2018-06-28 Oracle International Corporation Wafer-level packaged optoelectronic module
US10527896B2 (en) * 2017-12-08 2020-01-07 L3 Technologies, Inc. Chip on glass protection
US10575393B1 (en) * 2018-11-13 2020-02-25 International Business Machines Corporation Heat-shielding microcapsules for protecting temperature sensitive components
US11616019B2 (en) * 2020-12-21 2023-03-28 Nvidia Corp. Semiconductor assembly

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200803677A (en) * 2006-06-01 2008-01-01 Phoenix Prec Technology Corp Stack structure of circuit board with semiconductor component embedded therein
TW201005913A (en) * 2008-07-17 2010-02-01 Powertech Technology Inc BGA package stacked with multiple substrates

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200803677A (en) * 2006-06-01 2008-01-01 Phoenix Prec Technology Corp Stack structure of circuit board with semiconductor component embedded therein
TW201005913A (en) * 2008-07-17 2010-02-01 Powertech Technology Inc BGA package stacked with multiple substrates

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