4 7 3 4 t wf / 0 0 2410484 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（I ) 本發明是有關於一種半導體製程，且特別是有關於 一種光二極體的製造方法。 光二極體的應用範圍很廣，例如像光影像感應器、 數位式相機、PC視頻-相干（vedio-coferenceing)條碼閱讀 器等等，都使用到光二極體。 影響光二極體的靈敏度因素中，最重要的莫過於其 暗電流（dark current)。然而，在使用習知淺溝渠隔離 (Shallow Trench Isolation ; STI)技術所製作的光二極體， 往往在接合面的邊緣上形成很高的電場。這種高電場易 形成暗電流的遺漏路徑（leakage path)，而產生的很強的 光二極體暗電流。這種現象，在0.25微米及其以下的半 導體製造技術中尤其嚴重。 第1A至1E圖繪示習知一種光二極體的製造方法 請參照第1A圖，於基底100上依序形成墊氧化層 102、氮化矽層104、和光阻圖案106。 請參照第1B圖，以光阻圖案106爲罩幕，蝕刻基底 100，以於基底1〇〇中形成一溝渠108。接著，於溝渠108 中形成氧化層120塡滿開口 108並覆蓋氮化矽層104。 請參照第1C圖，去除氮化矽層104上的氧化層120a。 請參照第ID圖，去除氮化砂層104和墊氧化層102， 此時氧化層120a(第1C圖）會遭部份移除（partially removed)。此時留下的氧化層標記爲120b。 請參照第1E圖，進行P井區126、N井區122、P + 型區124、N +型區128等區域的摻雜。這些區域可利用 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---.Ί! J---©--------訂---------線 ^ 」 - (請先閱讀t面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 473441Ό4°84 at _____Β7_ 五、發明說明（> ) 離子植入法，配合不同罩幕而以適當的操作條件達成所 需的濃度與深度。第1Ε圖繪示的更包括周邊的情形，因 而其氧化插塞120的數目不止一個。Ν井區122、Ρ井區 126、Ρ+型區124、Ν+型區128，其相對位置如圖中所示。 圖中並顯示一個Ρ-Ν接合面136。這種接合面136的接 合面邊緣130很容形成遺漏路徑，而發生暗電流。 本發明提供一種光二極體的製造方法，係於提供的 基底上依序形成墊氧化層與氮化矽層。依序圖案化氮化 矽層、墊氧化層、和基底，以於基底中形成一開口。於 開口的側壁上形成一間隙壁。以間隙壁與氮化矽層爲一 罩幕，蝕刻基底，以於基底中形成一溝渠。用傳統淺溝 渠方法形成一氧化插塞塡滿溝渠與開口。於溝渠的兩側 分別形成一 Ρ井區與一 Ν井區。於開口的兩側分別形成 一：Ν +型區與一Ρ+型區，其中Ν+型區位於Ρ井區上，而 Ρ +型區位於Ν井區上。 本發明提供一種光二極體的製造方法，係於提供的 基底上依序形成一墊氧化層與一氮化矽層。依序圖案化 氮化矽層、墊氧化層' 和基底，以於基底中形成一開口。 於開口中形成一光阻圖案。以光阻圖案一罩幕，蝕刻基 底，以於基底中形成一溝渠。用傳統淺溝渠方法形成一 氧化插塞塡滿溝渠與開口。於溝渠的兩側分別形成一 Ρ 井區與一 Ν井區。於開口的兩側分別形成一 Ν +型區與一 Ρ +型區，其中Ν +型區位於Ρ井區上，而Ρ +型區位於Ν 井區上。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) JII&---- 訂-f I 丨 — J -------- A7 4 7 3 4 tfi〇°484 五、發明說明（3) 本發明提供一種光二極體的製造方法，係於提供的 基底上依序形成一墊氧化層與一圖案化之氧化矽層。以 熱氧化法形成一場氧化層。於圖案化之氧化矽層側壁上 形成一間隙壁。以間隙壁與圖案化之氧化矽層爲一罩幕， 蝕刻場氧化層與基底，以於基底中形成一溝渠。形成一 氧化層塡滿溝渠並覆蓋間隙壁與圖案化之氧化矽層。用 傳統淺溝渠方法形成一氧化插塞。於氧化插塞的兩側分 別形成一 P井區與一 N井區。於P井區上形成一 N+型 .區，且於N井區上形成一 P+型區，其中N+型區與P +型 區高於溝渠。 本發明提供一種光二極體的製造方法，係於提供的 基底上依序形成一墊氧化層與一圖案化之氮化矽層。以 熱氧化法形成一場氧化層。於場氧化層與圖案化之氮化 矽層上形成一光阻圖案。以光阻圖案爲一罩幕，蝕刻場 氧化層與基底，以於基底中形成一溝渠，其中溝渠位於 場氧化層下，且窄於場氧化層。去除光阻圖案。形成一 氧化層塡滿溝渠並覆蓋場氧化層與圖案化之氮化矽層。 用傳統淺溝渠方法形成一氧化插塞。於氧化插塞的兩側 分別形成一 P井區與一 N井區。於P井區上形成一 N+ 型區，且於N井區上形成一 P +型區，其中N+型區與P + 型區高於溝渠。 本發明至少具有增加崩潰電壓、減少P-N接合面的 漏電流、減少光二極體的暗電流、以及應用在光感應器 時，可增進靈敏度等優點。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印 -----11 —訂·!---—-線-I — *----τ--- 經濟部智慧財產局員工消費合作社印製 34JM484 A7 _B7_ 五、發明說明（Y) 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A至1E圖繪示習知一種光二極體的製造方法； 第2圖繪示根據本發明所製作之光二極體的剖面示 意圖； 第3A圖繪示一擴散程序所造成的P-N接合面結構示 意圖； 第3B圖繪示根據第3A圖，不同曲率的極性區構造， 崩潰電壓對摻質濃度的關係圖； 第4A至4E圖繪示根據本發明，一種光二極體的製 造方法； 第5A至5E圖繪示根據本發明，一種光二極體的製 造方法； 第6A至6E圖繪示根據本發明，一種光二極體的製 造方法；以及 第7A至7E圖繪示根據本發明，一種光二極體的製 造方法。 圖式標記說明： 100 :矽基底 122 ' 202 ' 422、522 ' 622 ' 722 : N 井區 124、204 ' 424 ' 524、624 ' 724 · P+型區 126、206、426、526、626 ' 726 : P 井區 (請先閱讀背面之注意事項再填寫本頁) -* --------訂—---------------τ-- 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 4_7 34twf/〇〇2410484 五、發明說明（f) A7 B7 128 136 130 200 108 214 208、428、528、628、728 : N+型區 2]6 :接合面 接合面邊緣 500 、 600 、 700 414 、 514 、 614 508 :開口 220 400 212 408 210a :絕緣層 210b ' 420 ' 520 102 、 402 、 502 104 、 404 ' 504 1.06、406、506 410 > 608 ' 708 基底 714 :溝渠 620 ' 720 :氧化插塞（絕緣層） 602 :墊氧化層 604、704 :氮化矽層 512、712 :光阻圖案 氧化層 4 1 2、6 1 2 :間隙壁 120 ' 120a、120b、606 :氧化砂層 第一實施例 (請先朋讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 第2圖繪示根據本發明所製作之光二極體的剖面示 思圖。 請參照第2圖，此光二極體具有一個接合面216，係 由極性相反的兩個區域所構成。這些區域的材質可以是 具有摻質的矽。當摻質爲Ν+型摻質時，第一極性區則可 視爲Ν +型區202 ;當摻質爲Ρ +型摻質時，第一極性區則 視爲Ρ +型區206。以第一極性區視作Ν+型區202爲例， 在接合面216的邊緣220上，第一極性區202是平坦而 不具轉角的。至於位在第一極性區202上的第二極性區 -01--------訂---------線丨/ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） "*^W*4<*>£^0〇2 A7 "*^W*4<*>£^0〇2 A7 經濟部智慧財產局員工消費合作社印製 ___B7___ 五、發明說明（f ) 2〇4，其極性與第一極性區202相反，且具有一個轉角， 如圖中的圓圏內所示。除此之外，第二極性區204更與 一絕緣層210a相鄰，而這個絕緣層210a也與第一區域202 鄰接^ 更仔細地說，此光二極體的結構係至少由三個構件 所組成。這三個構件可以是一P+型區204、一 N+型區 2 0 2、和一絕緣層2 10 a。它們都位於一個材質例如是砂的 基底200上。其中，P+型區204與N+型區202之間具有 —P-N接合面216。這兩個區域202、204 —個在上，一 個在下。至於何者在上，何者在下，可視製程或結構之 需要而定。於此，吾人稱呼在下的爲第一極性區，而在 上的爲第二極性區。至於絕緣層210a、210b，則位於第 二極性區204的兩側，並覆蓋位在下面的第一極性區 2〇2。其中，左側的絕緣層標記爲210a，右側則爲210b。 第一極性區202的寬度較寬，第二極性區204的寬 度較窄，所以第二極性區204可以整個座落在第一極性 區202上。也因此，在P-N接合面216上，尤其在P-N 接合面216的邊緣220上，只會有第二極性區204的轉 角，而不會有第一極性區2 0 2的轉角。換句話說，第一 極性區202在P-N接合面216上所呈現的，是一個平坦 的表面。表面平坦，也就是說接合面曲率（junction curvature)很小，亦即接合面曲率半徑(junction curvature radius)很大，有助於增加崩潰電壓，亦有助於減少接合 面的漏電流。也可以說，有助於減少光二極體的暗電流。 _______ Κ ί;張尺度適用中國國家標準（CNS>A4規格（210 x 297公楚〉 (請先閱讀背面之注意事項再填寫本頁) ί --- 經濟部智慧財產局員工消費合作社印製 4734twf/〇〇2 Δ7 410484_B7__ 五、發明說明（Ί) 也因此，當應用於光感應器的製作時，本發明可以增進 光感應器的靈敏度。 此外，像這樣的光二極體結構，可以透過製程條件 的最佳化來達成。而且，這種光二極體特別適用於0.25 微米及其以下的半導體製程。 本發明可應用於製作一種淺溝渠隔離結構。如第2 圖所示，這個淺溝渠隔離結構包括了 一個氧化插塞210b。 這個氧化插塞210b係塡充在一個由第一極性區202、208 與第二極性區2〇4、2〇6組成的開口中。不過，這裡的極 性"偶區（area pair)”共有兩組。其中一組是N+型區202在 下，P +型區204在上。而另外一組則爲P +型區206在下， N+型區208在上。位在下面的區域202、206彼此相鄰， 都屬於一種井區。但位在上面的區域204、208，以及下 方區域202、206中接近上面區域204、208的地方，則 是分開的，因而構成所要的淺溝渠。 另一種說法是，此淺溝渠隔離結構具有N井區202 與P井區206，這N井區202與P井區206相鄰處上共 同構成一溝渠212。此外，此淺溝渠隔離結構更包括一 P+ 型區204與一N +型區208，分別位於N井區202和P井 區206上。P+型區204與N+型區208彼此並不相鄰，但 .共同構成一開口 214完全暴露出下方的溝渠212，因爲 此開口 2 14的寬度大於溝渠212的寬度。此開口 214與 溝渠2 1 2，共同組成所謂的淺溝渠，而被一 T型氧化插 塞2 1 0 b完全填滿。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ^----------訂！-----線！ 4734twf/002 A7 4734twf/002 A7 經濟部智慧財產局員工消費合作社印製 -41G侧--- 五、發明說明（g ) 於此特別要說明的是，崩潰電壓的重要考慮因素之 —爲曲率效應（curvature effect)。請參照第3A圖，其所 繪示爲一擴散程序所造成的P-N接合面結構示意圖。圖 中斜線區係爲一已開窗的絕緣層，而絕緣層下的基底區 例如爲N型區，至於在絕緣層與N型區之間，從窗口擴 散開來的即爲P型區。P型區中的X』指的是曲率半徑。 一般而言，曲率半徑越大，表示曲率越小。 第3B圖繪示根據第3A圖，不同曲率的極性區構造， 崩潰電壓對摻質濃度的關係圖。較上方的曲線表示曲率 104半徑X」較大的極性區構造，較下方的表示曲率半徑 X」較小的極性區構造。橫軸表示摻質濃度，縱軸表示崩 潰電壓。最上面的曲線則表示平坦的接合面（Χρ〇〇，表 幾乎沒有曲率），崩潰電壓對摻質濃度的關係曲線。由圖 中吾人可以瞭解，在同一摻質濃度情況下，曲率半徑Xj 越大（越平坦）的極性區構造，其所造成的崩潰電壓也越 大，因其接合面遺漏(junction leakage)也越低。 至於這種淺溝渠隔離結構的製造方法，請參閱以下 第二至第五實施例。 第二實施例 第4A至4E圖繪示根據本發明，一種光二極體的製 造方法。 請參照第4A圖，於基底400上依序形成墊氧化層 402、氮化矽層404、和光阻圖案406。 請參照第4B圖，以光阻圖案406爲罩幕，蝕刻基底 1 0 本紙張尺度適用中國國家標準（CNS>A4規袼（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) #!1 訂· — -線--TV——\——-iIL----=--------- A7 經濟部智慧財產局員工消費合作社印製 4734twf/002 _41Q4R4_B7__ 五、發明說明（9 ) 400，以於基底400中形成一開口 408 = 請寥照第4C圖，於開口 408與氮化较層404上形成 一薄氧化層4 1 0。 請參照第4D圖，非等向性蝕刻薄氧化層410(第4C 圖），以於開口 408(第4C圖）側壁上形成間隙壁412。接 著，以間隙壁412與氮化矽層404爲罩幕，蝕刻基底400， 以於基底400中形成一溝渠414。 請參照第4E圖，以同傳統矽槽淺溝渠的作法，形成 一氧化插塞420塡滿開口 408與溝渠414(第4D圖）。之 後，進行P井區426、N井區422、P+型區424、N+型區 428等區域的摻雜。這些區域可利用離子植入法，配合 不同罩幕而以適當的操作條件達成所需的濃度與深度。 第4E圖繪示的更包括周邊的情形，因而其氧化插塞420 的數目不止一個。 特別要說明的是，離子植入的深度控制是可以在很 小的誤差範圍內的，也就是約0.05微米。而這裡的P+型 區424與N+型區428的深度較佳約爲500至2000埃。 此外，這些區域的摻雜步驟並不限定於此時進行。 其亦可能於其他步驟的前後實施，這些皆是熟悉此技藝 者所能輕易完成。 第三實施例 第5A至5E圖繪示根據本發明，一種光二極體的製 造方法。 請參照第5A圖，於基底500上依序形成墊氧化層4 7 3 4 t wf / 0 0 2410484 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (I) The present invention relates to a semiconductor process, and in particular to a method for manufacturing a photodiode . Photodiodes are used in a wide range of applications, such as light image sensors, digital cameras, PC video-coordinated bar code readers, etc., all using photodiodes. Among the factors that affect the sensitivity of a photodiode, the most important is its dark current. However, photodiodes made using the conventional Shallow Trench Isolation (STI) technology often form a very high electric field on the edges of the junction. Such a high electric field easily forms a leakage path of dark current, and generates a strong photodiode dark current. This phenomenon is particularly serious in semiconductor manufacturing technology of 0.25 microns and below. 1A to 1E illustrate a conventional method for manufacturing a photodiode. Referring to FIG. 1A, a pad oxide layer 102, a silicon nitride layer 104, and a photoresist pattern 106 are sequentially formed on a substrate 100. Referring to FIG. 1B, the photoresist pattern 106 is used as a mask to etch the substrate 100 to form a trench 108 in the substrate 100. Next, an oxide layer 120 is formed in the trench 108 to fill the opening 108 and cover the silicon nitride layer 104. Referring to FIG. 1C, the oxide layer 120a on the silicon nitride layer 104 is removed. Referring to FIG. ID, the nitrided sand layer 104 and the pad oxide layer 102 are removed. At this time, the oxide layer 120a (FIG. 1C) is partially removed. The oxide layer left at this time is labeled 120b. Referring to FIG. 1E, doping of regions such as the P-well region 126, the N-well region 122, the P + -type region 124, and the N + -type region 128 is performed. These areas can use 3 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) ---. Ί! J --- © -------- Order ------ --- line ^ "-(Please read the precautions on t side before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 473441Ό4 ° 84 at _____ Β7_ V. Description of the invention (>) Ion implantation method Different shades can be used to achieve the required concentration and depth under appropriate operating conditions. Figure 1E shows the surrounding situation, so the number of oxidation plugs 120 is more than one. The relative positions of the N-well region 122, the P-well region 126, the P + -type region 124, and the N + -type region 128 are shown in the figure. Also shown in the figure is a P-N junction 136. The joint surface edge 130 of the joint surface 136 is apt to form a missing path and cause dark current to occur. The invention provides a method for manufacturing a photodiode, which sequentially forms a pad oxide layer and a silicon nitride layer on a provided substrate. The silicon nitride layer, the pad oxide layer, and the substrate are sequentially patterned to form an opening in the substrate. A gap wall is formed on the side wall of the opening. Using the spacer and the silicon nitride layer as a mask, the substrate is etched to form a trench in the substrate. A conventional shallow trench method is used to form an oxide plug that fills the trench and opening. A well P and a well N are formed on both sides of the trench. One is formed on both sides of the opening: an N + -type region and a P + -type region, wherein the N + -type region is located on the P-well region and the P + -type region is located on the N-well region. The invention provides a method for manufacturing a photodiode, which sequentially forms a pad oxide layer and a silicon nitride layer on a provided substrate. The silicon nitride layer, the pad oxide layer 'and the substrate are sequentially patterned to form an opening in the substrate. A photoresist pattern is formed in the opening. Using a photoresist pattern as a mask, the substrate is etched to form a trench in the substrate. A conventional shallow trench method is used to form an oxide plug that fills the trench and opening. A well P and a well N are formed on both sides of the trench. An N + -type region and a P + -type region are respectively formed on both sides of the opening, wherein the N + -type region is located on the P-well region and the P + -type region is located on the N-well region. 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) JII & ---- Order -f I 丨 — J ---- ---- A7 4 7 3 4 tfi0 ° 484 5. Description of the invention (3) The present invention provides a method for manufacturing a photodiode, which sequentially forms a pad oxide layer and a patterned oxidation on the provided substrate. Silicon layer. A field oxide layer is formed by thermal oxidation. A spacer is formed on the sidewall of the patterned silicon oxide layer. With the spacer and the patterned silicon oxide layer as a mask, the field oxide layer and the substrate are etched to form a trench in the substrate. An oxide layer is formed to fill the trench and cover the spacer and the patterned silicon oxide layer. A conventional shallow trench method is used to form an oxide plug. A P well area and an N well area are formed on both sides of the oxidation plug. An N + -type .region is formed on the P-well region, and a P + -type region is formed on the N-well region. The N + -type region and the P + -type region are higher than the trench. The invention provides a method for manufacturing a photodiode, which sequentially forms a pad oxide layer and a patterned silicon nitride layer on the provided substrate. A field oxide layer is formed by thermal oxidation. A photoresist pattern is formed on the field oxide layer and the patterned silicon nitride layer. Using the photoresist pattern as a mask, the field oxide layer and the substrate are etched to form a trench in the substrate, wherein the trench is located below the field oxide layer and is narrower than the field oxide layer. Remove the photoresist pattern. An oxide layer fills the trench and covers the field oxide layer and the patterned silicon nitride layer. A conventional shallow trench method is used to form an oxide plug. A P well area and an N well area are formed on both sides of the oxidation plug, respectively. An N + -type region is formed on the P-well region, and a P + -type region is formed on the N-well region. The N + -type region and the P + -type region are higher than the trench. The invention has at least the advantages of increasing the breakdown voltage, reducing the leakage current of the P-N junction, reducing the dark current of the photodiode, and improving the sensitivity when used in a photo sensor. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). ! ---—- Line-I — * ---- τ --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 34JM484 A7 _B7_ V. Description of the Invention (Y) In order to make the above and other objects and features of the present invention , And advantages can be more obvious and easy to understand, the following specific examples are given in conjunction with the accompanying drawings to explain in detail as follows: Brief description of the drawings: Figures 1A to 1E show the conventional manufacturing of a photodiode Method; Figure 2 shows a schematic cross-sectional view of a photodiode made according to the present invention; Figure 3A shows a schematic diagram of the structure of a PN junction surface caused by a diffusion process; Figure 3B shows different curvatures according to Figure 3A Polar region structure, breakdown voltage vs. dopant concentration; Figures 4A to 4E illustrate a method of manufacturing a photodiode according to the present invention; Figures 5A to 5E illustrate a method of manufacturing a photodiode according to the present invention Method; Figures 6A to 6E show , A method of manufacturing an optical diode; and a second FIG. 7A to 7E illustrate the present invention, a method of manufacturing an optical diode body. Schematic description: 100: Silicon substrate 122 '202' 422, 522 '622' 722: N well area 124, 204 '424' 524, 624 '724P + type area 126, 206, 426, 526, 626' 726 : P well area (please read the precautions on the back before filling this page)-* -------- Order ----------------- τ-- This paper size Applicable to China National Standard (CNS) A4 specification (210x 297 mm) 4_7 34twf / 〇〇2410484 V. Description of the invention (f) A7 B7 128 136 130 200 108 214 208, 428, 528, 628, 728: N + zone 2 ] 6: Joint surface Joint surface edges 500, 600, 700 414, 514, 614 508: Opening 220 400 212 408 210a: Insulation layer 210b '420' 520 102, 402, 502 104, 404 '504 1.06, 406, 506 410 > 608 '708 substrate 714: trench 620' 720: oxide plug (insulating layer) 602: pad oxide layer 604, 704: silicon nitride layer 512, 712: photoresist pattern oxide layer 4 1 2, 6 1 2: Partition wall 120 '120a, 120b, 606: First embodiment of oxidized sand layer (please read the precautions on the back before filling out this page) Printed by the consumer cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Schematic diagram of a cross section of a photodiode made in the Ming Dynasty. Please refer to Fig. 2. This photodiode has a joint surface 216, which is composed of two regions with opposite polarities. These areas can be made of doped silicon. When the dopant is an N + type dopant, the first polar region can be regarded as an N + type region 202; when the dopant is a P + type dopant, the first polar region can be regarded as a P + type region 206. Taking the first polar region as the N + type region 202 as an example, the first polar region 202 is flat and has no corner on the edge 220 of the joint surface 216. As for the second polarity area-01 located on the first polarity area 202 -------- order --------- line 丨 / This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) " * ^ W * 4 < * > £ ^ 0〇2 A7 " * ^ W * 4 < * > £ ^ 0〇2 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ___B7___ 5. Description of the invention (f) 204, the polarity of which is opposite to that of the first polarity region 202, and has a corner, as shown in the circle in the figure. In addition, the second polar region 204 is adjacent to an insulating layer 210a, and this insulating layer 210a is also adjacent to the first region 202. More specifically, the structure of the photodiode is composed of at least three components. composition. The three components may be a P + -type region 204, an N + -type region 202, and an insulating layer 210a. They are all located on a substrate 200 made of, for example, sand. Among them, a P-N junction 216 is provided between the P + type region 204 and the N + type region 202. These two areas 202, 204 are one above and one below. Which one is up and which is down depends on the needs of the process or structure. Here, we call the first polar region below, and the second polar region above. As for the insulating layers 210a and 210b, they are located on both sides of the second polarity region 204 and cover the first polarity region 202 located below. Among them, the insulating layer on the left is labeled 210a, and the right is 210b. The width of the first polar region 202 is wider, and the width of the second polar region 204 is narrower, so the second polar region 204 can be entirely located on the first polar region 202. Therefore, on the P-N junction surface 216, especially on the edge 220 of the P-N junction surface 216, there will only be a corner of the second polar region 204, and there will be no corner of the first polar region 202. In other words, the first polar region 202 appears on the P-N junction 216 as a flat surface. The surface is flat, that is, the junction curvature is small, that is, the junction curvature radius is large, which helps increase the breakdown voltage and also reduces the leakage current of the junction. It can also be said to help reduce the dark current of the photodiode. _______ Κ; Zhang scale is applicable to Chinese National Standards (CNS > A4 specification (210 x 297 Gongchu) (Please read the precautions on the back before filling this page) ί --- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4734twf / 〇〇2 Δ7 410484_B7__ 5. Description of the invention (Ί) Therefore, when applied to the production of a light sensor, the present invention can improve the sensitivity of the light sensor. In addition, a photodiode structure like this can pass through process conditions This photodiode is particularly suitable for semiconductor processes of 0.25 microns and below. The invention can be applied to make a shallow trench isolation structure. As shown in Figure 2, this shallow trench isolation structure An oxidation plug 210b is included. This oxidation plug 210b is filled in an opening composed of the first polar regions 202,208 and the second polar regions 204,206. However, the polarity here " There are two sets of "area pair". One of them is N + -type region 202 below, P + -type region 204 above. The other group is P + -type region 206 below, and N + -type region 208 is above. In the area below 202 and 206 are adjacent to each other and belong to a kind of well area. However, the upper areas 204 and 208 and the lower areas 202 and 206 which are close to the upper areas 204 and 208 are separated, thus forming the desired shallow trench. Another way of saying is that this shallow trench isolation structure has N well area 202 and P well area 206, and the N well area 202 and P well area 206 are adjacent to form a trench 212. In addition, this shallow trench isolation structure is more Including a P + type region 204 and an N + type region 208, which are located on the N well region 202 and the P well region 206, respectively. The P + type region 204 and the N + type region 208 are not adjacent to each other, but together form an opening 214 completely The trench 212 below is exposed because the width of the opening 2 14 is greater than the width of the trench 212. The opening 214 and the trench 2 1 2 together form a so-called shallow trench, which is completely filled with a T-shaped oxidation plug 2 1 0 b This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ^ ---------- Order! --Line! 4734twf / 002 A7 4734twf / 002 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-41G Side --- V. Description of the invention (g) It is important to note here that one of the important considerations of the collapse voltage is the curvature effect. Please refer to Figure 3A, which is shown as a diffusion program. Schematic diagram of the structure of the resulting PN junction. The oblique line in the figure is an insulation layer with a window open, and the base area under the insulation layer is, for example, an N-type area. As for the insulation layer and the N-type area, the window diffuses away Here comes the P-type region. X ′ in the P-type region refers to the radius of curvature. In general, the larger the radius of curvature, the smaller the curvature. FIG. 3B shows the relationship between the breakdown voltage structure and the dopant concentration according to the structure of the polar regions with different curvatures according to FIG. 3A. The upper curve shows the structure of a polar region with a larger radius of curvature 104 "and the lower curve shows the structure of a polar region with a smaller radius of curvature X". The horizontal axis represents the dopant concentration, and the vertical axis represents the collapse voltage. The top curve represents the flat joint surface (Xρ〇, the table has almost no curvature), and the relationship between the breakdown voltage and the dopant concentration. From the figure, we can understand that under the same dopant concentration, the larger (flatter) the radius of curvature of the polar region structure, the greater the breakdown voltage caused by it, and the greater the junction leakage. low. As for the manufacturing method of such a shallow trench isolation structure, please refer to the following second to fifth embodiments. Second Embodiment Figures 4A to 4E illustrate a method for manufacturing a photodiode according to the present invention. Referring to FIG. 4A, a pad oxide layer 402, a silicon nitride layer 404, and a photoresist pattern 406 are sequentially formed on the substrate 400. Please refer to Figure 4B, using the photoresist pattern 406 as the cover, and etching the substrate. 10 This paper size applies the Chinese National Standard (CNS > A4 Regulation (210 X 297 mm). (Please read the precautions on the back before filling in this Page) #! 1 Order · — --- TV —— \ ——- iIL ---- = --------- A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4734twf / 002 _41Q4R4_B7__ 5 Explanation of the invention (9) 400, so as to form an opening 408 in the substrate 400 = Please refer to FIG. 4C to form a thin oxide layer 4 1 0 on the opening 408 and the nitrided layer 404. Please refer to FIG. 4D, Anisotropically etch the thin oxide layer 410 (Figure 4C) to form a spacer 412 on the side wall of the opening 408 (Figure 4C). Next, the substrate 400 is etched with the spacer 412 and the silicon nitride layer 404 as a mask. A trench 414 is formed in the substrate 400. Please refer to FIG. 4E, in the same manner as the conventional silicon trench shallow trench, to form an oxide plug 420 that fills the opening 408 and the trench 414 (FIG. 4D). Then, perform P Doping of wells 426, N-wells 422, P + -type regions 424, N + -type regions 428, etc. These regions can be ion implanted with different masks. To achieve the required concentration and depth with appropriate operating conditions. Figure 4E shows the surrounding conditions, so there are more than one oxidation plug 420. In particular, the depth control of the ion implantation is It can be within a small error range, that is, about 0.05 micrometers. Here, the depth of the P + type region 424 and the N + type region 428 is preferably about 500 to 2000 angstroms. In addition, the doping steps of these regions are not limited. It is performed at this time. It may also be implemented before and after other steps, which can be easily accomplished by those skilled in the art. Figures 5A to 5E of the third embodiment illustrate a method of manufacturing a photodiode according to the present invention. Referring to FIG. 5A, a pad oxide layer is sequentially formed on the substrate 500.
L I 本紙張尺度適用中國國家標準（CNS)A4規格<210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁)L I This paper size applies to China National Standard (CNS) A4 specifications < 210 x 297 mm) (Please read the notes on the back before filling this page)
A7 B7 4734twf/〇〇2 410484 五、發明說明（) 502、氮化矽層504、和光阻圖案506。 請參照第5B圖，以光阻圖案506爲罩幕，蝕刻基底 5 00，以於基底500中彤成一開口 508。 請參照第5C圖，形成一光阻層510塡滿開口 508並 覆蓋氮化矽層504。 請參照第5D圖，以習知微影技術將光阻層510(第5C 圖）轉爲光阻圖案512。接著，以光阻圖案512爲罩幕，蝕 刻基底500以於基底500中形成一溝渠514。其中，溝渠 5 14位於開口 508下，且窄於開口 508。 請參照第5E圖，以同傳統矽槽淺溝渠的作法，形成 一氧化插塞520塡滿開口 508與溝渠5 14(第5D圖）。之 後，進行P井區526、N井區522、P+型區524、N+型區 528等區域的摻雜。這些區域可利用離子植入法，配合 不同罩幕而以適當的操作條件達成所需的濃度與深度。 第5E圖繪示的更包括周邊的情形，因而其氧化插塞520 的數目不止一個。 特別要說明的是，離子植入的深度控制是可以在很 小的誤差範圍內的，也就是約0.05微米。而這裡的P+型 區524與N+型區528的深度較佳約爲500至2000埃。 此外，這些區域的摻雜步驟並不限定於此時進行。 其亦可能於其他步驟的前後實施，這些皆是熟悉此技藝 者所能輕易完成。 第四實施例 第6A至6E圖繪示根據本發明，一種光二極體的製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） {請先閱讀背面之注意事項再填寫本頁) -1 -------訂---- 經濟部智慧財產局員工消費合作社印製 -線 I -^^一----^---”---,·1·---'-- A7 B7 4734twf/002 410484 五、發明說明（f丨） 造方法。當然’也可說是一種淺溝渠隔離結構的製造方 •法。 請參照第6A圖，在一基底600上依序形成墊氧化層 602與氧化矽罩幕圖案604後，以熱氧化法成長場氧化 層 6 1 0 0 請參照第6 B圖，形成一氧化砂層6 0 6覆蓋場氧化層 610與氧化砂罩幕圖案604。 請參照第6C圖，回蝕刻氧化矽層606(第6B圖），以 於氧化矽罩幕圖案604缺口側壁上形成氧化矽間隙壁 612。 請參照第6D圖，以氧化矽罩幕圖案604與氧化矽間 隙壁612爲罩幕，蝕刻場氧化層610與基底600，以於 基底600中形成溝渠614。接著，形成氧化層608塡滿 溝渠並覆蓋整個基底600結構。 請參照第6E圖，以同傳統矽槽淺溝渠的作法，形成 一氧化插塞620。其中，所完成的氧化插塞620係由部 份的氧化層608(第6D圖）與部份的場氧化層610(第6D 圖）所組成。之後，進行P井區626、N井區622、P+型 區624、N+型區628等區域的摻雜。其中N+型區628與 P +型區624高於溝渠6H(第6D圖）。這些區域可利用離 子植入法，配合不同罩幕而以適當的操作條件達成所需 的濃度與深度。第6E圖繪示的更包括周邊的情形，因而 其氧化插塞620的數目不止一個。 特別要說明的是，離子植入的深度控制是可以在很 (請先閱讀背面之注意事項再填寫本頁) 0— 訂---------線！ 經濟部智慧財產局員工消費合作社印製 中國國家標準（CNS)A4規格（210 X 297公釐） 4 7 3 4射的§4 A7 _B7_ 五、發明說明（β) 小的誤差範圍內的，也就是約0.05微米。而這裡的Ρ+型 區624與Ν+型區628的深度較佳約爲500至2000埃。 此外，這些區域的摻雜步驟並不限定於此時進行。 其亦可能於其他步驟的前後實施，這些皆是熟悉此技藝 者所能輕易完成。 第五實施例 第7Α至7Ε圖繪示根據本發明，一種光二極體的製 造方法。當然，也可說是一種淺溝渠隔離結構的製造方 法。 請參照第7Α圖，在一基底700上形成氮化矽罩幕圖 案704後，以熱氧化法成長場氧化層7 1 0。 請參照第7Β圖，形成一光阻層706覆蓋場氧化層7 1 0 與氮化矽罩幕圖案704。 請參照第7C圖，以習知微影技術將光阻層706轉爲 光阻圖案712。 請參照第7D圖，以光阻圖案712爲罩幕，蝕刻場氧 化層710與基底700，以於基底700中形成溝渠714。其 中溝渠714位於場氧化層710下，且窄於場氧化層710。 接著，去除光阻圖案712。之後，形成氧化層708塡滿 溝渠並覆蓋整個基底700結構。 請參照第7Ε圖，以同傳統矽槽淺溝渠的作法，完成 的氧化插塞720係由部份的氧化層708(第7D圖）與部份 的場氧化層710(第7D圖）所組成。之後，進行Ρ井區727、 Ν井區722、Ρ +型區724、Ν+型區728等區域的摻雜。 (請先閱讀背面之注意事項再填寫本頁) 丨----丨I —丨訂·--------1 _ 經濟部智慧財產局員工消費合作社印製A7 B7 4734twf / 〇〇2 410484 V. Description of the invention () 502, silicon nitride layer 504, and photoresist pattern 506. Referring to FIG. 5B, the photoresist pattern 506 is used as a mask, and the substrate 500 is etched to form an opening 508 in the substrate 500. Referring to FIG. 5C, a photoresist layer 510 is formed to fill the opening 508 and cover the silicon nitride layer 504. Referring to FIG. 5D, the photoresist layer 510 (FIG. 5C) is converted into a photoresist pattern 512 by a conventional lithography technique. Next, using the photoresist pattern 512 as a mask, the substrate 500 is etched to form a trench 514 in the substrate 500. The trench 514 is located below the opening 508 and is narrower than the opening 508. Please refer to FIG. 5E, in the same way as the shallow trench of the conventional silicon trench, to form an oxide plug 520 that fills the opening 508 and the trench 5 14 (FIG. 5D). After that, the P-well region 526, the N-well region 522, the P + -type region 524, and the N + -type region 528 are doped. These areas can be ion implanted to match the different masks to achieve the desired concentration and depth under appropriate operating conditions. FIG. 5E shows the surrounding situation, so the number of oxidation plugs 520 is more than one. In particular, the depth control of the ion implantation can be within a small error range, that is, about 0.05 microns. The depth of the P + -type region 524 and the N + -type region 528 here is preferably about 500 to 2000 Angstroms. In addition, the doping steps in these regions are not limited to be performed at this time. It may also be implemented before and after other steps, which can be easily done by those skilled in the art. Figures 6A to 6E of the fourth embodiment show that according to the present invention, the paper size of a photodiode is adapted to the Chinese National Standard (CNS) A4 (210x297 mm) {Please read the precautions on the back before filling this page) -1 ------- Order ---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -line I-^^ 一 ---- ^ --- "---, · 1 · --- '-A7 B7 4734twf / 002 410484 V. Description of the invention (f 丨) Manufacturing method. Of course, it can also be said to be a manufacturing method and method of shallow trench isolation structure. Please refer to FIG. 6A and sequentially on a substrate 600 After the pad oxide layer 602 and the silicon oxide mask pattern 604 are formed, the field oxide layer 6 1 0 0 is grown by a thermal oxidation method. Please refer to FIG. 6B to form an oxide sand layer 6 0 6 to cover the field oxide layer 610 and the oxide sand mask. Pattern 604. Referring to FIG. 6C, the silicon oxide layer 606 (FIG. 6B) is etched back to form a silicon oxide spacer 612 on the notched sidewall of the silicon oxide mask pattern 604. Referring to FIG. 6D, a silicon oxide mask is used. The pattern 604 and the silicon oxide spacer 612 are masks, and the field oxide layer 610 and the substrate 600 are etched to form a trench 614 in the substrate 600. Then, the shape The oxide layer 608 fills the trench and covers the entire substrate 600 structure. Please refer to FIG. 6E to form an oxide plug 620 in the same manner as the conventional silicon trench shallow trench. Among them, the completed oxide plug 620 is partially formed by It consists of oxide layer 608 (Figure 6D) and part of field oxide layer 610 (Figure 6D). Then, doping of P well area 626, N well area 622, P + type area 624, and N + type area 628 is performed. The N + -type region 628 and P + -type region 624 are higher than the trench 6H (Figure 6D). These regions can be ion implanted with different masks to achieve the required concentration and depth under appropriate operating conditions. Figure 6E shows the surrounding conditions, so the number of oxidation plugs 620 is more than one. In particular, the depth of ion implantation can be controlled (please read the precautions on the back before filling in this (Page) 0—Order --------- line! The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the Chinese National Standard (CNS) A4 (210 X 297 mm) 4 7 3 4 §4 A7 _B7_ 5. The description of the invention (β) is within a small error range, which is about 0.05 microns. And here The depth of the P + -type region 624 and the N + -type region 628 is preferably about 500 to 2000 angstroms. In addition, the doping steps of these regions are not limited to this time. It may also be performed before and after other steps, which are both It can be easily accomplished by those skilled in the art. Figures 7A to 7E of the fifth embodiment illustrate a method for manufacturing a photodiode according to the present invention. Of course, it can also be said to be a method for manufacturing a shallow trench isolation structure. Referring to FIG. 7A, after a silicon nitride mask pattern 704 is formed on a substrate 700, a field oxide layer 7 1 0 is grown by a thermal oxidation method. Referring to FIG. 7B, a photoresist layer 706 is formed to cover the field oxide layer 7 1 0 and the silicon nitride mask pattern 704. Referring to FIG. 7C, the photoresist layer 706 is converted into a photoresist pattern 712 by a conventional lithography technique. Referring to FIG. 7D, with the photoresist pattern 712 as a mask, the field oxide layer 710 and the substrate 700 are etched to form a trench 714 in the substrate 700. The trench 714 is located below the field oxide layer 710 and is narrower than the field oxide layer 710. Next, the photoresist pattern 712 is removed. Thereafter, an oxide layer 708 is formed to fill the trench and cover the entire substrate 700 structure. Please refer to FIG. 7E. In the same way as the conventional shallow trench of silicon trench, the completed oxide plug 720 is composed of a part of the oxide layer 708 (Figure 7D) and a part of the field oxide layer 710 (Figure 7D) . After that, doping of regions such as the P-well region 727, the N-well region 722, the P + -type region 724, and the N + -type region 728 is performed. (Please read the notes on the back before filling in this page) 丨 ---- 丨 I — 丨 Order · -------- 1 _ Printed by the Employees' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs
I I I l· I I I- 1 I I ^ ! I j.r t I I I I I I I 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 734 tw^0^g^ A7 B7 五、發明說明（ϋ) 其中Ν+型區728與Ρ +型區724高於溝渠714(第7D圖）。 這些區域可利用離子植入法，配合不同罩幕而以適當的 操作條件達成所需的濃度與深度。第7Ε圖繪示的更包括 周邊的情形，因而其氧化插塞720的數目不止一個。 特別要說明的是，離子植入的深度控制是可以在很 小的誤差範圍內的，也就是約〇.〇5微米。而這裡的Ρ+型 區724與Ν +型區728的深度較佳約爲500至2000埃。 此外，這些區域的摻雜步驟並不限定於此時進行。 其亦可能於其他步驟的前後實施，這些皆是熟悉此技藝 者所能輕易完成。 由以上說明可以得知，本發明所製造的光二極體， 或者所建立的淺溝渠隔離結構至少具有特點如下： 1. 增加崩潰電壓。 2. 減少接合面的漏電流。 3. 減少光二極體的暗電流。 4. 增進光感應器的靈敏度。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾。因此本發明 之保護範圍當視後附之申請專利範圍所界定者爲準。 -------:''ίΓ! -------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）III l · II I- 1 II ^! I jr t IIIIIII This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 734 tw ^ 0 ^ g ^ A7 B7 V. Description of the Invention (i) Wherein, the N + -type region 728 and the P + -type region 724 are higher than the trench 714 (Figure 7D). These areas can be ion implanted to match the different masks to achieve the desired concentration and depth under appropriate operating conditions. Figure 7E shows the surrounding situation, so the number of oxidation plugs 720 is more than one. In particular, it should be noted that the depth control of ion implantation can be within a small error range, that is, about 0.05 micrometers. The depth of the P + -type region 724 and the N + -type region 728 here is preferably about 500 to 2000 angstroms. In addition, the doping steps in these regions are not limited to be performed at this time. It may also be implemented before and after other steps, which can be easily done by those skilled in the art. From the above description, it can be known that the photodiode manufactured by the present invention or the shallow trench isolation structure established has at least the following characteristics: 1. Increasing the breakdown voltage. 2. Reduce the leakage current on the joint surface. 3. Reduce the dark current of the photodiode. 4. Improve the sensitivity of the light sensor. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. -------: '' ίΓ! ------- Order --------- line (Please read the precautions on the back before filling out this page) This paper size applies to Chinese national standards (CNS) A4 size (210 X 297 mm)