CN110581107A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

Info

Publication number
CN110581107A
CN110581107A CN201910484072.0A CN201910484072A CN110581107A CN 110581107 A CN110581107 A CN 110581107A CN 201910484072 A CN201910484072 A CN 201910484072A CN 110581107 A CN110581107 A CN 110581107A
Authority
CN
China
Prior art keywords
semiconductor chip
substrate
conductive pattern
connection
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910484072.0A
Other languages
English (en)
Inventor
沈钟辅
金知晃
赵汊济
韩相旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110581107A publication Critical patent/CN110581107A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06137—Square or rectangular array with specially adapted redistribution layers [RDL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/2413—Connecting within a semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H01L2224/29191—The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一种半导体封装包括：下基板；连接基板，耦合到下基板，所述连接基板具有围绕空腔的横向部分以及横向部分的顶表面上的第一导电图案；下基板上的下半导体芯片，所述下半导体芯片位于连接基板的空腔中，所述下半导体芯片包括下半导体芯片的顶表面上的第二导电图案；接合构件，将第一导电图案和第二导电图案彼此连接；以及第一导电图案和第二导电图案上的顶部封装。

Description

半导体封装及其制造方法
相关申请的交叉引用
本申请要求于2018年6月8日在韩国知识产权局提交的题为“半导体封装及其制造方法”的韩国专利申请No.10-2018-0066049的优先权，该申请通过引用整体并入本文。
技术领域
本公开涉及一种半导体封装及其制造方法。
背景技术
半导体封装用以实现合格用于电子产品中的集成电路芯片。在一种类型的半导体封装中，半导体芯片安装在印刷电路板上，并且使用接合线或凸块将半导体芯片电连接到印刷电路板。随着近来电子工业的发展，半导体封装得以多样的开发以实现小尺寸、轻重量和/或低制造成本的目标。此外，许多种类的半导体封装还包括例如大容量存储器件。
发明内容
根据一些示例实施例，一种半导体封装可以包括：下基板；连接基板，耦合到下基板，所述连接基板具有围绕空腔的横向部分以及横向部分的顶表面上的第一导电图案；下基板上的下半导体芯片，所述下半导体芯片位于连接基板的空腔中，所述下半导体芯片包括下半导体芯片的顶表面上的第二导电图案；接合构件，将第一导电图案和第二导电图案彼此连接；以及第一导电图案和第二导电图案上的顶部封装。
根据一些示例实施例，一种半导体封装可以包括：连接基板，包括连接基板中的空腔以及连接基板的顶表面上的第一导电图案；半导体芯片，位于空腔中并且包括第二导电图案，所述半导体芯片具有其上设置有第二导电图案的非有源表面和面对非有源表面的有源表面；以及接合构件，将第一导电图案和第二导电图案彼此电连接。半导体芯片和第二导电图案可以彼此电绝缘。连接基板还可以包括穿透连接基板并连接到第一导电图案的过孔。
根据一些示例实施例，一种制造半导体封装的方法可以包括：提供下半导体芯片，所述下半导体芯片包括下半导体芯片的非有源表面上的第一导电图案；提供连接基板，所述连接基板包括连接基板中的空腔以及连接基板的顶表面上的第二导电图案；将下半导体芯片和连接基板设置在下基板上，以将下半导体芯片置于连接基板的空腔中；将第一导电图案和第二导电图案彼此接合；提供顶部封装，所述顶部封装包括顶部封装的底表面上的多个连接端子；以及将顶部封装安装在下半导体芯片和连接基板上，以将连接端子耦合到第一导电图案和第二导电图案。
附图说明
通过参考附图详细描述示例性实施例，特征对于本领域技术人员将变得清楚，在附图中：
图1示出了根据一些示例实施例的半导体封装的横截面图。
图2示出了第一导电图案、第二导电图案和接合构件的平面图。
图3至图5示出了根据一些示例实施例的半导体封装的横截面图。
图6至图12示出了根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
图13至图15示出了根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
图16至图23示出了根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
具体实施方式
下面参考附图描述根据示例实施例的半导体封装。图1示出了根据一些示例实施例的半导体封装的横截面图。
参考图1，可以提供底部封装P100。底部封装P100可以包括下基板100、连接基板200、下半导体芯片300和下模制构件400。
例如，下基板100可以是或可以包括在其顶表面上设置有信号图案的印刷电路板(PCB)。在另一示例中，下基板100可以具有电介质层和布线层的交替结构。
外部端子110可以设置在下基板100下方，例如，设置在下基板100背对下半导体芯片300的底表面上。外部端子110可以包括焊球或焊料凸块，并且基于外部端子110的类型，底部封装P100可以包括球栅阵列(BGA)类型、精细球栅阵列(FBGA)类型和接点栅格阵列(LGA)类型中的一种。
连接基板200可以设置在下基板100上。连接基板200可以安装在下基板100的顶表面上，例如，安装在与下基板100的底表面相对的表面上。例如，连接基板200可以通过焊料凸块或焊球安装在下基板100上。连接基板200可以通过下基板100电连接到外部端子110。在本说明书中，短语“电连接/耦合”可以包括“直接或间接电连接/耦合”。
连接基板200可以包括穿透连接基板200的开口OP，即空腔OP。例如，开口OP可以成形如开放孔，例如空腔，将连接基板200的底表面200b和顶表面200a相互连接。例如，如图1所示，开口OP可以穿过连接基板200的整个厚度，因此连接基板200的横向部分可以围绕开口OP，例如，用以提供容纳下面更详细说明的下半导体芯片300的空间。
连接基板200可以包括基层210和基层210中的导电构件220。例如，基层210可以包括氧化硅。导电构件220可以占据连接基板200的外侧(例如，外围侧)，并且开口OP可以占据连接基板200的内侧(例如，中心侧)。例如，如图1所示，开口OP可以穿过基层210的整个厚度，并且导电构件220可以位于基层210围绕开口OP的部分(例如，基层210围绕开口OP的横向部分)内和该部分的表面上。例如，连接基板200的基层210可以围绕开口OP的整个周边(图2)。导电构件220可以包括连接基板焊盘222，连接基板过孔224和第一导电图案226。
连接基板焊盘222可以设置在连接基板200的下部，例如，设置在连接基板200的底表面200b上。连接基板200可以通过设置在连接基板焊盘222上的焊球或焊料凸块电连接到下基板100。连接基板过孔224可以穿透基层210并且与连接基板焊盘222具有电连接。第一导电图案226可以设置在连接基板200的上部，例如，设置在连接基板200的顶表面200a上。第一导电图案226可以包括其上安装有下述顶部封装P200的第一焊盘CP1、耦合到连接基板过孔224的第二焊盘CP2、第一电线EL1和第一接合焊盘BP1。第一电线EL1、第一焊盘CP1、第二焊盘CP2和第一接合焊盘BP1可以构成电路。如图1所示，顶部封装P200也可以安装在第二焊盘CP2上。例如，底部封装P100可以被配置为使得第一焊盘CP1具有与第二焊盘CP2相同的功能。然而，本公开的示例实施例不限于此。
下半导体芯片300可以设置在下基板100上。如图1所示，下半导体芯片300可以位于连接基板200的开口OP中(例如，在开口OP内)。当在平面图中观察时，下半导体芯片300可以具有比开口OP的平面形状小的平面形状。例如，下半导体芯片300可以与开口OP的内侧壁间隔开，例如，连接基板200可以围绕下半导体芯片300的周边(图2)。
下半导体芯片300可以具有面对下基板100的底表面300b以及与底表面300b相对的顶表面300a。下半导体芯片300的底表面300b可以是有源表面，下半导体芯片300的顶表面300a可以是非有源表面。下半导体芯片300可以安装在下基板100的顶表面上。例如，下半导体芯片300可以是倒装接合到下基板100。下半导体芯片300可以具有第一电路EC1，第一电路EC1通过设置在下芯片焊盘305上的下芯片端子310(例如，焊球或焊料凸块)电连接到下基板100。焊剂340可以填充下半导体芯片300和下基板100之间的空间。下半导体芯片300可以是例如逻辑芯片或存储器芯片。逻辑芯片可以包括逻辑部分和存储器部分。存储器芯片可以是或可以包括例如动态随机存取存储器(DRAM)、NAND闪存、NOR闪存、相变随机存取存储器(PRAM)、电阻随机存取存储器(ReRAM)和磁阻随机存取存储器(MRAM)中的一种或多种。下半导体芯片300可以电连接到外部端子110。图1仅示出了一个下半导体芯片300，但是下半导体芯片300可以设置为多个。
下半导体芯片300在作为下半导体芯片300的非有源表面的顶表面300a上可以包括第二导电图案320。下半导体芯片300的顶表面300a可以位于与连接基板200的顶表面200a的高度相同的高度处，例如，顶表面300a和200a可以共面。第二导电图案320可以包括其上安装有顶部封装P200的第三焊盘CP3、第二电线EL2和第二接合焊盘BP2。第二电线EL2可以重新分布第三焊盘CP3和第二接合焊盘BP2之间的电连接。第二导电图案320可以与下半导体芯片300没有直接电连接，例如，下半导体芯片300和第二导电图案320可以经由非有源顶表面300a而彼此电绝缘。
例如，下半导体芯片300可以包括穿过其中的芯片过孔330。芯片过孔330可以从下半导体芯片300的顶表面300a朝向底表面300b延伸。芯片过孔330可以耦合到第三焊盘CP3之一。芯片过孔330还可以耦合到下基板100。在这种情况下，芯片过孔330可以将第二导电图案320电连接到下基板100。在该配置中，芯片过孔330可以不耦合到下半导体芯片300的第一电路EC1，或者可以与下半导体芯片300的第一电路EC1电绝缘，例如，下半导体芯片300的第一电路EC1和芯片过孔330可以延伸穿过下半导体芯片300的相对端。在另一示例中，与图1不同，下半导体芯片300可以不包括芯片过孔330。
可以提供接合构件BM。接合构件BM可以将连接基板200上的第一结合焊盘BP1和下半导体芯片300上的第二结合焊盘BP2彼此电连接。在一些示例实施例中，接合构件BM可以是或可以包括接合线。第二电线EL2和第三焊盘CP3可以通过第一接合焊盘BP1和第二接合焊盘BP2以及接合构件BM电连接到连接基板200和下基板100。
图2是用于说明图1所示的第一导电图案226、第二导电图案320和接合构件BM的平面图，其中部分地示出了下半导体芯片300和连接基板200。参考图2，连接基板200的第一焊盘CP1、第二焊盘CP2和第一接合焊盘BP1可以通过第一电线EL1彼此电连接。下半导体芯片300的第三焊盘CP3和第二接合焊盘BP2可以通过第二电线EL2彼此电连接。第一接合焊盘BP1和第二接合焊盘BP2可以通过接合构件BM彼此电连接。为了便于描述，图2随意地示出了焊盘CP1、CP2和CP3以及接合焊盘BP1和BP2的布置，但是本公开不限于此，例如，一个附加的第二焊盘CP2可以位于图2的右侧，与第一焊盘CP1相邻并通过第一电线EL1与第一焊盘CP1连接(如图1所示)。
再次参考图1，下模制构件400可设置在下基板100上。下模制构件400可以填充连接基板200和下半导体芯片300之间的空间。下模制构件400可以覆盖下半导体芯片300的顶表面300a和连接基板200的顶表面200a。下模制构件400可以覆盖第一电线EL1、第二电线EL2、第一接合焊盘BP1、第二接合焊盘BP2和接合构件BM。下模制构件400中可以具有第一凹陷RS1，第一凹陷RS1暴露连接基板200的第一焊盘CP1和第二焊盘CP2以及下半导体芯片300的第三焊盘CP3。下模制构件400可以包括聚合物材料，例如Ajinomoto堆积膜环氧基聚合物或热固性树脂。
在一些示例实施例中，下模制构件400可以暴露下半导体芯片300的顶表面300a。图3图示了示出根据一些示例实施例的半导体封装的横截面图。如图3所示，下模制构件400可以暴露下半导体芯片300的顶表面300a上的第二电线EL2和第三焊盘CP3。在这种情况下，下模制构件400可以掩埋接合构件BM和下半导体芯片300的第二接合焊盘BP2。
再次参考图1，可以在底部封装P100上设置顶部封装P200。顶部封装P200可以包括上基板500、上半导体芯片600、上模制构件700和连接端子510。
例如，上基板500可以是或可以包括在其顶表面上设置有信号图案的印刷电路板(PCB)。在另一示例中，上基板500可以具有电介质层和布线层的交替结构。上基板500的宽度可以大于下半导体芯片300的宽度W1，如图1所示。上基板500的宽度可以与下基板100的宽度相同或者小于下基板100的宽度，但是示例实施例不限于此。顶部封装P200的宽度(可以与上基板500的宽度相同)可以与连接基板200的宽度(可以与下基板100的宽度相同)相同。
上半导体芯片600可以设置在上基板500上。上半导体芯片600的宽度W2可以大于下半导体芯片300的宽度W1。当在平面图中观察时，上半导体芯片600可以与下半导体芯片300重叠并且还与连接基板200的一部分重叠，例如，上半导体芯片600可以与下半导体芯片300及下半导体芯片300周围的开口OP中的下模制构件400完全重叠。上半导体芯片600可以具有面对上基板500的底表面600b以及与底表面600b相对的顶表面600a。上半导体芯片600的顶表面600a可以是有源表面。上半导体芯片600可以安装在上基板500的顶表面上。例如，上半导体芯片600可以引线接合到上基板500。上半导体芯片600可以通过例如一根或多根接合线610电连接到上基板500。上半导体芯片600可以是例如逻辑芯片或存储器芯片。逻辑芯片可以包括逻辑部分和存储器部分。
上模制构件700可以设置在上基板500上。上模制构件700可以覆盖上基板500的顶表面和上半导体芯片600的顶表面600a。上模制构件700可以包括聚合物材料，例如Ajinomoto堆积膜环氧基聚合物或热固性树脂。
连接端子510可以设置在上基板500下方。连接端子510可以包括焊球或焊料凸块，并且基于连接端子510的类型，顶部封装P200可以包括球栅阵列(BGA)类型、精细球栅阵列(FBGA)类型和接点栅格阵列(LGA)类型中的一种。上半导体芯片600可以电连接到连接端子510。
连接端子510可以包括第一连接端子512和第二连接端子514。第一连接端子512可以设置在连接基板200上。第一连接端子512可以耦合到连接基板200的第一焊盘CP1。第二连接端子514可以设置在下半导体芯片300上。第二连接端子514可以耦合到下半导体芯片300的第三焊盘CP3。上半导体芯片600可以通过上基板500电连接到第一连接端子512和第二连接端子514。上半导体芯片600可以包括第二电路EC2，第二电路EC2通过第二连接端子514、第二导电图案320、接合构件BM和第一导电图案226电连接到外部端子110，并且上半导体芯片600还可以包括第三电路EC2，第三电路EC3通过第一连接端子512和第一导电图案226电连接到外部端子110。第二电路EC2和第三电路EC3可以与下半导体芯片300的第一电路EC1没有电连接或者电绝缘，例如，第一连接端子512可以与下半导体芯片300电绝缘。
图4和图5图示了示出根据一些示例实施例的半导体封装的横截面图。为了便于描述，省略或简化了对图4-5中与先前参考图1-3描述的附图标记相对应的元件的描述。
参考图4，可以提供接合构件BM。接合构件BM可以将第一接合焊盘BP1和第二接合焊盘BP2彼此电连接。在一些示例实施例中，接合构件BM可以是或可以包括第三导电图案410。第三导电图案410可以设置在下模制构件400的第二凹陷RS2中。第二凹陷RS2可以位于第一接合焊盘BP1和第二接合焊盘BP2之间。例如，在下模制构件400的第二凹陷RS2中，第三导电图案410可以具有从第一接合焊盘BP1延伸到第二接合焊盘BP2的形状。
参考图5，底部封装P100可以是扇出型面板级封装(FO-PLP)。例如，下基板100可以是再分布基板，即再分布层。下基板100可以包括例如电介质层102和导电层104。导电层104可以包括穿透电介质层102的一个或多个过孔。例如，电介质层102可以包括无机绝缘层，例如，氧化硅层或氮化硅层。在另一示例中，电介质层102可以包括聚合物材料。导电层104可以被电介质层102围绕或嵌入电介质层102中。导电层104可以重新分布下半导体芯片300的下芯片焊盘305和下基板100的外部端子110之间的电连接。底部封装P100可以通过下基板100具有扇出型结构。导电层104可以包括金属。导电层104可以连接到设置在下基板100的底表面上的基板焊盘106。钝化层108可以设置在下基板100的底表面上。钝化层108可以包括Ajinomoto堆积膜有机材料、无机材料或绝缘聚合物例如环氧基聚合物。外部端子110可以设置在下基板100的底表面上。外部端子110可以置于基板焊盘106上。外部端子110可以通过基板焊盘106电连接到导电层104。
下基板100可以直接接触连接基板200的底表面200b和下半导体芯片300的底表面300b。例如，下基板100可以与下半导体芯片300的下芯片焊盘305以及连接基板200的连接基板焊盘222直接接触。
在根据一些示例实施例的半导体封装中，导电图案226和320可以设置在连接基板200的顶表面200a和下半导体芯片300的顶表面300a上，并且顶部封装P200可以安装在导电图案226和320上。顶部封装P200的连接端子510可以全部设置在连接基板200和下半导体芯片300上。在这种情况下，连接端子510可以具有增大的面积用于其位置，结果，顶部封装P200可以增加处于底部封装P100上的输出端子(例如，连接端子510)的数量。导电图案226和320可以重新分布顶部封装P200的电路，这可以导致顶部封装P200和底部封装P100之间的布线自由度增加。因此，可以改善半导体封装的电特性。
此外，可以不需要附加的基板进行底部封装P100和顶部封装P200之间的再分布，因此，半导体封装的厚度可以减小。即使没有提供用于重新分布的基板，顶部封装P200也可以通过使用具有小厚度的导电图案226和320来重新分布其电连接。因此，半导体封装可以有利于尺寸缩减。
半导体封装总厚度的减小可以允许下半导体芯片300的厚度增加，因此，下半导体芯片300可以具有散热的优点。此外，从下半导体芯片300产生的热量可以通过导电图案226和320释放掉。结果，半导体封装可以增加散热和操作稳定性。
图6至图12示出了根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
参考图6，可以提供下半导体芯片300。下半导体芯片300可以具有彼此面对的底表面300b和顶表面300a。下半导体芯片300的底表面300b可以是有源表面，下半导体芯片300的顶表面300a可以是非有源表面。下半导体芯片300可以包括设置在其底表面300b上的下芯片焊盘305。下半导体芯片300可以包括穿过其中的芯片过孔330。芯片过孔330可以从下半导体芯片300的顶表面300a朝向底表面300b延伸。下芯片端子310可以附着到下芯片焊盘305。
参考图7，可以在下半导体芯片300的顶表面300a上形成第二导电图案320。例如，可以在下半导体芯片300的顶表面300a上形成导电层，然后可以图案化该导电层以形成第二导电图案320。在另一示例中，可以在下半导体芯片300的顶表面300a上形成阴影掩模(shadow mask)，然后可以以阴影掩模的图案沉积导电材料，这可以导致形成第二导电图案320。阴影掩模的图案可以部分地暴露下半导体芯片300的顶表面300a，并且可以限定形成第二导电图案320的区域。在形成第二导电图案320之后，可以去除阴影掩模。第二导电图案320可以包括第三焊盘CP3、第二电线EL2和第二接合焊盘BP2。
参考图8，可以将下半导体芯片300安装在下基板100上。下半导体芯片300可以以倒装接合方式安装。例如，可以在作为下半导体芯片300的非有源表面的底表面300b上涂覆焊剂340，然后可以定位下半导体芯片300使底表面300b上的下芯片端子310面对下基板100的顶表面。在该阶段，焊剂340可以突出到下半导体芯片300的侧向表面上。焊剂340可以包括树脂、活化剂和溶剂。溶剂可以包括例如二醇醚酯化合物、二醇醚化合物、酯化合物、酮化合物或环酯化合物。可以对下芯片端子310执行回流工艺，因此，下半导体芯片300可以安装在下基板100上。
参考图9，可以提供连接基板200。连接基板200可以包括基层210和基层210中的导电构件220。导电构件220可以包括连接基板焊盘222、连接基板过孔224和第一导电图案226。第一导电图案226可以包括第一焊盘CP1、第二焊盘CP2、第一电线EL1和第一接合焊盘BP1。例如，可以蚀刻基层210，然后可以在其内部填充导电材料以形成连接基板焊盘222、连接基板过孔224和第一导电图案226。
可以在连接基板200中形成开口OP(也称为空腔)。例如，可以去除连接基板200的一部分以形成穿透连接基板200的例如整个厚度的开口OP，例如，可以去除基层210的一部分以提供用于容纳下半导体芯片300的开口OP即空腔。开口OP可以例如通过蚀刻工艺如钻孔、激光烧蚀或激光切割形成。
可以将连接基板200安装在下基板100上。在该阶段，连接基板200可以设置为将下半导体芯片300置于开口OP中，例如，使连接基板200的一部分围绕开口OP中的下半导体芯片300。可以回流连接基板焊盘222上的焊球或焊料凸块以将连接基板200安装在下基板100上。
参考图10，可以形成接合构件BM。例如，连接基板200的第一接合焊盘BP1和下半导体芯片300的第二接合焊盘BP2可以以引线接合的方式彼此连接。在一些示例实施例中，可能期望连接基板200的顶表面200a与下半导体芯片300的顶表面300a处于同一高度，该配置可以容易地实现第一接合焊盘BP1和第二接合焊盘BP2之间的引线接合。
参考图11，可以在下基板100上形成下模制构件400。下模制构件400可以填充连接基板200和下半导体芯片300之间的空间。例如，可以将绝缘物质注入到连接基板200和下半导体芯片300之间的空间中，然后可以固化绝缘物质以形成下模制构件400。绝缘物质可以覆盖连接基板200的第一导电图案226、下半导体芯片300的第二导电图案320和接合构件BM。绝缘物质可以包括绝缘聚合物或热固性树脂。
例如，可以蚀刻下模制构件400以形成暴露第一焊盘CP1、第二焊盘CP2和第三焊盘CP3的第一凹陷RS1。在另一示例中，可以蚀刻下模制构件400以进一步暴露下半导体芯片300的顶表面300a。例如，下模制构件400可以暴露第一焊盘CP1、第二焊盘CP2、第三焊盘CP3以及位于下半导体芯片300的顶表面300a上的第二电线EL2。当下模制构件400形成为进一步暴露下半导体芯片300的顶表面300a时，可以制造图3的半导体封装。下面描述下模制构件400选择性地暴露第一焊盘CP1、第二焊盘CP2、第三焊盘CP3的示例。
参考图12，可以在下基板100的底表面上形成外部端子110。外部端子110可以包括焊球或焊料凸块。外部端子110可以通过下基板100、连接基板200的导电构件220和接合构件BM电连接到第一导电图案226和第二导电图案320。通过上述工艺可以形成底部封装P100。
再次参考图1，可以在底部封装P100上设置顶部封装P200。顶部封装P200可以包括上基板500、上半导体芯片600、上模制构件700和连接端子510。上基板500可以是或可以包括在其顶表面上设置有信号图案的印刷电路板(PCB)。上半导体芯片600可以安装在上基板500上。上模制构件700可以覆盖上基板500的顶表面和上半导体芯片600的顶表面600a。连接端子510可以设置在上基板500下方。连接端子510可以包括第一连接端子512和第二连接端子514。第二连接端子514可以比第一连接端子512更远离上基板500的边缘下方的位置。
底部封装P100和顶部封装P200可以彼此对准以将第一连接端子512置于第一导电图案226上并且将第二连接端子514置于第二导电图案320上。第一连接端子512和第二连接端子514可以分别与第一导电图案226和第二导电图案320接触，然后可以回流以将顶部封装P200安装在底部封装P100上。通过上述工艺，可以制造图1的半导体封装。
图13至图15图示了示出根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
参考图13，可以在如参考图1至9所述制造得到的结构上形成下模制构件400。下模制构件400可以填充连接基板200和下半导体芯片300之间的空间。例如，可以将绝缘物质注入到连接基板200和下半导体芯片300之间的空间中，然后可以固化绝缘物质以形成下模制构件400。下模制构件400可以覆盖第一导电图案226和第二导电图案320。
参考图14，可以蚀刻下模制构件400以形成第一凹陷RS1和第二凹陷RS2。第一凹陷RS1可以暴露第一焊盘CP1、第二焊盘CP2和第三焊盘CP3。当在平面图中观察时，第二凹陷RS2可以形成在连接基板200和下半导体芯片300之间，或者形成在连接基板200的第一接合焊盘BP1和下半导体芯片300的第二接合焊盘BP2之间。第二凹陷RS2可以暴露第一接合焊盘BP1和第二接合焊盘BP2各自的侧向表面。
参考图15，可以在第二凹陷RS2中形成第三导电图案410。可以通过用导电材料填充第二凹陷RS2来形成第三导电图案410。例如，可以执行电镀工艺以用导电材料填充第二凹陷RS2。在另一示例中，可以执行印刷工艺例如喷墨印刷，以用导电材料填充第二凹陷RS2。通过上述工艺可以形成底部封装P100。
之后，可以执行参考图1所述的工艺。例如，可以在底部封装P100上安装顶部封装P200以制造图4的半导体封装。
图16至图23示出了根据一些示例实施例的制造半导体封装的方法中一些阶段的横截面图。
参考图16，可以提供连接基板200。连接基板200可以包括基层210和基层210中的导电构件220。导电构件220可以包括连接基板焊盘222、连接基板过孔224和第一导电图案226。例如，可以蚀刻基层210，然后用导电材料填充蚀刻部分，以形成连接基板焊盘222、连接基板过孔224和第一导电图案226。
参考图17，可以在连接基板200中形成开口OP。可以去除连接基板200的一部分以形成穿透连接基板200的开口OP。开口OP可以例如通过蚀刻工艺如钻孔、激光烧蚀或激光切割形成。连接基板200的去除部分可以是在后续工艺中下半导体芯片300所设置到的区域。
连接基板200可以附着到载体基板800上。例如，载体基板800可以是绝缘基板(包括玻璃或聚合物)或导电基板(包括金属)。载体基板800的顶表面可以包括用于将载体基板800粘附到连接基板200的底表面200b的粘附构件。粘附构件可以包括例如胶带。
参考图18，可以在载体基板800上设置下半导体芯片300，例如，设置在连接基板200的开口OP内。下半导体芯片300可以与如参考图6和7所述制造的下半导体芯片300相同。下半导体芯片300可以设置在连接基板200的开口OP中。在该阶段，下半导体芯片300可以粘附到载体基板800。下半导体芯片300可以在其下部上包括下芯片焊盘305。例如，下半导体芯片300的底表面300b可以对应于与载体基板800接触的有源表面。
参考图19，可以形成接合构件BM。例如，连接基板200的第一接合焊盘BP1和下半导体芯片300的第二接合焊盘BP2可以以引线接合的方式彼此连接。
参考图20，可以在载体基板800上形成下模制构件400。下模制构件400可以填充连接基板200和下半导体芯片300之间的空间。例如，可以将绝缘物质注入到连接基板200和下半导体芯片300之间的空间中，然后可以固化绝缘物质以形成下模制构件400。下模制构件400可以覆盖连接基板200的第一导电图案226和下半导体芯片300的第二导电图案320。
参考图21，可以在连接基板200上设置支撑基板910。支撑基板910可以是例如绝缘基板如玻璃。可以使用胶层920将支撑基板910粘附到下模制构件400的顶表面。胶层920可以是例如树脂膜。
可以去除载体基板800。可以如虚线所示去除载体基板800，以暴露下半导体芯片300的底表面300b和连接基板200的底表面200b。可以通过施加剪切应力或通过化学处理粘附构件来去除载体基板800。
参考图22，可以在下半导体芯片300的底表面300b和连接基板200的底表面200b上形成下基板100。例如，可以在下半导体芯片300的底表面300b上和连接基板200的底表面200b上形成电介质层102、导电层104和基板焊盘106，从而可以制造下基板100。可以在下半导体芯片300的底表面300b上和连接基板200的底表面200b上形成电介质材料层(例如，氧化硅层)，然后图案化电介质材料层以形成电介质层102的一部分。下芯片焊盘305和连接基板焊盘222可以通过电介质层102暴露。可以在电介质层102的底表面上形成导电材料层，然后图案化导电材料层以形成导电层104和基板焊盘106。导电层104可以电连接到下半导体芯片300和连接基板200。可以在导电层104的底表面上形成电介质材料层，然后图案化电介质材料层以形成电介质层102的其他部分。在该阶段，基板焊盘106可以通过电介质层102暴露。
可以在暴露的基板焊盘106上形成外部端子110。外部端子110可以包括焊球或焊料凸块。
参考图23，可以去除支撑基板910。例如，可以通过施加剪切应力或通过化学处理胶层920来去除支撑基板910。可以如虚线所示去除支撑基板910，以暴露下模制构件400的顶表面。
可以蚀刻下模制构件400以形成暴露第一焊盘CP1、第二焊盘CP2和第三焊盘CP3的第一凹陷RS1。通过上述工艺可以制造底部封装P100。
之后，可以执行参考图1所述的工艺。例如，可以在底部封装P100上安装顶部封装P200以制造图5的半导体封装。
作为总结和回顾，一些示例实施例提供了具有改善电特性的半导体封装及其制造方法。一些示例实施例还提供了紧凑大小的半导体封装及其制造方法。一些示例实施例还提供了具有改善热稳定性的半导体封装及其制造方法。
也即，根据一些示例实施例的半导体封装可以被配置为使得顶部封装的连接端子可以全部设置在连接基板和下半导体芯片上。因此，导电图案可以重新分布顶部封装的电路，并且可以增加顶部封装和底部封装之间的布线自由度。
另外，因为不需要附加的基板进行底部封装和顶部封装之间的再分布，所以半导体封装的厚度可以减小。结果，半导体封装可以具有整体减小的大小。此外，半导体封装总厚度的减小可以允许下半导体芯片具有增加的厚度，因此下半导体芯片可以有利地散热。此外，从下半导体芯片产生的热量可以通过导电图案释放掉，从而增加散热。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是这些术语仅用于且应被解释为一般性、描述性含义，而不是为了限制的目的。在一些情况下，在提交本申请时本领域普通技术人员应清楚，结合特定实施例描述的特征、特性和/或元件可以单独使用或者与结合其它实施例描述的特征、特性和/或元件组合使用，除非另外具体指出。因此，本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (25)

1.一种半导体封装，包括：
下基板；
连接基板，耦合到所述下基板，所述连接基板包括：
围绕空腔的横向部分，和
所述横向部分的顶表面上的第一导电图案；
所述下基板上的下半导体芯片，所述下半导体芯片位于所述连接基板的所述空腔中，所述下半导体芯片包括所述下半导体芯片的顶表面上的第二导电图案；
接合构件，将所述第一导电图案和所述第二导电图案彼此连接；以及
所述第一导电图案和所述第二导电图案上的顶部封装。
2.根据权利要求1所述的半导体封装，其中，所述顶部封装包括：
上基板；
所述上基板上的上半导体芯片；以及
所述上基板的底表面上的连接端子。
3.根据权利要求2所述的半导体封装，其中，所述连接端子位于所述下半导体芯片上。
4.根据权利要求2所述的半导体封装，其中，所述连接端子包括：
第一连接端子，耦合到所述第一导电图案；以及
第二连接端子，耦合到所述第二导电图案。
5.根据权利要求4所述的半导体封装，其中，所述第二连接端子通过所述第二导电图案、所述接合构件和所述连接基板电耦合到所述下基板。
6.根据权利要求2所述的半导体封装，其中，所述连接端子与所述下半导体芯片电绝缘。
7.根据权利要求2所述的半导体封装，其中，所述上半导体芯片的宽度大于所述下半导体芯片的宽度。
8.根据权利要求1所述的半导体封装，其中，所述下半导体芯片的所述顶表面是非有源表面。
9.根据权利要求1所述的半导体封装，其中，所述连接基板的所述横向部分的所述顶表面和所述下半导体芯片的所述顶表面位于相同的高度。
10.根据权利要求1所述的半导体封装，其中，所述接合构件包括：
接合线；或者
所述第一导电图案和所述第二导电图案之间的第三导电图案。
11.根据权利要求1所述的半导体封装，还包括下模制构件，所述下模制构件在所述下基板上掩埋所述下半导体芯片和所述连接基板，
其中所述下模制构件暴露所述第一导电图案和所述第二导电图案。
12.根据权利要求1所述的半导体封装，其中，所述下半导体芯片还包括过孔，所述过孔穿透所述下半导体芯片并将所述第二导电图案电连接到所述下基板。
13.根据权利要求1所述的半导体封装，其中，所述下基板包括再分布层，所述再分布层直接耦合到所述下半导体芯片的下芯片焊盘和所述连接基板的基板焊盘。
14.一种半导体封装，包括：
连接基板，包括：
围绕空腔的横向部分，
所述横向部分的顶表面上的第一导电图案，和
穿过所述横向部分并连接到所述第一导电图案的过孔；
所述空腔内的半导体芯片，包括：
所述半导体芯片的非有源表面上的第二导电图案，所述半导体芯片和所述第二导电图案彼此电绝缘，和
面对所述非有源表面的有源表面；以及
接合构件，将所述第一导电图案和所述第二导电图案彼此电连接。
15.根据权利要求14所述的半导体封装，其中，所述连接基板的所述横向部分的所述顶表面和所述半导体芯片的所述非有源表面彼此共面。
16.根据权利要求14所述的半导体封装，还包括顶部封装，所述顶部封装耦合到所述第一导电图案和所述第二导电图案。
17.根据权利要求16所述的半导体封装，其中，所述顶部封装包括在所述顶部封装下方的第一连接端子和第二连接端子，
其中所述第一连接端子耦合到所述第一导电图案，以及
其中所述第二连接端子耦合到所述第二导电图案。
18.根据权利要求16所述的半导体封装，其中，所述顶部封装的宽度与所述连接基板的宽度相同。
19.根据权利要求16所述的半导体封装，还包括在所述连接基板下方的附加基板，
其中所述连接基板和所述半导体芯片耦合到所述附加基板，以及
其中所述半导体芯片的所述有源表面面对所述附加基板。
20.根据权利要求19所述的半导体封装，其中，所述半导体芯片还包括穿过所述半导体芯片的芯片过孔，所述芯片过孔将所述第二导电图案电连接到所述附加基板。
21.根据权利要求14所述的半导体封装，还包括：模制构件，覆盖所述连接基板的所述横向部分的所述顶表面和所述半导体芯片的所述非有源表面，所述模制构件暴露所述第一导电图案和所述第二导电图案。
22.一种制造半导体封装的方法，所述方法包括：
提供下半导体芯片，所述下半导体芯片包括所述下半导体芯片的非有源表面上的第一导电图案；
提供连接基板，所述连接基板包括所述连接基板中的空腔和所述连接基板的顶表面上的第二导电图案；
将所述下半导体芯片和所述连接基板设置在下基板上，以将所述下半导体芯片置于所述连接基板的所述空腔中；
将所述第一导电图案和所述第二导电图案彼此接合；
提供顶部封装，所述顶部封装包括所述顶部封装的底表面上的多个连接端子；以及
将所述顶部封装安装在所述下半导体芯片和所述连接基板上，以将所述多个连接端子耦合到所述第一导电图案和所述第二导电图案。
23.根据权利要求22所述的方法，其中，提供所述下半导体芯片包括：
在所述下半导体芯片的所述非有源表面上设置导电层；以及
图案化所述导电层。
24.根据权利要求22所述的方法，其中，将所述第一导电图案和所述第二导电图案接合包括：
形成模制构件以覆盖所述连接基板和所述下半导体芯片；
对所述模制构件执行蚀刻工艺以形成暴露所述第一导电图案和所述第二导电图案的第一凹陷；以及
将所述第一导电图案和所述第二导电图案彼此引线接合。
25.根据权利要求22所述的方法，其中，将所述第一导电图案和所述第二导电图案接合包括：
形成模制构件以覆盖所述连接基板和所述下半导体芯片；
图案化所述模制构件以形成第二凹陷，同时暴露所述第一导电图案和所述第二导电图案；以及
用导电材料填充所述第二凹陷以形成第三导电图案。
CN201910484072.0A 2018-06-08 2019-06-04 半导体封装及其制造方法 Pending CN110581107A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020180066049A KR102586794B1 (ko) 2018-06-08 2018-06-08 반도체 패키지 및 그 제조 방법
KR10-2018-0066049 2018-06-08

Publications (1)

Publication Number Publication Date
CN110581107A true CN110581107A (zh) 2019-12-17

Family

ID=68765263

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910484072.0A Pending CN110581107A (zh) 2018-06-08 2019-06-04 半导体封装及其制造方法

Country Status (3)

Country Link
US (1) US10978431B2 (zh)
KR (1) KR102586794B1 (zh)
CN (1) CN110581107A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102540829B1 (ko) * 2018-10-05 2023-06-08 삼성전자주식회사 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
DE102019121012A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Verkapseltes Package mit Träger, Laminatkörper und dazwischenliegender Komponente
KR20220146073A (ko) * 2021-04-23 2022-11-01 주성엔지니어링(주) 반도체 패키징 장치
KR20220167637A (ko) * 2021-06-14 2022-12-21 삼성전자주식회사 반도체 패키지

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7894203B2 (en) 2003-02-26 2011-02-22 Ibiden Co., Ltd. Multilayer printed wiring board
TWI335652B (en) * 2007-04-04 2011-01-01 Unimicron Technology Corp Stacked packing module
US8188379B2 (en) * 2008-07-04 2012-05-29 Unimicron Technology Corp. Package substrate structure
TWI373109B (en) * 2008-08-06 2012-09-21 Unimicron Technology Corp Package structure
US8471376B1 (en) 2009-05-06 2013-06-25 Marvell International Ltd. Integrated circuit packaging configurations
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
KR101695846B1 (ko) 2010-03-02 2017-01-16 삼성전자 주식회사 적층형 반도체 패키지
US8901435B2 (en) * 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
US9704780B2 (en) 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US9685414B2 (en) * 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
US9831214B2 (en) 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
KR20160012424A (ko) * 2014-07-24 2016-02-03 삼성전기주식회사 전자부품 내장 인쇄회로기판
US9543277B1 (en) 2015-08-20 2017-01-10 Invensas Corporation Wafer level packages with mechanically decoupled fan-in and fan-out areas
KR102595276B1 (ko) * 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
KR102059403B1 (ko) * 2016-10-04 2019-12-26 삼성전자주식회사 팬-아웃 반도체 패키지
US10347598B2 (en) * 2017-05-19 2019-07-09 Samsung Electro-Mechanics Co., Ltd. Composite antenna substrate and semiconductor package module
KR102073956B1 (ko) * 2017-11-29 2020-02-05 삼성전자주식회사 팬-아웃 반도체 패키지
US10347586B2 (en) * 2017-11-30 2019-07-09 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package

Also Published As

Publication number Publication date
KR102586794B1 (ko) 2023-10-12
US10978431B2 (en) 2021-04-13
US20190378825A1 (en) 2019-12-12
KR20190139491A (ko) 2019-12-18

Similar Documents

Publication Publication Date Title
KR102491103B1 (ko) 반도체 패키지 및 그 제조방법
TWI628778B (zh) 半導體封裝結構及其形成方法
US9947641B2 (en) Wire bond support structure and microelectronic package including wire bonds therefrom
US9165878B2 (en) Semiconductor packages and methods of packaging semiconductor devices
US7339278B2 (en) Cavity chip package
KR100511728B1 (ko) 복수의 반도체 칩을 고밀도로 실장할 수 있는 소형 반도체장치 및 그의 제조 방법
US9129870B2 (en) Package structure having embedded electronic component
KR20190091751A (ko) 반도체 패키지
CN110581107A (zh) 半导体封装及其制造方法
JP2011101044A (ja) スタックパッケージ及びその製造方法
JP2002252303A (ja) 成型チップ・スケール・パッケージにおけるフリップ・チップ半導体装置および組み立て方法
US11600545B2 (en) Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package
US20240006325A1 (en) Method of fabricating a semiconductor package
US11600564B2 (en) Redistribution substrate, method of fabricating the same, and semiconductor package including the same
CN112992872A (zh) 半导体封装件
US20080258288A1 (en) Semiconductor device stack package, electronic apparatus including the same, and method of manufacturing the same
US20220319973A1 (en) Semiconductor package including an interposer and method of fabricating the same
US20230054984A1 (en) Semiconductor package
US20200075561A1 (en) Semiconductor package
US11854989B2 (en) Semiconductor package substrate and semiconductor package including the same
US11764188B2 (en) Electronic package and manufacturing method thereof
KR100836642B1 (ko) 전자 패키지 및 그 제조방법
CN106469706B (zh) 电子封装件及其制法
US20240136272A1 (en) Semiconductor packages
US20230131730A1 (en) Package substrate and semiconductor package including the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination