TWI628778B - 半導體封裝結構及其形成方法 - Google Patents

半導體封裝結構及其形成方法 Download PDF

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TWI628778B
TWI628778B TW105124055A TW105124055A TWI628778B TW I628778 B TWI628778 B TW I628778B TW 105124055 A TW105124055 A TW 105124055A TW 105124055 A TW105124055 A TW 105124055A TW I628778 B TWI628778 B TW I628778B
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electronic component
conductive
substrate
semiconductor package
package structure
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TW105124055A
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TW201714275A (zh
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林子閎
蕭景文
彭逸軒
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體封裝結構及其形成方法。該半導體封裝結構包括：一第一電子元件，位於一基底上。該半導體封裝結構也包括：一第二電子元件，堆疊在該第一電子元件上。該第一電子元件之主動面朝向該第二電子元件之主動面。該半導體封裝結構進一步包括：一成型材料，位於該第一電子元件上並且圍繞該第二電子元件。另外，該半導體封裝結構包括：一第三電子元件，堆疊在該第二電子元件及該成型材料上。

Description

半導體封裝結構及其形成方法
本發明涉及半導體封裝結構，特別係涉及一種3D(三維)SIP(System-In-Package，系統級封裝)半導體封裝結構及其形成方法。
為了確保電子產品及通訊設備(諸如穿戴式設備)之微型化及多功能性，期望一種小尺寸的、支持多引腳連接的、高速運行的和提供高功能性的半導體封裝。習知的半導體封裝一般將主動設備及被動設備放置在PCB(Printed Circuit Board，印刷電路板)上。但是，需要大小相當的PCB來提供區域給安裝於其上的主動設備及被動設備。因此，難以降低半導體封裝的尺寸以及難以降低由該半導體封裝形成的電子產品的尺寸。
如此，期望一種創新的半導體封裝結構及其形成方法。
因此，本發明之主要目的即在於提供一種半導體封裝結構及其形成方法，可以減少半導體封裝結構之尺寸。
根據本發明至少一個實施例之一種半導體封裝結構，包括：一第一電子元件，設置於一基底上；一第二電子元 件，堆疊在該第一電子元件上，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；一成型材料，設置於該第一電子元件上並且圍繞該第二電子元件。
根據本發明至少一個實施例之一種半導體封裝結構，包括：一第一電子元件，設置於一基底上；一介電層，設置於該基底上並且圍繞該第一電子元件；一第二電子元件，堆疊於該第一電子元件上，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；一成型材料，設置在該介電層上並且圍繞該第二電子元件；以及一第一導電層，設置在該成型材料上。
根據本發明至少一個實施例之一種形成半導體封裝結構的方法，包括：於一基底上提供一第一電子元件；於該基底上形成一介電層以圍繞該第一電子元件；於該第一電子元件上堆疊一第二電子元件，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；於該介電層上形成一成型材料以圍繞該第二電子元件；以及於該成型材料上形成一第一導電層。
本發明實施例將複數個電子元件(如第一、第二電子元件)整合至一個半導體封裝中，因此可以降低半導體封裝結構之尺寸。另外，第一電子元件之主動面係朝向第二電子元件之主動面，因此可縮短第一電子元件和第二電子元件之間之信號傳輸路徑。
100‧‧‧基底
110‧‧‧絕緣材料層(絕緣層)
120、220、280‧‧‧阻焊層(防焊掩模層)
240、290、310‧‧‧導電結構
130‧‧‧導電層
140‧‧‧通孔
150、180、200‧‧‧介電層
160‧‧‧第一電子元件
170‧‧‧黏合層
160a、250a、300a‧‧‧導電墊
190、210、270‧‧‧導電層
230‧‧‧導電柱
250‧‧‧第二電子元件
260‧‧‧成型材料
300‧‧‧第三電子元件
通過閱讀接下來的詳細描述以及參考所附圖式所做之示例，可以更全面地理解本發明，其中：第1A~1F圖係用於說明根據本發明一些實施例的形成半導體封裝結構的方法中的各個階段的剖面示意圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
以下描述為實現本發明的一種預期模式。該描述是出於說明本發明的一般原理的目的，而不應被視為限制。本發明的範圍係參考所附的申請專利範圍而確定。
本發明將參考特定的實施例和確定的圖式來描述，但是本發明不限制於此，並且本發明僅由申請專利範圍來限制。描述的圖式僅是原理圖並且不是限制。在圖式中，出於說明目的而誇大了某些元件的尺寸，並且這些元件的尺寸並非按比例繪制。這些元件的尺寸及相對尺寸不對應本發明實踐中 的真實尺寸。
第1A~1F圖係用於說明根據本明一些實施例的半導體封裝結構的形成方法中的各階段的剖面示意圖。在第1A~1F圖中所描述的各階段之前、期間或之後，可以提供額外的操作。對於不同的實施例，描述的該些階段中的一部分可以被取代或者省略。額外的特徵(如結構)可以添加至該半導體封裝結構中。對於不同實施例，以下描述的該些特征(如結構)中的一部分可以被取代或者省略。為了簡化圖形，第1A~1F圖僅描繪了半導體封裝結構的一部分。
如第1A圖所示，提供了一基底100。在一些實施例中，該基底100為一CCL(Copper Clad Laminate，覆銅箔層壓板)或者另一合適的基底。在一些實施例中，基底100為一面板(panel)或者一晶圓。在一些實施例中，基底100可以包括一絕緣材料層(絕緣層)110、一阻焊層(防焊掩模層)120、一導電層130和一通孔140。需要注意的是，圖式中所示基底100的組態僅為示例而不是對本發明的限制。基底100可以為單層或者包括複數層(即，兩層或者多於兩層)。
絕緣材料層110可以是單個絕緣層或者包括複數個絕緣層。為了簡化圖形，此中僅描繪了單個絕緣層作為示例。在一些實施例中，該絕緣材料層110包括：一有機材料，該有機材料包括：PP(polypropylene，聚丙烯)加玻璃纖維、環氧樹脂(epoxy resin)、聚醯亞胺(polyimide)、氰酸酯(cyanate ester)、另一合適的材料或者他們的組合。
在絕緣層110的頂面和底面上均設置了阻焊層120 和導電層130。阻焊層120和導電層130一起完全覆蓋絕緣層110的頂面和底面。絕緣層110的頂面和底面上的導電層130係經由絕緣層110中的通孔140而彼此電性連接。在一些實施例中，導電層130和通孔140包括：銅或者另一合適的導電材料。
接著，在基底100上形成一介電層150。該介電層150覆蓋絕緣層110頂面上的阻焊層120及導電層130。在一些實施例中，通過沉積(deposition)製程來形成介電層150，諸如涂覆(coating)製程、物理氣相沉積製程、化學氣相沉積製程或者另一合適的製程。
接著，在基底100上接合一個或更多的電子元件。例如，第一電子元件160通過黏合層(adhesive layer)170來貼附至介電層150。在一些實施例中，每個第一電子元件160包括：在其正面或者主動面的一個或更多的導電墊160a。導電墊160a背向基底100、介電層150和黏合層170。
在一些實施例中，第一電子元件160包括：一個或複數個主動元件，及/或，一個或複數個被動元件。主動元件可以為整合的電路晶片/晶粒(chip/die)或者另一合適的主動元件。例如，第一電子元件160可以為記憶體晶粒、邏輯晶粒或者另一合適的主動電子元件，其中邏輯晶粒包括：CPU(Central Processing Unit，中央處理單元)、GPU(Graphics Processing Unit，圖形處理單元)或DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)控制器。可選地，第一電子元件160可以為整合的被動設備(Integrated Passive Device，IPD)、電容、電阻、電感、變容二極體或者另一合適的被動元件。
複數個第一電子元件160之間可以具有相同或不同的功能。複數個第一電子元件160之間可以具有相同或不同的尺寸。第一電子元件160的實際數目、功能和尺寸由設計要求決定並且不受限制。
如第1B圖所示，在基底100上形成一介電層180。該介電層180覆蓋並且圍繞第一電子元件160和黏合層170。在一些實施例中，介電層180通過沉積製程形成，諸如凃覆製程、物理氣相沉積製程、化學氣相沉積製程或者另一合適的製程。
接著，在介電層180和介電層150中形成複數個開口。部分開口穿透介電層180和介電層150以露出基底100中一部分的導電層130。部分開口在介電層180中延伸以露出第一電子元件160中的導電接墊160a。在一些實施例中，通過鐳射鉆孔(laser drilling)製程、蝕刻製程或者另一適合的製程來在介電層180和介電層150中形成該等開口。
接著，在介電層180上形成一導電層190，並且該導電層190延伸至該介電層180和介電層150中的開口的底部和側壁。如此，如第1B圖所示，從剖面視圖的視角來看時，導電層190為彎曲的。在一些實施例中，一部分的導電層190的底面與另一部分的導電層190的底面非共平面。在一些實施例中，一部分的導電層190(位於介電層180內的開口中)的底面位於第一電子元件160的上方，同時另一部分的導電層 190(位於介電層180和150內的另一開口中)的底面位於第一電子元件160的下方。導電層190穿過介電層180和介電層150中的開口而電性連接至基底100中的導電層130和導電墊160a。在一些實施例中，導電層190係通過電鍍製程或者另一合適的製程形成。
如第1C圖所示，於導電層190上形成一介電層200。該導電層190及該介電層200一起完整地填滿介電層180和介電層150中的開口。介電層200進一步在介電層180上的導電層190上延伸。在一些實施例中，介電層200係通過沉積製程形成，諸如凃覆製程、物理氣相沉積製程、化學氣相沉積製程或者另一合適的製程。介電層200和介電層180可以包括相同或不同的材料。
接著，在介電層200中形成複數個開口以露出介電層180上的一部分導電層190。在一些實施例中，通過鐳射鉆孔製程、蝕刻製程或者另一合適的製程在介電層200中形成上述開口。
接著，於介電層200中形成圖案化的導電層210並且該圖案化的導電層210填滿該介電層200中的開口。導電層210經由介電層200中的開口而電性連接至該導電層190。在一些實施例中，通過電鍍製程或者另一合適的製程來形成該導電層210。
接著，於介電層200上形成一防焊掩模層220(或者介電層)並且該防焊掩模層220覆蓋該導電層210。在一些實施例中，該防焊掩模層220具有平坦的頂面。在一些實施例 中，通過沉積製程形成該防焊掩模層220，諸如凃覆製程、物理氣相沉積製程、化學氣相沉積製程或者另一合適的製程。
如第1D圖所示，於防焊掩模層220中形成複數個開口以露出一部分的導電層210。在一些實施例中，通過鐳射鉆孔製程、蝕刻製程或者另一合適的製程在防焊掩模層220中形成該等開口。
接著，於導電層210上形成一個或更多的導電柱230。導電柱230可以被稱為TIV(Through Interposer Vias，通過中介層通孔)。導電柱230通過防焊掩模層220中的開口來電性及物理地連接至某些已露出的一部分的導電層210。在一些實施例中，導電柱230與第一電子元件160垂直重疊，此處的垂直重疊係指於俯視方向上，導電柱230與第一電子元件160重疊。在其他一些實施例中，導電柱230不與第一電子元件160垂直重疊。在一些實施例中，導電柱230包括：銅、另一合適的導電材料或者他們的組合。在一些實施例中，通過電鍍製程或者另一合適的製程來形成導電柱230。
接著，提供一個或更多的第二電子元件250。在一些實施例中，第二電子元件250包括：一個或複數個主動元件、和/或、一個或複數個被動元件。例如，第二電子元件250可以是記憶體晶粒、邏輯晶粒或者另一合適的主動電子元件，其中邏輯晶粒包括：CPU、GPU、或者DRAM控制器。可選地，第二電子元件250可以是IPD、電容、電阻、電感、變容二極體或者另一合適的被動元件。
複數個第二電子元件250可以具有相同或不同的 功能。複數個第二電子元件250可以具有相同或不同的尺寸。第二電子元件250的數目、功能和尺寸由設計要求決定並且不受限制。
在一些實施例中，每個第二電子元件250可以包括：在其正面或主動面的一個或更多的導電墊250a。導電墊250a可以連接至導電結構240。在一些實施例中，導電結構240為導電凸塊、導電柱、導電膠(conductive paste)結構或者另一合適的導電結構。導電結構240可以包括：銅、焊錫、或者另一合適的導電材料。
接著，翻轉第二電子元件250並經由導電結構240耦接至某些已露出的一部分導電層210。執行合適的製程(例如回流製程)以接合第二電子元件250。如此，導電墊250a(連接至導電結構240)面向基底100和第一電子元件160的導電墊160a。換言之，第二電子元件250和第一電子元件160係面對面連接。
如第1D圖所示，第二電子元件250堆疊於第一電子元件160上。在一些實施例中，第二電子元件250與第一電子元件160垂直重疊，此處的垂直重疊係指於俯視方向上，第二電子元件250與第一電子元件160重疊。在其他一些實施例中，第二電子元件250與第一電子元件160不垂直重疊。第二電子元件250和第一電子元件160可以具有相同或不同的功能。第二電子元件250和第一電子元件160可以具相同或不同的尺寸。第二電子元件250和第一電子元件160的數目、功能和尺寸由設計要求決定，並且不受限制。
第二電子元件250和導電柱230係並排設置。在一些實施例中，複數個導電柱230位於第二電子元件250的兩相對側。也就是說，一個或更多的第二電子元件250設置在複數個導電柱230之間。在其他一些實施例中，一個或更多的導電柱230可以設置在複數個第二電子元件250之間。在一些實施例中，從俯視的視角來看，複數個導電柱230位於第二電子元件250周圍，並且一同圍繞第二電子元件250。
在一些實施例中，第二電子元件250的厚度小於導電柱230的厚度或高度。在一些實施例中，導電柱230高於第二電子元件250。在其他一些實施例中，導電柱230的頂面與第二電子元件250的頂面大致上共平面。
如第1E圖所示，在防焊掩模層220上形成一成型材料(molding compound)260。該成型材料260圍繞導電柱230、導電結構240和第二電子元件250。導電柱230和導電結構240的部分底部係嵌入於防焊掩模層220中，並且沒有覆上成型材料260。在一些實施例中，第二電子元件250浸入成型材料260中。在一些實施例中，介電層150、180和200以及防焊掩模層220係位於成型材料260和基底100之間。
在一些實施例中，成型材料260可以由非導電材料形成，諸如環氧樹脂、樹脂、可塑聚合物或者另一合適的成型材料。在一些實施例，成型材料260在大致上為液體時應用，接著經由化學反應固化。在其他一些實施例中，成型材料260為UV(ultraviolet，紫外)或者熱固化的聚合物，該聚合物作為凝膠或者可塑固體來應用，然後通過UV或熱固化製程來固 化。該成型材料260可以按照模型來固化。
在一些實施例中，沉積的成型材料260覆蓋第二電子元件250和導電柱230的頂面。接著，執行研磨製程以使沉積的成型材料260變薄。如此，變薄的成型材料260露出導電柱230的頂面。在一些實施例中，成型材料260的頂面大致上與導電柱230的頂面共平面。在一些實施例中，成型材料260露出導電柱230的頂面但是覆蓋第二電子元件250的頂面。在其他一些實施例中，第二電子元件250的頂面可以從成型材料260中露出。在一些實施例中，導電柱230穿透成型材料260並且從成型材料260的表面伸出。
接著，於成型材料260上形成一圖案化的導電層270並且該圖案化的導電層270耦接至從成型材料260中露出的導電柱230。部分的導電層270與第二電子元件250垂直重疊，此處的垂直重疊係指於俯視方向上，該部分的導電層270與第二電子元件250重疊；以及通過成型材料260的頂部而與第二電子元件250隔離。換言之，一部分的成型材料260夾在導電層270和第二電子元件250之間。另一部分的導電層270不與第二電子元件250垂直重疊。在一些實施例中，通過電鍍製程或者另一合適的製程來形成該導電層270。在其他一些實施例中，導電層270可以由RDL(Redistribution Layer，重分佈層)結構取代，該RDL結構包括：一個或更多的導電線路，設置在一個或更多的IMD(Inter-Metal Dielectric，金屬間介電)層中。
接著，於成型材料260上形成一防焊掩模層280， 並且該防焊掩模層280覆蓋該導電層270。在一些實施例中，通過沉積製程來形成該防焊掩模層280。
如第1F圖所示，在防焊掩模層280中形成複數個開口以露出一部分的導電層270。在一些實施例中，通過鐳射鉆孔製程、蝕刻製程或者另一合適的製程來於防焊掩模層280中形成該等開口。
接著，提供一第三電子元件300。在一些實施例中，該第三電子元件300包括：主動元件或被動元件。例如，第三電子元件300可以是記憶體晶粒、邏輯晶粒或者另一合適的主動電子元件，其中邏輯晶粒包括：CPU、GPU、或者DRAM控制器。可選地，第三電子元件300可以是IPD、電容、電阻、電感、變容二極體或者另一合適的被動元件。
在一些實施例中，第三電子元件300可包括：在其正面或主動面的一個或更多的導電墊300a。導電墊300a可以連接至導電結構290。在一些實施例中，導電結構290可以為導電凸塊、導電柱、導電膠結構或者另一合適的導電結構。導電結構290可以包括：銅、焊錫、或者另一合適的導電材料。
接著，翻轉第三電子元件300並將其經由導電結構290耦接至某些已露出的一部分的導電層270。執行合適的製程(例如回流製程)以接合第三電子元件300。如此，導電墊300a(連接至導電結構290)面向基底100和第一電子元件160的導電墊160a。在一些實施例中，導電柱230設置在介電層180和第三電子元件300之間。在其他一些實施例中，於第三電子元件300和防焊掩模層280中形成一底部填充材料以圍繞 導電結構290。
接著，於基底100的下方形成一導電結構310。例如，導電結構310接合至絕緣層110的底面，該底面背向該第一電子元件160、第二電子元件250及第三電子元件300。相應地，導電結構310及第一電子元件160係位於基底100的兩相對側。
導電結構310耦接至基底100底面上的導電層130。導電結構310經由基底100的導電層130和通孔140而電性連接至該第一電子元件160。導電結構310經由基底100的導電層130和通孔140、導電層190、導電層210和導電結構240而電性連接至第二電子元件250。導電結構310經由基底100的導電層130和通孔140、導電層190、導電層210、導電柱230，導電層270和導電結構290而電性連接至第三電子元件300。
在一些實施例，導電結構310可以為導電凸塊、導電柱、導電膠結構或者另一合適的導電結構。導電結構310可以包括：銅、焊錫或者另一合適的導電材料。在一些實施例中，導電結構310的尺寸可以大於導電結構240和290的尺寸。
根據本發明的一些實施例，基底100可以為面板或者晶圓。對具有複數個電子元件160、250和300的基底100執行一切割(singulation)製程。例如，將基底150、180和200，防焊掩模層220，成型材料260和防焊掩模層280切為小方塊。如此，通過晶圓製程或者面板製程來形成含有複數個電子元件160、250和300的複數個封裝，使得製造成本降低。 因此，提供了一種創新的3D SIP半導體封裝結構。在一些實施例中，基底100可以為比晶圓具有更多可使用面積的面板，以及由面板來製造複數個SIP半導體封裝結構以便於進一步降低製造成本。
如第1F圖所示，第三電子元件300堆疊在第二電子元件250和第一電子元件160之上。第二電子元件250位於第三電子元件300和第一電子元件160之間。在一些實施例中，第三電子元件300與第一電子元件160垂直重疊。在一些實施例中，第三電子元件300與第二電子元件250垂直重疊。在其他一些實施例中，第三電子元件300不與第一電子元件160和/或第二電子元件250垂直重疊。
本發明實施例不限制於此。在一些實施例中，存在複數個第三電子元件300垂直堆疊在第二電子元件250和第一電子元件160上。第三電子元件300、第二電子元件250和第一電子元件160可以具有相同或不同的功能。第三電子元件300、第二電子元件250和第一電子元件160可以具有相同或不同的尺寸。第三電子元件300、第二電子元件250以及第一電子元件160的數目、功能和尺寸均是由設計要求決定，並且不受限制。
可以對本發明的實施例做出各種變形和/或修改。在一些實施例中，SIP半導體封裝結構為含有複數個堆疊的電子元件160和250的半導體封裝。接著，另一封裝可以垂直地堆疊在含有電子元件160和250的半導體封裝之上，以形成POP(Package-On-Package，封裝上封裝)半導體封裝結構。 例如，第1F圖所示的第三電子元件300可以被合適的封裝所取代。該封裝可以經由導電結構290而接合至導電層270。
根據本發明一些實施例的半導體封裝結構及其形成方法具有許多優點。該半導體封裝結構包括：至少兩個垂直堆疊的電子元件。具有不同功能的複數個電子元件(如晶片、被動元件或IPD)可以整合至單個半導體封裝結構中。由不同技術節點製造的電子元件也可以整合在一起。相應地，半導體封裝結構可以異質(heterogeneous)整合。另外，半導體封裝結構的尺寸(尤其是橫向尺寸)可以顯著地降低。半導體封裝結構的設備密度或者I/O(Input/Output，輸入/輸出)引腳數目也增加。因此，根據本發明一些實施例的半導體封裝結構及其形成方法可以提供小型化和多功能性的電子產品。根據本發明一些實施例可以製造不同的電子產品(如穿戴式設備或者另一合適的電子產品)。
另外，不同的主動和/或被動元件可以嵌入於單個半導體封裝結構中。如此，電子元件之間的信號傳輸路徑/距離可以顯著地縮短。如此，半導體封裝結構可以具有好的信號完整性和好的電源完整性。如此，改善了半導體封裝結構的電性能。例如，半導體封裝結構具有更好的SI/PI(signal integrity/power integrity，信號完整性/電源完整性)性能。
本發明實施例進一步提供了具有增強的熱解決方案的半導體封裝結構。一個或更多的導電柱(如垂直的銅通孔)可以嵌入於熱傳導性差的成型材料中。如此，可以在半導體封裝(諸如高功耗設備)中構建一個或更多的有效熱耗散路徑。 因此，顯著地改善了半導體封裝結構的質量和穩定性。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。

Claims (26)

  1. 一種半導體封裝結構，包括：一第一電子元件，設置於一基底上；一第二電子元件，堆疊在該第一電子元件上，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；及一成型材料，設置於該第一電子元件上並且圍繞該第二電子元件；一導電層，設置於該基底上；該導電層的朝向該基底的一部分底面與該導電層的朝向該基底的另一部分底面不共平面。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中，還包括：一第三電子元件，堆疊在該第二電子元件及該成型材料上。
  3. 如申請專利範圍第2項所述的半導體封裝結構，其中，該第一電子元件、該第二電子元件和該第三電子元件中的任一個包括：一主動元件或者一被動元件。
  4. 如申請專利範圍第2項所述的半導體封裝結構，其中，該第一電子元件的一導電墊朝向該第二電子元件的一導電墊；及/或者，該第二電子元件的一導電墊和該第三電子元件的一導電墊朝向該基底，以及該第一電子元件的一導電墊背向該基底。
  5. 如申請專利範圍第2項所述的半導體封裝結構，其中，於俯視方向上，該第二電子元件與該第一電子元件重疊；及/或，於俯視方向上，該第二電子元件與該第三電子元件重疊。
  6. 如申請專利範圍第2項所述的半導體封裝結構，其中，進一步包括：一導電結構，設置於該基底下方，該導電結構係電性連接至該第一電子元件、該第二電子元件以及該第三電子元件。
  7. 如申請專利範圍第2項所述的半導體封裝結構，其中，進一步包括：一介電層，設置於該基底和該成型材料之間，並且圍繞該第一電子元件。
  8. 如申請專利範圍第2項或第7項所述的半導體封裝結構，其中，進一步包括：一導電柱，設置於該第一電子元件上方並且由該成型材料圍繞，其中，該導電柱和該第二電子元件係並排設置。
  9. 如申請專利範圍第8項所述的半導體封裝結構，其中，該第三電子元件堆疊在該導電柱上。
  10. 如申請專利範圍第1項所述的半導體封裝結構，其中，該導電層的一部分底面設置在該第一電子元件的上方，而另一部分底面設置在該第一電子元件的下方。
  11. 一種半導體封裝結構，包括：一第一電子元件，設置於一基底上；一介電層，設置於該基底上並且圍繞該第一電子元件；一第二電子元件，堆疊於該第一電子元件上，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；一成型材料，設置在該介電層上並且圍繞該第二電子元件；以及一第一導電層，設置在該成型材料上；一第二導電層，設置於該介電層上，其中，該第二導電層的朝向該基底的一部分底面與該第二導電層的朝向該基底的另一部分底面不共平面。
  12. 如申請專利範圍第11項所述的半導體封裝結構，其中，該基底為一覆銅箔層壓板。
  13. 如申請專利範圍第11項所述的半導體封裝結構，其中，進一步包括：一導電結構，電性連接至該基底，其中該導電結構與該第一電子元件位於該基底的兩相對側。
  14. 如申請專利範圍第11項所述的半導體封裝結構，其中，該第一電子元件之導電墊朝向該第二電子元件之導電墊。
  15. 如申請專利範圍第11項所述的半導體封裝結構，其中，於俯視方向上，該第一電子元件與該第二電子元件重疊；及/或者，該成型材料之一部分夾在該第一電子元件和該第二電子元件之間。
  16. 如申請專利範圍第11項所述的半導體封裝結構，其中，進一步包括：一導電柱，設置於該第一電子元件上方並且被該成型材料圍繞，其中該導電柱和該第二電子元件並排設置。
  17. 如申請專利範圍第16項所述的半導體封裝結構，其中，於俯視方向上，該第一電子元件與該導電柱重疊；及/或者，該導電柱之頂面與該成型材料之頂面共平面；及/或者，該導電柱穿透該成型材料並且從該成型材料之表面凸出。
  18. 一種形成半導體封裝結構的方法，包括：於一基底上提供一第一電子元件；於該基底上形成一介電層以圍繞該第一電子元件；於該第一電子元件上堆疊一第二電子元件，其中，該第一電子元件之主動面朝向該第二電子元件之主動面；於該介電層上形成一成型材料以圍繞該第二電子元件；以及於該成型材料上形成一第一導電層；在堆疊該第二電子元件之前，於該介電層上形成一第二導電層，其中，該第二導電層延伸進該介電層中之複數個開口中；該第二導電層的朝向該基底的一部分底面與該第二導電層的朝向該基底的另一部分底面不共平面。
  19. 如申請專利範圍第18項所述的方法，其中，該第一電子元件通過一黏合層貼附在該基底上。
  20. 如申請專利範圍第18項所述的方法，其中，堆疊該第二電子元件的步驟包括：翻轉該第二電子元件，接著接合該第二電子元件。
  21. 如申請專利範圍第18項所述的方法，其中，進一步包括：於該介電層上形成一導電柱並且該導電柱被該成型材料圍繞，其中，該導電柱和該第二電子元件並排設置。
  22. 如申請專利範圍第21項所述的方法，其中，進一步包括：薄化該成型材料直至露出該導電柱之頂面。
  23. 如申請專利範圍第21項所述的方法，其中，進一步包括：於該導電柱及該第二電子元件上堆疊一第三電子元件，其中該第三電子元件係電性連接至該第一導電層。
  24. 如申請專利範圍第23項所述的方法，其中，堆疊該第三電子元件的步驟包括：翻轉該第三電子元件，接著接合該第三電子元件。
  25. 如申請專利範圍第18項所述的方法，其中，進一步包括：形成一導電結構，其中該導電結構接合至該基底的背向該第一電子元件和該第二電子元件的表面。
  26. 如申請專利範圍第18項所述的方法，其中，進一步包括：在形成該第一導電層之後，切割該基底、該介電層和該成型材料。
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