JP4413174B2 - アンテナ一体型回路装置 - Google Patents
アンテナ一体型回路装置 Download PDFInfo
- Publication number
- JP4413174B2 JP4413174B2 JP2005243651A JP2005243651A JP4413174B2 JP 4413174 B2 JP4413174 B2 JP 4413174B2 JP 2005243651 A JP2005243651 A JP 2005243651A JP 2005243651 A JP2005243651 A JP 2005243651A JP 4413174 B2 JP4413174 B2 JP 4413174B2
- Authority
- JP
- Japan
- Prior art keywords
- antenna
- conductor
- circuit device
- integrated circuit
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Details Of Aerials (AREA)
- Transceivers (AREA)
Description
図1は、第1の実施の形態に係るアンテナ一体型回路装置100の断面図である。アンテナ一体型回路装置100は、絶縁基材20、半導体回路素子30、チップ部品40、モールド樹脂50、アンテナ導体60、接地導体70、外部引出電極80を含む。図1において、便宜上、チップ部品40が実装される面を上方向とし、外部引出電極80が設けられた面を下方向とする。
第1の実施の形態では、高周波回路を構成する半導体回路素子30、複数のチップ部品40が、絶縁基材20上に設けられ、モールド樹脂50によって封止されることにより絶縁体層に埋め込まれていた。
図3は、第3の実施の形態に係るアンテナ一体型回路装置100の構成を示す断面図である。図2に示すアンテナ一体型回路装置100では、外部引出電極80とアンテナ導体60が同一面に設けられていたが、本実施の形態においては、アンテナ導体60は外部引出電極80とは異なる面に設けられている。
図6は、第4の実施の形態に係るアンテナ一体型回路装置100の構成を示す断面図である。図6に示すアンテナ一体型回路装置100では、アンテナ導体60a、60bが、アンテナ一体型回路装置100の両方の面に設けられている。その他の構成については第2、第3の実施の形態と同様である。
図7は、第5の実施の形態に係るアンテナ一体型回路装置100の構成を示す平面図である。図8、9は、それぞれ、第5の実施の形態に係るアンテナ一体型回路装置100の構成を示す図7のA−A’線上、B−B’線上の断面図である。本実施の形態のアンテナ一体型回路装置100は、基体110、絶縁基材20、半導体回路素子30、アンテナ導体60、および接地導体70を含む。
Claims (3)
- 絶縁体層と配線導体層が積層され、前記絶縁体層に回路素子が埋め込まれて形成される信号処理回路装置と、
前記信号処理回路装置の配線導体層に設けられたアンテナ導体と、
を備え、
前記信号処理回路装置は、前記アンテナ導体と前記回路素子との間に位置する配線導体層に、前記アンテナ導体とオーバーラップする接地導体を備えており、
前記アンテナ導体は、前記信号処理回路装置において外部引出電極が引き出される面と反対の面に設けられており、
さらに、前記アンテナ導体が設けられた面には、前記アンテナ導体が受信または送信する信号の周波数と同じ周波数の信号を調整する回路部品が実装されていることを特徴とするアンテナ一体型回路装置。 - 前記アンテナ導体と、前記接地導体の設けられた配線導体層の間の絶縁体層は、その他の絶縁体層と比誘電率が異なる材料で形成されることを特徴とする請求項1に記載のアンテナ一体型回路装置。
- 前記回路素子がRFIDチップであることを特徴とする請求項1に記載のアンテナ一体型回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005243651A JP4413174B2 (ja) | 2004-09-01 | 2005-08-25 | アンテナ一体型回路装置 |
US11/215,131 US7615856B2 (en) | 2004-09-01 | 2005-08-31 | Integrated antenna type circuit apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004254066 | 2004-09-01 | ||
JP2005243651A JP4413174B2 (ja) | 2004-09-01 | 2005-08-25 | アンテナ一体型回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006101494A JP2006101494A (ja) | 2006-04-13 |
JP4413174B2 true JP4413174B2 (ja) | 2010-02-10 |
Family
ID=36240814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005243651A Expired - Fee Related JP4413174B2 (ja) | 2004-09-01 | 2005-08-25 | アンテナ一体型回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4413174B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3255668A4 (en) * | 2015-04-14 | 2018-07-11 | Huawei Technologies Co., Ltd. | Chip |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4812777B2 (ja) * | 2006-01-20 | 2011-11-09 | パナソニック株式会社 | アンテナ内蔵モジュールとカード型情報装置およびそれらの製造方法 |
JP2008017421A (ja) * | 2006-07-10 | 2008-01-24 | Seiko Epson Corp | 半導体装置 |
JP4645911B2 (ja) * | 2006-10-25 | 2011-03-09 | 株式会社村田製作所 | 複合部品 |
CN101828301A (zh) * | 2007-10-18 | 2010-09-08 | 英特尔公司 | 用于多频带应用的使用低损耗衬底层叠的多层小型的嵌入式天线 |
JP2010239344A (ja) * | 2009-03-31 | 2010-10-21 | Fujikura Ltd | 無線回路モジュール |
JP5087118B2 (ja) * | 2010-09-28 | 2012-11-28 | 株式会社東芝 | 通信機器 |
KR101434003B1 (ko) | 2011-07-07 | 2014-08-27 | 삼성전기주식회사 | 반도체 패키지 및 그 제조 방법 |
US9431369B2 (en) | 2012-12-13 | 2016-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Antenna apparatus and method |
WO2015171118A1 (en) * | 2014-05-06 | 2015-11-12 | Intel Corporation | Multi-layer package with integrated antenna |
WO2018016624A1 (ja) * | 2016-07-22 | 2018-01-25 | 京セラ株式会社 | Rfidタグ用基板、rfidタグおよびrfidシステム |
KR102028714B1 (ko) * | 2017-12-06 | 2019-10-07 | 삼성전자주식회사 | 안테나 모듈 및 안테나 모듈 제조 방법 |
JP7013323B2 (ja) | 2018-05-17 | 2022-01-31 | 株式会社東芝 | 回路装置 |
JP7383312B2 (ja) | 2022-03-07 | 2023-11-20 | 日本ミクロン株式会社 | 無線センサー |
-
2005
- 2005-08-25 JP JP2005243651A patent/JP4413174B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3255668A4 (en) * | 2015-04-14 | 2018-07-11 | Huawei Technologies Co., Ltd. | Chip |
US10475741B2 (en) | 2015-04-14 | 2019-11-12 | Huawei Technologies Co., Ltd. | Chip |
Also Published As
Publication number | Publication date |
---|---|
JP2006101494A (ja) | 2006-04-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4413174B2 (ja) | アンテナ一体型回路装置 | |
US7615856B2 (en) | Integrated antenna type circuit apparatus | |
US8400307B2 (en) | Radio frequency IC device and electronic apparatus | |
EP2928015B1 (en) | Radio frequency ic device and electronic apparatus | |
US11264703B2 (en) | Chip antenna | |
KR101037035B1 (ko) | 무선 ic 디바이스 및 전자기기 | |
US11233336B2 (en) | Chip antenna and chip antenna module including the same | |
US6353420B1 (en) | Wireless article including a plural-turn loop antenna | |
US11211689B2 (en) | Chip antenna | |
US6518885B1 (en) | Ultra-thin outline package for integrated circuit | |
KR101188791B1 (ko) | Nfc 통신을 위한 안테나 내장형 카드형 정보 매체 및 그 제조 방법 | |
US11721913B2 (en) | Chip antenna module | |
US11069954B2 (en) | Chip antenna | |
US9177240B2 (en) | Communication device | |
US9336475B2 (en) | Radio IC device and radio communication terminal | |
JP4840275B2 (ja) | 無線icデバイス及び電子機器 | |
KR20200047089A (ko) | 칩 안테나 모듈 | |
TWI785713B (zh) | 射頻系統及通訊設備 | |
KR102444299B1 (ko) | 전자 소자 모듈 및 이의 제조 방법 | |
CN218383977U (zh) | 电路模块和rfid标签 | |
JP4783997B2 (ja) | 接触・非接触兼用型icモジュールとその製造方法 | |
JP2002236900A (ja) | 接触・非接触兼用型icモジュールとその製造方法 | |
JP2012221212A (ja) | 非接触型icモジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070112 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081203 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090209 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090303 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090428 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20090706 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090728 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090928 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091020 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091117 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121127 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131127 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |