TW201436156A - 封裝與方法 - Google Patents

封裝與方法 Download PDF

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Publication number
TW201436156A
TW201436156A TW103101924A TW103101924A TW201436156A TW 201436156 A TW201436156 A TW 201436156A TW 103101924 A TW103101924 A TW 103101924A TW 103101924 A TW103101924 A TW 103101924A TW 201436156 A TW201436156 A TW 201436156A
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Taiwan
Prior art keywords
die
interposer
connectors
substrate
package
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TW103101924A
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English (en)
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TWI567916B (zh
Inventor
Chin-Chuan Chang
Jing-Cheng Lin
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201436156A publication Critical patent/TW201436156A/zh
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Publication of TWI567916B publication Critical patent/TWI567916B/zh

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Abstract

封裝包括中介物，其包括第一基板，不具有穿孔於其中；多個再佈線，位於第一基板上；以及多個第一連接物，電性耦接至再佈線並位於其上。第一晶粒接合至第一連接物並位於其上。第一晶粒包括：第二基板；以及多個穿孔，位於第二基板中。第二晶粒接合至第一連接物並位於其上。第一晶粒與第二晶粒經由再佈線彼此電性耦接。多個第二連接物位於第一晶粒與第二晶粒上。第二連接物經由第二基板中的穿孔電性耦接至第一連接物。

Description

封裝與方法
本發明係關於封裝，更特別關於封裝的結構與其接合方法。
在某些三維積體電路(3DIC)中，先將元件晶粒接合至中介物後，再將其接合至封裝基板以形成封裝。操作元件晶粒所產生的熱必需散除。習知結構將元件晶粒的基板貼合至散熱器(heat spreader)以散熱，而散熱器的尺寸大於元件晶粒與封裝基板的尺寸。如此一來，元件晶粒所產生的熱將散佈至較大面積。將散熱片(heat sink)貼合至散熱器，可將傳導至散熱器的熱散除。
元件晶粒經由熱界面材料(TIM)如環氧樹脂基材料，可貼合至散熱片。此外，某些導熱材料如矽粒子可混合至環氧樹脂基材料中，以增加TIM的導熱性。散熱片經由另一TIM，可貼合至散熱器。然而採用兩層TIM的作法，會降低散熱效率。
此外，習知封裝面臨的挑戰還包括降低厚度，以及改善封裝中封裝構件之間的傳導效率。
本發明一實施例提供之封裝，包括：中介物，包 括：第一基板，不具有穿孔於其中；多個再佈線，位於第一基板上；以及多個第一連接物，電性耦接至再佈線並位於再佈線上；第一晶粒，接合至第一連接物並位於第一連接物上，其中第一晶粒包括：第二基板；以及多個穿孔，位於第二基板中；第二晶粒，接合至第一連接物並位於第一連接物上，其中第一晶粒與第二晶粒經由再佈線彼此電性耦接；以及多個第二連接物，位於第一晶粒與第二晶粒上，其中第二連接物經由第二基板中的穿孔電性耦接至第一連接物。
本發明一實施例提供之封裝，包括：中介物，不具有任何主動元件於其中，其中中介物包括：矽基板，不具有任何穿孔於其中；多個再佈線，位於矽基板上；以及多個第一連接物，電性耦接至再佈線並位於再佈線上；第一晶粒，接合至第一連接物並位於第一連接物上，其中第一晶粒包括：第一半導體基板；多個第一穿孔，位於第一半導體基板中；以及多個金屬柱，電性耦接至第一穿孔；第二晶粒，接合至第一連接物並位於第一連接物上，其中第一晶粒與第二晶粒經由再佈線彼此電性耦接；成型化合物，圍繞第一晶粒與第二晶粒，其中成型化合物之上表面與第一晶粒之上表面等高；以及多個第二連接物，位於第一晶粒與第二晶粒上，其中第二連接物經由第一半導體基板中的第一穿孔與金屬柱，電性耦接至第一連接物。
本發明一實施例提供之方法，包括：將第一晶粒接合至中介晶圓的正表面上，其中中介晶圓不具有任何穿孔於中介晶圓的第一基板中，且其中第一晶粒包括多個第一穿孔於 第一晶粒的第二基板中；施加成型化物於中介晶圓上，且第一晶粒係成型於成型化合物中；進行平坦化製程，使成型化合物之上表面與第一晶粒之上表面等高，直到露出第一晶粒的多個導電結構，其中導電結構電性耦接至中介晶圓；形成多個再佈線於成型化合物與第一晶粒上，其中再佈線電性耦接至導電結構；以及形成多個連接物以電性耦接至再佈線。
H1‧‧‧高度
T1‧‧‧厚度
20‧‧‧底填物
22‧‧‧成型化合物
26‧‧‧導電結構
28、132‧‧‧切割帶
29‧‧‧UBM
30、128‧‧‧焊球
32、130、204‧‧‧連接物
33、34、114‧‧‧介電層
35‧‧‧封裝
36‧‧‧PCB
100、300‧‧‧元件晶粒
102‧‧‧元件晶圓
104‧‧‧半導體基板
106‧‧‧積體電路元件
108‧‧‧內連線結構
110‧‧‧金屬線路與通孔
112、124‧‧‧金屬墊
114a、116a‧‧‧上表面
116、126‧‧‧金屬柱
118、218‧‧‧穿孔
120‧‧‧載板
122‧‧‧黏結劑
200‧‧‧中介晶圓
201‧‧‧中介物
202‧‧‧再佈線
206、306‧‧‧基板
220‧‧‧溝槽
304‧‧‧記憶體
402、404、406‧‧‧折線
第1A至1K圖係某些實施例中，製作面對背封裝的製程剖視圖；第2A至2I圖係某些實施例中，製作面對面異質封裝的製程剖視圖；第3A至3F圖係某些實施例中，製作面對面同質封裝的製程剖視圖；以及第4圖係樣品封裝中，樣品封裝的溫度對CPU晶粒之功率的折線圖。
下述內容將詳述本發明實施例如何製作與使用。可以理解的是，這些實施例所提供的多種可行發明概念，以實施於多種特定方式。然而這些特定實施例僅用以說明而非侷限本發明。
多種實施例提供封裝與其形成方法，以及形成封裝的中間製程。這些實施例的變化亦敘述如下。在多種實施例與對應的圖式中，相同標號將用以標示類似單元。
第1A至1K圖係某些實施例中，面對背封裝的製程剖視圖，其中中介物之正面係接合至元件晶粒之背面(及/或記憶晶粒之背面)。第1A至1D圖說明如何形成元件晶粒100。如第1A圖所示，形成元件晶圓102。元件晶圓102包含多個相同的元件晶粒100於其中。元件晶圓102可包含半導體基板104、積體電路元件106、與上方的內連線結構108形成其中。為簡化說明，後續圖式不包含必然存在的積體電路元件106。半導體基板104可為矽基板，或其他半導體材料如矽鍺合金、碳化矽、III-V族半導體化合物、或類似物。內連線結構108包含金屬線路與通孔110，用以內連線積體電路元件106。金屬線路與通孔110如圖所示，但此為示意圖而非詳細結構。積體電路元件106可包含主動元件如電晶體。元件晶圓102可為邏輯元件晶圓，其包含多個邏輯晶粒。為簡化說明，後續圖式不包含必然存在的積體電路元件106。
金屬墊112係形成於元件晶粒100中，並經由金屬線路與通孔110電性耦接至積體電路元件106。金屬墊112可為鋁、銅、鎳、或上述之組合。介電層114係形成於金屬墊112上。介電層114可為厚層狀物，其厚度T1大於約10μm，比如介於約10μm至約50μm之間。介電層114可擇自下列高分子：阻焊劑、聚苯并噁唑(PBO)、苯並環丁烷(BCB)、成型化合物、與類似物。在另一實施例中，介電層114可為氧化矽、氮化矽、或類似物。
金屬柱116係形成於介電層114上，並電性耦接至金屬墊112。在某些實施例中，金屬柱116之下表面接觸金屬墊 112的上表面。金屬柱116可為銅，因此又稱作銅柱。然而金屬柱116亦可為其他導電材料如鎳及/或鋁，且上述導電材料亦可應用於銅柱中。金屬柱116之高度H1亦可大於約10μm，比如介於約10μm至約50μm之間。在某些實施例中，金屬柱116的上表面116a與介電層114之上表面114a實質上等高。在其他實施例中，金屬柱116之上表面116a高於介電層114之上表面114a，即部份金屬柱116突出介電層114的上表面114a。穿孔118(導電通孔)係形成於半導體基板104上，且經由金屬墊112及金屬線路與通孔110電性耦接至金屬柱116。上述穿孔118又撐作穿透基板通孔(TSV)或穿透矽通孔。
接著如第1B圖所示，將元件晶圓102的正面安裝於載板120上，其安裝步驟可採用黏結劑122。舉例來說，載板120可為玻璃載板、陶瓷載板、或有機載板。在某些實施例中，黏結劑122可為極紫外光膠。接著進行背面研磨製程以移除多餘的部份半導體基板104，直到露出穿孔118。接著如第1C圖所示，形成連接物130於半導體基板104的背面上，且連接物130電性耦接至穿孔118。在某些實施例中，連接物130包含金屬墊(或線路)124、金屬柱126、與焊球128。額外再佈線(未圖示)亦可形成於半導體基板104的背面上，以內連線連接物130與穿孔118。連接物130亦可具有其他結構如焊球。
在形成連接物130後，分離元件晶圓102與載板120。接著如第1D圖所示，將元件晶圓102切割成個別的元件晶粒100。在某些實施例中為了切割元件晶圓102，先將元件晶圓102貼合至切割帶132上，再切割元件晶圓102。之後再分開個 別的元件晶粒100與切割帶132。
如第1E圖所示，中介晶圓200包含再佈線202，與連接至再佈線202的連接物204。再佈線202如圖所示，但此為示意圖而非詳細結構。再佈線202可包含分佈於多個層狀物中的金屬線路，以及使不同層之金屬線路內連線的通孔。再佈線202與連接物204位於基板206上。連接物204可為銅柱、金屬墊、焊料層、及/或類似物。在某些實施例中，基板206可為矽基板。在另一實施例中，基板206為介電基板如玻璃基板。
在某些實施例中，中介晶圓200可不具有主動元件(如電晶體)與被動元件(如電感、電阻、與電容)。在另一實施例中，中介晶圓200包含被動元件而不包含主動元件。在又一實施例中，中介晶圓200包含主動元件與被動元件於其中。中介晶圓200不具有穿透矽通孔於其中。綜上所述，每一連接物204與另一連接物204之間經由再佈線202連接。
如第1F圖所示，元件晶粒100與300接合至中介晶圓200。雖然圖式中只有一個元件晶粒100與一個元件晶粒300，但可將多個元件晶粒100與多個元件晶粒300接合至中介晶圓200。元件晶粒100的連接物130，係接合至中介晶圓200的連接物204。由於中介晶圓200的正面朝元件晶粒100的背面，上述個別的接合即所謂的面對背接合。
此外，元件晶粒300的連接物302接合至中介晶圓200的連接物204。在某些實施例中，元件晶粒300為記憶晶粒，但元件晶粒300亦可為邏輯晶粒。在某些實施例中，元件晶粒300可包含記憶體304如動態隨機存取記憶體(DRAM)、靜態隨 機存取記憶體(SRAM)、或類似物。記憶體304可電性耦接至中介晶圓200中的連接物204。綜上所述，元件晶粒100經由中介晶圓200中的再佈線202與連接物204，可電性內連線至元件晶粒300並電性耦接至記憶體304。
第1G圖施加底填物20至中介晶圓200與元件晶粒之間的空隙，以及中介晶圓200與元件晶粒300之間的空隙。此外，施加成型化合物22至元件晶粒100、元件晶粒300、與中介晶圓200上，以及元件晶粒100與300之間的空隙中。成型化合物22亦覆蓋元件晶粒100與元件晶粒300的上表面。接著進行硬化製程，使底填物20固化並使成型化合物22成型。在另一實施例中，可採用成型底填物取代底填物20與成型化合物22。
如第1H圖所示，進行平坦化製程如研磨於成型化合物22上，直到露出銅柱166與介電層114。綜上所述，介電層114的上表面114a、銅柱116的上表面116a、與成型化合物22的上表面22a為實質上等高。研磨後的結果為沒有任何成型化合物22高過元件晶粒100。由上視角度來看，介電層114圍繞並接觸銅柱116。此外，成型化合物22圍繞每一元件晶粒100中的銅柱116與介電層114所形成的積體構件。
如第1I圖所示，形成導電結構26，以及連接物32以電性連接至導電結構26。導電結構26可包含銅、鎢、鎳、及/或類似物。在某些實施例中，形成介電層33於元件晶粒100、元件晶粒300、與成型化合物22上，再圖案化介電層33以露出銅柱116。介電層34係形成於介電層33與導電結構26上。在某些實施例中，介電層33與34可為高分子層如聚亞醯胺、PBO、 或類似物。接著形成開口於介電層34中，以露出導電結構26。接著形成連接物32於開口中以連接至導電結構26。在某些實施例中，連接物32包含UBM(凸塊下金屬化物)29，以及UBM 29上的焊球30。在另一實施例中，連接物32可具有其他結構如銅柱、預焊層、或類似物。連接物32可經由導電結構26，電性耦接至中介晶圓200中的連接物204。此外，連接物32可經由中介晶圓200中的連接物204與再佈線202，電性耦接至元件晶粒300。
在第1J圖中，可採用研磨步驟薄化中介晶圓200的基板206。接著貼合中介晶圓200與切割帶28，再將中介晶圓200與其上的元件晶粒100與300切割成多個封裝35。每一封裝35包含一片中介晶圓200如中介物201。每一封裝35亦包含元件晶粒100與300，且兩者經由中介物201內連線。接著分開封裝35與切割帶28。
在某些實施例中，圖案化中介晶圓200的基板206以形成溝槽220。在切割步驟之前，可進行晶圓級的圖案化步驟如雷射刻槽、蝕刻、或類似方法。在薄化基板206之前或之後，可進行上述圖案化步驟。由下視視角來看，溝槽220可為中介物201中的格狀圖案，保留的部份基板206形成凸塊，且溝槽220圍繞上述凸塊。如此一來，基板206具有高散熱能力。最後形成的封裝如第1K圖(及第2I與第3F圖)所示，中介物201可具有或不具有溝槽220與凸塊。
如第1K圖所示，接合封裝至PCB(印刷電路板)36。在實施例中，連接物32為球格陣列(BGA)球狀物，因此可 直接接合至PCB 36，而不需任何封裝基板夾設其中。此外，中介物201可作為封裝的散熱單元，以及元件晶粒100與300之間的內連線。
第2A至2I圖與第3A至3F圖係其他實施例中，形成封裝的製程剖視圖。除了特別說明以外，這些實施例的構件之材料與形成方法，與第1A至1K圖所示之實施例中的構件之材料與形成方法基本上類似，且類似構件將以類似標號標示。換言之，第2A至2I圖與第3A至3F圖之構件的形成方法與材料之詳情，可參考第1A至1K圖所示之實施例。
如第2A至2B圖所示，製備元件晶粒100。在第2A圖中，形成元件晶圓102。第2A圖的元件晶圓102與第1A圖的元件晶圓102類似，在此不贅述。接著如第2B圖所示，將元件晶圓102切割為多個元件晶粒100。在此階段並未完成元件晶粒100，其後續製程如下述內容。
在第2C圖中，形成中介晶圓200。第2C圖的中介晶圓200與第1E圖的中介晶圓200基本上相同，在此不贅述。在第2D圖中，藉由元件晶粒100中的銅柱116與元件晶粒300中的連接物302，將元件晶粒100與300接合至中介晶圓200。同樣地，雖然圖示中只有單一元件晶粒100與單一元件晶粒300，但有多個元件晶粒100與多個元件晶粒300接合至中介晶圓200。在這些實施例中，中介晶圓200的正面，面對元件晶粒100的正面，因此個別的接合稱作面對面接合。
接著如第2E圖所示，施加底填物20與成型化合物22，其中成型化合物22的上表面高於元件晶粒100與300。接著 進行平坦化步驟如化學機械研磨(CMP)如第2F圖所示，直到露出穿孔118的背側末端。在某些實施例中，成型化合物22的層狀物可位於元件晶粒300上。在另一實施例中，研磨步驟將露出元件晶粒300的背表面。
如第2G圖所示，形成導電結構26、介電層33與34、以及連接物32。如此一來，連接物32可經由穿孔118電性耦接至中介晶圓200中的連接物204。此外，連接物32可經由中介晶圓200中的連接物204與再佈線202，電性耦接至元件晶粒300。在第2H與2I圖中，薄化中中介晶圓200中的基板206、將中介晶圓200貼合至切割帶28上、以及切割中介晶圓200。經上述步驟即形成封裝35如第2H圖所示，再將封裝35接合至PCB 36如第2I圖所示。
在第2I圖所示之實施例中，元件晶粒300可為記憶晶粒，其不含穿透矽通孔於其中，因此連接物32與中介物201之間的電性內連線係經由元件晶粒100而非元件晶粒300。在另一實施例中，穿透矽通孔亦形成於元件晶粒300中，因此元件晶粒100與300均可作為連接物32與中介物201之間的內連線路徑。第3A至3G圖為個別製程中的中間製程。
如第3A圖所示，元件晶粒100與元件晶粒300係接合至中介晶圓200。在這些實施例中，元件晶粒100與300之正面係接合至中介晶圓200的正面，因此個別的接合稱作面對面接合。穿孔118係埋置於半導體基板104，而穿孔218係埋置於元件晶粒300中的基板306中。基板306可為半導體基板如矽基板。
接著如第3B圖所示，施加並硬化底填物20與成型化合物22，其中成型化物22的上表面高於元件晶粒100與300的上表面。接著進行平坦化步驟如CMP，形成第3C圖所示的結構。進行CMP步驟直到露出半導體基板104與基板306，再持續CMP以完全露出穿孔118與218的背側末端。
如第3D圖所示，形成導電結構26、介電層33與34、以及連接物32。如此一來，連接物32電性耦接至中介晶圓200中的連接物204。在第3E與3F圖中，薄化中介晶圓200的基板206、將中介晶圓200貼合至切割帶28上、以及切割中介晶圓200，以形成封裝35。接著如第3F圖所示，將封裝35接合至PCB 36。
在本發明的實施例中，中介物可作為接合其上的晶粒之內連線。然而中介物不具有穿透矽通孔於其中。綜上所述，中介物並電性耦接至位於晶圓相反兩側上的任何封裝構件。如此一來，中介物可作為散熱單元。模擬結果指出，具有矽基板的中介物的散熱能力，與經由TIM貼合至晶粒的金屬蓋之散熱能力實質上相同。舉例來說，第4圖為三個樣本封裝的模擬結果比較。第一樣品封裝包含第1K圖所示的結構，其具有額外的熱墊接合至第1K圖中的中介物201，以及電磁干擾(EMI)遮罩貼合至熱墊。在第二樣品封裝中，熱介面材料(TIM)與金屬蓋取代第1K圖中的中介物201。在第三樣品封裝中，與第1G圖之成型化合物22相同的成型化合物層，取代第1K圖中的中介物201。至於第一、第二、與第三樣品封裝的其餘構件彼此相同。第4圖顯示的模擬結果中，第一、第二與第三樣品封裝之 溫度對元件晶粒100(如CPU晶粒)之功率的折線402、404、與406。由模擬結果可知，第三樣品封裝的溫度最高，即第三樣品封裝的散熱能力最差。第一樣品封裝與第二樣品封裝的溫度類似，證明本發明之實施例的封裝，與採用金屬蓋的第二樣品封裝之散熱能力一樣好。然而第一樣品封裝之金屬佈線能力優於第二樣品封裝。第4圖更顯示當CPU功率上升時，第一樣品封裝與第二樣品封裝仍具有類似的散熱能力。
此外，模擬結果指出當中介物中的基板厚度由775m下降至250μm時，第1K、2I、或3F圖中的封裝溫度將由75℃增加至77℃。換言之，大幅縮小封裝的總厚度並不會明顯地降低其散熱能力。此外，模擬結果亦比較整合金屬EMI遮罩的樣品封裝，與不具有金屬EMI遮罩的樣品封裝。在本發明實施例中，模擬的樣品封裝包含中介物(如第1K圖中的中介物201)與CPU晶粒(如第1K圖中的元件晶粒100)。模擬結果指出在開啟CPU晶粒時，整合金屬EMI遮罩的樣品封裝溫度介於約74.8℃至約77.2℃之間。與此相較，當開啟CPU晶粒時，不具有EMI遮罩的樣品封裝溫度介於約77.2℃至約79.2℃之間。EMI遮罩只讓封裝溫度降低約2℃至約3℃之間。由上述可知，採用中介物之封裝其散熱能力已夠好，因此EMI遮罩只稍微增加散熱能力。
在某些實施例中，封裝包括：中介物，其包括：第一基板，不具有穿孔於其中；多個再佈線，位於第一基板上；以及多個第一連接物，電性耦接至再佈線並位於其上。第一晶粒，接合至第一連接物並位於其上。第一晶粒包括：第二基板； 以及多個穿孔，位於第二基板中。第二晶粒接合至第一連接物並位於第一連接物上。第一晶粒與第二晶粒經由再佈線彼此電性耦接。多個第二連接物，位於第一晶粒與第二晶粒上。第二連接物經由第二基板中的穿孔電性耦接至第一連接物。
在其他實施例中，封裝包括：中介物，不具有任何主動元件於其中。中介物包括：矽基板，不具有任何穿孔於其中；多個再佈線，位於矽基板上；以及多個第一連接物，電性耦接至再佈線並位於其上。第一晶粒，接合至第一連接物並位於第一連接物上。第一晶粒包括：第一半導體基板；多個第一穿孔，位於第一半導體基板中；以及多個金屬柱，電性耦接至第一穿孔。第二晶粒，接合至第一連接物並位於其上，其中第一晶粒與第二晶粒經由再佈線彼此電性耦接。成型化合物，圍繞第一晶粒與第二晶粒。成型化合物之上表面與第一晶粒之上表面等高。多個第二連接物，位於第一晶粒與第二晶粒上。第二連接物經由第一半導體基板中的第一穿孔與金屬柱，電性耦接至第一連接物。
在其他實施例中，方法包括：將第一晶粒接合至中介晶圓的正表面上。中介晶圓不具有任何穿孔於中介晶圓的第一基板中。第一晶粒包括多個第一穿孔於第一晶粒的第二基板中。成型化物係施加於中介晶圓上，且第一晶粒係成型於成型化合物中。進行平坦化製程，使成型化合物之上表面與第一晶粒之上表面等高，直到露出第一晶粒的多個導電結構，其中導電結構電性耦接至中介晶圓。多個再佈線係形成於成型化合物與第一晶粒上其中再佈線電性耦接至導電結構。形成多個連 接物以電性耦接至再佈線。
雖然上述內容已詳述實施例與其優點，但應理解在不脫離申請專利範圍和實施例精神的前提下，可進行各種改變、替代、與變更。此外，申請專利範圍不限於上述內容中特定實施例的製程、機器、製作、組成、裝置、方法、和步驟。如本技術領域中具有通常知識者由本發明所知，根據本發明可用的方式與對應實施例，即可採用目前或未來研發之具有實質上相同功能或可達實質上相同結果的製程、機器、製作、組成、裝置、方法或步驟。綜上所述，申請專利範圍包括上述製程、機器、製作、組成、裝置、方法、或步驟。此外，每個申請專利範圍均為個別實施例，且各種申請專利範圍和實施例的組合均屬本發明範疇。
28‧‧‧切割帶
35‧‧‧封裝
36‧‧‧PCB
100、300‧‧‧元件晶粒
201‧‧‧中介物
206‧‧‧基板
220‧‧‧溝槽

Claims (12)

  1. 一種封裝，包括：一中介物，包括：一第一基板，不具有穿孔於其中；多個再佈線，位於該第一基板上；以及多個第一連接物，電性耦接至該些再佈線並位於該些再佈線上；一第一晶粒，接合至該些第一連接物並位於該些第一連接物上，其中該第一晶粒包括：一第二基板；以及多個穿孔，位於該第二基板中；一第二晶粒，接合至該些第一連接物並位於該些第一連接物上，其中該第一晶粒與該第二晶粒經由該些再佈線彼此電性耦接；以及多個第二連接物，位於該第一晶粒與該第二晶粒上，其中該些第二連接物經由該第二基板中的該些穿孔電性耦接至該些第一連接物。
  2. 如申請專利範圍第1項所述之封裝，其中該中介物不具有主動元件及/或被動元件於其中。
  3. 如申請專利範圍第1項所述之封裝，更包括：一成型化合物，圍繞該第一晶粒與該第二晶粒，其中該成型化合物之上表面與該第一晶粒之上表面等高；以及一介電層，位於該第一晶粒、該第二晶粒、與該成型化合物上，其中該些第二連接物位於該介電層上。
  4. 如申請專利範圍第1項所述之封裝，其中該第一晶粒經由一面對背接合法接合至該中介物，其中該第一晶粒之背面接合至該中介物的正面。
  5. 如申請專利範圍第1項所述之封裝，其中該第一晶粒經由一面對面接合法接合至該中介物，其中該第一晶粒之正面接合至該中介物的正面。
  6. 一種封裝，包括：一中介物，不具有任何主動元件於其中，其中該中介物包括：一矽基板，不具有任何穿孔於其中；多個再佈線，位於該矽基板上；以及多個第一連接物，電性耦接至該些再佈線並位於該些再佈線上；一第一晶粒，接合至該些第一連接物並位於該些第一連接物上，其中該第一晶粒包括：一第一半導體基板；多個第一穿孔，位於該第一半導體基板中；以及多個金屬柱，電性耦接至該些第一穿孔；一第二晶粒，接合至該些第一連接物並位於該些第一連接物上，其中該第一晶粒與該第二晶粒經由該些再佈線彼此電性耦接；一成型化合物，圍繞該第一晶粒與該第二晶粒，其中該成型化合物之上表面與該第一晶粒之上表面等高；以及多個第二連接物，位於該第一晶粒與該第二晶粒上，其中 該些第二連接物經由該第一半導體基板中的該些第一穿孔與該些金屬柱，電性耦接至該些第一連接物。
  7. 如申請專利範圍第6項所述之封裝，其中該第一晶粒之背面經由一面對背接合法接合至該中介物的正面，且其中該些金屬柱的上表面與該成型化合物的上表面等高。
  8. 如申請專利範圍第6項所述之封裝，其中該第一晶粒之正面經由一面對面接合法接合至該中介物的正面，且其中該些第一穿孔的上表面與該成型化合物的上表面等高，其中該第二晶粒更包括：一第二半導體基板；以及多個第二穿孔，貫穿該第二半導體基板，其中部份該些第二連接物經由該些第二穿孔電性耦接至部份該些第一連接物，且其中該些第一穿孔與該些第二穿孔之上表面等高。
  9. 如申請專利範圍第6項所述之封裝，其中該第二晶粒之上表面低於該第一晶粒之上表面，且其中部份該成型化合物延伸超過該第二晶粒的上表面並接觸該第二晶粒的上表面。
  10. 一種方法，包括：將一第一晶粒接合至一中介晶圓的正表面上，其中該中介晶圓不具有任何穿孔於該中介晶圓的一第一基板中，且其中該第一晶粒包括多個第一穿孔於該第一晶粒的一第二基板中；施加成型化物於該中介晶圓上，且該第一晶粒係成型於該成型化合物中；進行平坦化製程，使該成型化合物之上表面與該第一晶粒 之上表面等高，直到露出該第一晶粒的多個導電結構，其中該些導電結構電性耦接至該中介晶圓；形成多個再佈線於該成型化合物與該第一晶粒上，其中該些再佈線電性耦接至該些導電結構；以及形成多個連接物以電性耦接至該些再佈線。
  11. 如申請專利範圍第10項所述之方法，其中該第一晶粒經由一面對面接合法接合至該中介晶圓，以及在平坦化製程後，該些第一穿孔之上表面與該成型化合物之上表面等高。
  12. 如申請專利範圍第10項所述之方法，其中該第一晶粒經由一面對背接合法接合至該中介晶圓，以及在平坦化製程後，該第一晶粒中的該些金屬柱之上表面與該成型化合物之上表面等高。
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