TW201911476A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW201911476A
TW201911476A TW107126052A TW107126052A TW201911476A TW 201911476 A TW201911476 A TW 201911476A TW 107126052 A TW107126052 A TW 107126052A TW 107126052 A TW107126052 A TW 107126052A TW 201911476 A TW201911476 A TW 201911476A
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die
package
insulating layer
bonding
conductive
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TW107126052A
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TWI692838B (zh
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余振華
志航 董
余國寵
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台灣積體電路製造股份有限公司
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Abstract

在實施例中，一種封裝包括第一封裝結構。第一封裝結構包括具有第一主動側和第一背側的第一晶粒，第一主動側包括第一接合墊和第一絕緣層；第二晶粒，與第一晶粒接合，第二晶粒具有第二主動側和第二背側，第二主動側包括第二接合墊和第二絕緣層，第二晶粒的二主動側面向第一晶粒的第一主動側，第二絕緣層藉由介電質對介電質的接合鍵而與第一絕緣層接合；導電接合材料，與第一接合墊和第二接合墊接合，導電接合材料的回焊溫度低於第一接合墊的回焊溫度和第二接合墊的回焊溫度。

Description

半導體封裝及其形成方法
由於各種電子元件（如電晶體、二極體、電阻器、電容器等）的積集密度的不斷提高，半導體行業已經歷了快速發展。在很大程度上，積集密度的此種提高是由最小特徵尺寸的反覆運算（interative）縮減導致的，這使得更多的元件能夠整合到給定區域中。隨著對電子元件縮減的需求不斷增長，需要更小的以及更有創造力的半導體晶粒封裝技術。這種封裝系統的一個例子是疊層封裝（package-on-package, PoP）技術。在疊層封裝元件中，頂部半導體封裝堆疊在底部半導體封裝的頂部，以提供高積集度以及高元件密度。疊層封裝技術通常能夠生產功能增強且在印刷電路板（PCB）上佔用面積小的半導體元件。
以下揭露內容提供用於實現本揭露的不同特徵的許多不同的實施例或實例。以下闡述元件及配置的具體實例以簡化本揭露內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成於第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵，進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複使用參照編號及/或字母。這種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
另外，為易於說明，本文中可能使用例如“在...之下（beneath）”、“在...下面（below）”、“下部的（lower）”、“在...上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外還囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或其他定向），且本文中所用的空間相對性用語可同樣相應地進行解釋。
本文所論述的實施例可在特定的上下文中討論，即封裝結構（例如，疊層封裝（package on package, PoP）結構），包括用混合接合技術接合在一起的晶粒。晶粒與晶粒可以面對面（face-to-face, F2F）或面對背（face-to-back, F2B）接合在一起。舉例來說，在F2F接合配置中，晶粒的主動表面（面（face））接合在一起，而在F2B接合配置中，一個晶粒的主動表面接合到另一個晶粒的背面。另外，晶粒之間的混合接合包括介電質對介電質的接合（dielectric-to-dielectric bonding）以及金屬接合。舉例來說，藉由包含焊料接合（代替，例如銅與銅接合），可以顯著降低混合接合的接合溫度。
此外，本揭露的教示適用於包括一個或多個半導體晶粒的任何封裝結構。其他實施例考慮了其他應用，例如在閱讀本揭露的基礎上對於本領域普通技術人員而言顯而易見的不同的封裝類型或不同配置。應注意，本文所討論的實施例可不必繪示在結構中可能存在的每個構件或特徵。舉例來說，例如當討論一個構件可能足以表達實施例的態樣時，構件的多數個可以從圖中省略。此外，本文所討論的方法實施例可以被討論為以特定順序執行。但是，其他方法實施例可以按照任何邏輯順序執行。
圖1至圖3、圖4A至圖4O以及圖5至圖14繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。
圖1繪示製程中間步驟處的積體電路晶粒100。積體電路晶粒100可以是邏輯晶粒（例如中央處理單元（central processing unit）、移動應用處理器、特定應用積體電路（ASIC）、圖形處理器（GPU）、現場可程式邏輯門陣列（FPGA）、微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory, DRAM）晶粒、加寬匯流排（wide I/O）晶粒、磁性隨機存取記憶體（M-RAM）晶粒、電阻式隨機存取記憶體（R-RAM晶粒）、NAND晶粒、靜態隨機存取記憶體（SRAM）晶粒等）、記憶體立方體（例如高頻寬記憶體（high bandwidth memory, HBM）、混合記憶體立方體（Hybrid Memory Cube, HMC）等）、高資料速率收發器晶粒（high data rate transceiver die）、I/O界面晶粒（interface die）、IPD晶粒（例如積體被動元件）、電力管理晶粒（power management die）（例如，電力管理積體電路（PMIC）晶粒）、射頻（RF）晶粒、感測器晶粒、微機電系統（MEMS）晶粒、訊號處理晶粒（例如數位訊號處理（digital signal processing, DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end, AFE）晶粒）、單片3D異質晶片堆疊晶粒（monolithic 3D heterogeneous chiplet stacking die）、其類似物或其組合。
在圖1所示的中間步驟之前，積體電路晶粒100可以根據適當的製造製程進行處理，以在積體電路晶粒100中形成積體電路。舉例來說，積體電路晶粒100包括半導體基底102，例如是經摻雜或未經摻雜的矽或絕緣層上半導體（semiconductor-on-insulator, SOI）基底的主動層。半導體基底102可以包括其他半導體材料，例如鍺、化合物半導體、合金半導體或其組合。化合物半導體包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦。合金半導體包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。也可使用其他基底，例如多層式基底或梯度基底。可在半導體基底102中及/或上形成元件（例如電晶體、二極體、電容器、電阻器等），並且這些元件可以藉由內連線結構彼此內連，以形成積體電路。內連線結構例如是由在半導體基底102上的一個或多個介電層中的金屬化圖案形成的。在一些實施例中，內連線結構是利用鑲嵌及/或雙鑲嵌製程形成的。
積體電路晶粒100更包括做為外部連接的接墊104，例如銅接墊或鋁接墊或其組合。在一些實施例中，這些接墊104可使用在混合接合配置中，以將積體電路晶粒100接合到另一晶粒或結構。接墊104位於積體電路晶粒100的可被稱為主動側的部分上。絕緣層也位於積體電路晶粒100的主動側上。在一些實施例中，絕緣層由聚合物形成，聚合物可以是光敏材料，例如聚苯並噁唑（PBO）、聚醯亞胺（polyimide）、苯並環丁烯（BCB）或其類似物。在其他實施例中，絕緣層由氮化物（例如氮化矽）、氧化物（例如氧化矽）、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼摻雜磷矽玻璃（BPSG）、其組合或其類似物形成。絕緣層可以藉由旋轉塗佈、層壓（lamination）、化學氣相沉積（CVD）、其類似製程或其組合來形成。
在一些實施例中，接墊104可被稱為晶粒連接件，且可為導電柱（例如包括金屬（例如銅））。接墊104可例如是藉由金屬沉積、鍍覆、其組合或其類似製程形成。積體電路晶粒100的主動側（包括接墊104和絕緣層）可以藉由平坦化製程（例如化學機械研磨（CMP））被平坦化，以確保平坦的表面用於隨後的接合。
圖1還繪示形成在一些接墊104上的導電柱（conductive pillar）106。如圖所示，由於柱具有高的高寬比和相對較小的尺寸，導電柱106可從頂部至底部漸縮（taper）。導電柱106將延伸穿過隨後形成的包封體390（參見圖6），且在下文中可以被稱為穿孔（through via）。作為形成穿孔（導電柱106）的實例，在積體電路晶粒的主動側（例如內連線和所示的接墊104）上形成晶種層。在一些實施例中，晶種層是金屬層，其可以是單層或複合層。所述複合層包括多個由不同材料形成的子層（sub-layer）。在一些實施例中，晶種層包括鈦層和位於鈦層上的銅層。晶種層可以使用例如物理氣相沉積（PVD）或其類似製程來形成。在晶種層上形成光阻並將所述光阻圖案化。光阻可藉由由旋轉塗佈、層壓或其類似製程來形成，且可暴露於光照下，以進行圖案化。光阻的圖案對應於穿孔。所述圖案化形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及被暴露的部分晶種層上形成導電材料。導電材料可藉由鍍覆來形成，鍍覆例如是電鍍或無電鍍覆或其類似製程。導電材料可包括金屬，例如銅、鎳、鈦、鎢、鋁、其組合或其類似物。將光阻和其上未形成有導電材料的部分晶種層移除。光阻可以藉由可接受的灰化（ashing）或剝離（stripping）製程（例如使用氧電漿或其類似物）來移除。在移除光阻之後，例如藉由使用可接受的蝕刻製程（例如藉由濕式或乾式蝕刻）來移除暴露出的部分晶種層。晶種層的剩餘部分和導電材料形成穿孔（導電柱106）。
在一些實施例中，與沒有導電柱106的接墊104相比，具有導電柱106形成於其上的接墊104被形成為具有不同的配置（例如，具有導電柱的接墊104可以不像例如如圖4A中的凹進的接墊312所示那樣凹陷）。在一些實施例中，所有接墊104被形成為具有相同的配置。
圖2繪示製程中間步驟處的積體電路晶粒200。積體電路晶粒200可以是邏輯晶粒（例如，中央處理單元、ASIC、FPGA、微控制器等）、記憶體晶粒（例如DRAM晶粒、加寬匯流排晶粒、M-RAM晶粒、R-RAM晶粒、NAND晶粒、SRAM晶粒等）、記憶體立方體（例如HBM、HMC等）、高資料速率收發器晶粒、I/O界面晶粒、IPD晶粒（例如積體被動元件）、電力管理晶粒（例如PMIC晶粒）、RF晶粒、感測器晶粒、MEMS晶粒、訊號處理晶粒（例如DSP晶粒）、前端晶粒（例如AFE晶粒）、單片電路3D異質晶片堆疊晶粒、其類似物或其組合。在一些實施例中，積體電路晶粒100為邏輯晶粒，積體電路晶粒200為記憶體晶粒。
在圖2所示的中間步驟之前，積體電路晶粒200可根據適用的製造製程進行處理，以在積體電路晶粒200中形成積體電路。舉例來說，積體電路晶粒200包括半導體基底202，例如是經摻雜的或未經摻雜的矽或絕緣層上半導體（SOI）基底的主動層。半導體基底202可以包括其他半導體材料，例如鍺、化合物半導體、合金半導體或其組合。化合物半導體包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦。合金半導體包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。也可使用其他基底，例如多層式基底或梯度基底。可在半導體基底202中及/或上形成元件（例如電晶體、二極體、電容器、電阻器等），並且這些元件可以藉由內連線結構彼此內連，以形成積體電路。內連線結構例如是由在半導體基底202上的一個或多個介電層中的金屬化圖案形成的。在一些實施例中，內連線結構是利用鑲嵌及/或雙鑲嵌製程形成的。
積體電路晶粒200更包括穿孔204和接墊206。穿孔204可在製程的此處延伸穿過半導體基底202，或者如圖2所示，可在製程中的此處部分地延伸穿過半導體基底202。在部分實施例中，半導體基底202可被薄化（參見例如圖11），使得穿孔204可以延伸穿過半導體基底202。穿孔204可以藉由例如蝕刻基底202以在基底202中形成開口，並接著沉積導電材料於開口中來形成。用於形成穿孔204的這些開口可全部同時形成於同一製程，或者形成於單獨的製程。基底202中的開口可以使用合適的微影罩幕和蝕刻製程來形成。舉例來說，可在基底202上形成光阻並將其圖案化，並利用一個或多個蝕刻製程（例如，濕式蝕刻製程或乾式蝕刻製程）來移除期望形成穿孔204處的部分基底202。開口可從積體電路晶粒200的主動側（即圖2中積體電路晶粒200的下側）形成。開口可藉由在積體電路晶粒200的主動側上形成罩幕並將所述罩幕圖案化而形成。
開口可被例如襯裡（例如擴散阻擋層）、黏合層或其類似物以及導電材料填充。襯裡可包括鈦、氮化鈦、鉭、氮化鉭或其類似物。襯裡可使用化學氣相沉積（CVD）製程（例如電漿增強CVD（PECVD））來形成。然而，可使用其他替代製程，例如濺鍍或金屬有機化學氣相沉積（MOCVD）。
穿孔204的導電材料可以包括一種或多種導電材料，例如銅、銅合金、銀、金、鎢、鋁、鎳、其他導電金屬、其組合或其類似物。舉例來說，導電材料可以藉由如下製程來形成：沉積晶種層（未繪示）並使用電鍍、無電鍍覆或其類似製程在晶種層上沉積導電材料，導電材料填充和過量填充（overfilling）用於形成穿孔204的開口。在用於形成穿孔204的開口被填滿之後，用於形成穿孔204的開口之外的過量的襯裡和過量導電材料可被移除，所述移除可藉由研磨製程（例如CMP），但也可使用任何合適的移除製程。本領域的普通技術人員應理解，上述用於形成穿孔204的製程僅僅是形成穿孔204的一種方法，且其他方法也完全意圖被包括在實施例的範圍內。在一些實施例中，穿孔204從積體電路晶粒200的背側形成。
儘管在積體電路晶粒200中繪示兩個穿孔204，但應理解，在每個積體電路晶粒200中可以存在更多或更少的穿孔204。
接墊206可以是做為外部連接的銅接墊或鋁接墊或其組合。在一些實施例中，這些接墊206可使用在混合接合配置中，以將積體電路晶粒200接合到另一晶粒或結構。接墊206位於積體電路晶粒200的可被稱為主動側的部分上。接墊206可以形成在穿孔204上並且電耦合到穿孔204。一個或多個絕緣層208也位於積體電路晶粒200的主動側上。絕緣層208可以是無機層或有機層。在一些實施例中，絕緣層208由聚合物形成，該聚合物可以是光敏材料，例如PBO、聚醯亞胺、BCB或其類似物。在其他實施例中，絕緣層208由氮化物（例如氮化矽）、氧化物（例如氧化矽）、PSG、BSG、BPSG或其類似物形成。絕緣層208可以藉由旋轉塗佈、層壓、CVD、其類似製程或其組合形成。積體電路晶粒200的主動側（包括接墊206和絕緣層208）可以藉由平坦化製程（例如CMP）被平坦化，以確保平坦的表面用於隨後的接合。
在一些實施例中，接墊206可被稱為晶粒連接件，並且可以是導電柱或通孔（via）（舉例來說，包括金屬，例如銅、鋁或其組合）。接墊206可以藉由例如鍍覆或其類似製程來形成。在一些實施例中，接墊104和接墊206中的任何一個或兩個包括焊料材料，所述焊料材料在連接積體電路晶粒100和積體電路晶粒200時使用。這個結構將在圖4A至圖4O中詳細描述。
圖3繪示藉由混合接合將積體電路晶粒200接合到積體電路晶粒100。為了實現混合接合，將積體電路晶粒100和積體電路晶粒200輕輕地按壓在一起，使積體電路晶粒100和積體電路晶粒200藉由其主動側上的絕緣層（例如，絕緣層208）預先接合。儘管繪示一個積體電路晶粒100和一個積體電路晶粒200，但是混合接合可在晶圓級（例如晶圓上晶片（chip on wafer）或晶圓上晶圓（wafer on wafer））執行，其中形成於晶圓中的多個積體電路晶粒100與多個積體電路晶粒200（與繪示的積體電路晶粒200相同）被預先接合，並且在晶圓上排列成列與行。
在將所有積體電路晶粒100和積體電路晶粒200預先接合之後，執行回焊製程，以引起焊料（即接墊104和接墊206之間的焊料材料）的回焊以及焊料的相互擴散與接墊104和接墊206中的至少一個的金屬的相互擴散。回焊溫度可降至低於約200℃，以避免絕緣層和接合晶粒的損傷。舉例來說，回焊溫度可在約150℃至約200℃的範圍內。回焊時間可為約2小時至3小時。根據一些實施例，可採用熱壓縮接合（thermal compression bond, TCB）局部加熱接合界面，以減少接合時間和接合接點處的熱機械應力，所述熱機械應力由頂部電路晶粒、底部電路晶粒及接合工具之間的熱膨脹係數（CTE）失配導致。
藉由混合接合，接墊104和接墊206藉由焊料接合而彼此接合以形成接合接點（bonding joint）300。積體電路晶粒100的絕緣層也藉由形成在其與絕緣層208之間的接合鍵而接合到絕緣層208。舉例來說，一個絕緣層中的原子（例如氧原子）與另一絕緣層的原子（如氫原子）形成化學鍵或共價鍵（如O-H鍵）。根據各種實施例，絕緣層之間所形成的鍵為介電質對介電質的接合鍵，其可以是無機對聚合物的接合鍵、聚合物對聚合物的接合鍵或無機對無機的接合鍵（inorganic-to-inorganic bond）。此外，兩個積體電路晶粒100及/或積體電路晶粒200的表面絕緣層可彼此不同（舉例來說，一個是聚合物層，另一個是無機層），因此可在同一封裝中同時存在無機對聚合物的接合鍵、聚合物對聚合物的接合鍵及無機對無機的接合鍵的兩種類型的接合鍵。
圖4A、圖4B、圖4C、圖4D、圖4E、圖4F、圖4G、圖4H、圖4I、圖4J、圖4K、圖4L、圖4M、圖4N和圖4O繪示圖3的接合接點300的不同配置的詳細視圖。在每個所繪示的配置中，積體電路晶粒100和積體電路晶粒200可以是圖4A至圖4O中的頂部示例晶粒（即，接合界面350上方的晶粒）或在圖4A至圖4O中的底部示例晶粒（即，接合界面350下方的晶粒）。
圖4A繪示具有介電接合和凹進的接合墊的接合接點配置300A。在圖4A中，第一晶粒包括半導體基底302、半導體基底302上的介電層304、介電層308及介電層310、介電層304中的金屬化層306以及位於介電層310中且位於金屬化層306上的凹進的接合墊（recessed bond pad）（接墊312）。在圖4A中，第二晶粒包括半導體基底320、位於半導體基底320上的介電層322、介電層326和介電層328、位於介電層322中的金屬化層324、位於介電層328中且位於金屬化層324上的接合墊330以及包括層332和層334的突出的凸塊。界面350繪示介電層310和328之間的接合界面。
在本實施例中，介電層304、介電層308、介電層310、介電層322、介電層326和介電層328由氮化物（例如氮化矽）、氧化物（例如氧化矽）、PSG、BSG、BPSG或其類似物形成。當在各個晶粒上形成接合墊（接墊312）和接合墊330時，介電層308和介電層326可用作蝕刻停止層，且可由與周圍介電層不同的材料組成物形成。介電層310和介電層328在接合界面350（包括它們各自的導電特徵（接合墊330）和導電特徵（接墊312））處的表面可藉由平坦化製程（例如CMP）被平坦化，以確保用於接合的平坦表面。
金屬化層306和金屬化層324以及接合墊330可由導電材料形成，該導電材料可以包括金屬，例如銅、鈦、鎢、鋁或其類似物。導電材料可以藉由鍍覆形成，例如電鍍或無電鍍覆、濺鍍或其類似製程。這些結構可以藉由鑲嵌製程形成，並且可以包括擴散阻擋層、黏合層或其類似物、晶種層以及導電材料。擴散阻擋層及/或黏合層可以包括鈦、氮化鈦、鉭、氮化鉭或其類似物。擴散阻擋層及/或黏合層可以使用CVD製程（例如PECVD）形成。然而，也可使用其他替代製程，例如濺鍍或MOCVD。在一些實施例中，晶種層是金屬層，其可以是單層或複合層，所述複合層包括由不同材料形成的多個子層。在一些實施例中，晶種層包含鈦層及位於鈦層上的銅層。晶種層可使用例如PVD或其類似製程來形成。
凹進的接合墊（接墊312）可包括形成在介電層310的凹陷中的多個層。所述多個層可以包括晶種層312A、擴散阻擋層312B及導電材料層312C。此外，在晶種層312A與介電層310之間可以具有擴散阻擋層及/或黏合層。
擴散阻擋層及/或黏合層可包括鈦、氮化鈦、鉭、氮化鉭或其類似物。擴散阻擋層及/或黏合層可以使用CVD製程（例如PECVD）形成。然而，也可使用其他替代製程，例如濺鍍或MOCVD。
在一些實施例中，晶種層312A是金屬層，其可以是單層或複合層，所述複合層包括由不同材料形成的多個子層。在一些實施例中，晶種層312A包括鈦層及位於鈦層上的銅層。晶種層312A可以使用例如PVD或其類似製程來形成。
在一些實施例中，擴散阻擋層312B包含鎳層。擴散阻擋層312B可以使用例如PVD或其類似製程來形成。擴散阻擋層312B提供擴散保護，使得層334中的焊料材料不擴散到金屬化層306中。也可使用其他材料代替擴散阻擋層，只要所述材料提供適量的擴散保護。
導電材料層312C可以包括一種或多種導電材料，例如銅、銅合金、銀、金、鎢、鋁、鎳、其他導電金屬或其類似物。舉例來說，導電材料層312C可以藉由電鍍、無電鍍覆或其類似製程沉積導電材料而形成。接合墊（接墊312）的層312A、層312B和層312C沒有填滿介電層310中的凹陷，使得接合墊（接墊312）凹進於介電層310中。這種凹進的接合墊（接墊312）可以減小接合的封裝的高度（standoff）而允許較薄的封裝。在形成導電材料層312C之後，可以藉由研磨製程（例如CMP）移除位於凹陷外的多餘（例如，在晶粒接合之前沿著介電層310的上表面）的層312A、層312B和層312C。在本實施例中，層312A、層312B及層312C的組合厚度（combined thickness）小於介電層310的厚度。
凸塊層332和凸塊層334包括擴散阻擋層和焊料層。擴散阻擋層332可形成在接合墊330上。在一些實施例中，擴散阻擋層332包含鎳層。擴散阻擋層332可使用例如PVD或其類似製程來形成。擴散阻擋層332提供擴散保護，使得層334中的焊料材料不擴散到接墊/通孔（接合墊330）中。也可使用其他材料代替擴散阻擋層，只要所述材料提供適量的擴散保護。
焊料層334可形成在擴散阻擋層332上。焊料層334可由焊料材料形成。焊料材料包括銅、鋁、金、鎳、銀、鈀、錫、其類似物或其組合。焊料層334可藉由蒸鍍、電鍍、印刷（printing）、焊料轉移（solder transfer）、植球或其類似製程形成。焊料層334藉由焊料回焊製程（如上詳細描述）或熱壓縮接合製程接合到凹進的接合墊（接墊312）。焊料層334具有比接合墊（接墊312）的導電材料層312C和接墊/通孔（接合墊330）兩者更低的回焊溫度。這允許在將晶粒接合在一起時使用較低的回焊溫度。
如圖所示，圖4A至圖4O的接合接點配置300A至300O包括環繞焊料層334且位於接合墊（接墊312）與介電層322/328之間的空隙336或間隙。該空隙336或間隙可以保持未被填充並且在最終產品中可見。
圖4B繪示圖3的接合接點300的另一配置300B。本實施例與先前圖4A的實施例相似，不同之處在於，在本實施例中，接合界面350包括聚合物層340和聚合物層342而非介電層，且因此接合界面350包括聚合物接合。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，每個晶粒都包含聚合物層作為接合層。聚合物層340形成在第一晶粒上，聚合物層342形成在第二晶粒上。聚合物層340和聚合物層342可以是光敏材料，例如PBO、聚醯亞胺、BCB或其類似物。聚合物層340和聚合物層342可以藉由旋轉塗佈、層壓、其類似製程或其組合來形成。
圖4C繪示圖3的接合接點300的另一配置300C。本實施例與先前圖4B的實施例相似，不同之處在於，在本實施例中，接合墊（接墊312）並未凹入絕緣層中。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，接合墊（接墊312）不是凹進的，而是大體上平坦地跨過（across）金屬化層306。聚合物層340延伸到接合墊（接墊312）的上表面上方，且聚合物層342從第二晶粒的介電層322延伸，使得凸塊層332和凸塊層334在接合墊（接墊312）與接墊/通孔（金屬化層324）之間具有空間。
圖4D繪示圖3的接合接點300的另一配置300D。本實施例與先前圖4A的實施例相似，不同之處在於，在本實施例中，由於介電層310與介電層328彼此分離，接合界面350為焊料接合，而非介電接合。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，晶粒的介電層310與介電層328在接合製程後彼此分隔開。由於與其他實施例相比，間隔高度（standoff height）更大且接合強度可能會降低，這個實施例不一定是理想的。
圖4E繪示圖3的接合接點300的另一配置300E。本實施例與先前圖4A的實施例相似，不同之處在於，在本實施例中，金屬化層306位於穿孔204/穿孔466上方並與穿孔204/穿孔466（參見圖15的穿孔466）電耦合。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，穿孔204/穿孔466被形成為穿過積體電路晶粒100及/或積體電路晶粒200中的一個。
圖4F繪示圖3的接合接點300的另一配置300F。本實施例與先前圖4E的實施例相似，不同之處在於，在本實施例中省略了金屬化層306，且穿孔204/穿孔466直接耦合至凹進的接墊312。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，鄰接凹進的接墊312的穿孔204/穿孔466的寬度小於凹進的接墊312的寬度。
圖4G繪示圖3的接合接點300的另一配置300G。本實施例與先前圖4F的實施例相似，不同之處在於，在本實施例中，鄰接凹進的接墊312的穿孔204/穿孔466的寬度大於凹進的接墊312的寬度。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4H繪示圖3的接合接點300的另一配置300H。本實施例與先前圖4F的實施例相似，不同之處在於，在本實施例中，鄰接凹進的接墊312的穿孔204/穿孔466的寬度等於凹進的接墊312的寬度。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4I繪示圖3的接合接點300的另一配置300I。本實施例與先前圖4F的實施例相似，不同之處在於，在本實施例中，有多於一個的穿孔204/穿孔466與凹進的接墊312鄰接。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4J繪示圖3的接合接點300的另一配置300J。本實施例與先前圖4E的實施例相似，不同之處在於，在本實施例中，有多於一個的穿孔204/穿孔466與凹進的接墊312鄰接。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4K繪示圖3的接合接點300的另一配置300K。本實施例與先前圖4J的實施例相似，不同之處在於，在本實施例中，鄰接凹進的接墊312的金屬化層306的寬度等於凹進的接墊312的寬度。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4L繪示圖3的接合接點300的另一配置300L。本實施例與先前圖4F的實施例相似，不同之處在於，在本實施例中省略了凹進的接墊312，且層334中的焊料材料直接耦合至穿孔204/穿孔466。關於本實施例與前述實施例類似的細節在此不再贅述。
在本實施例中，穿孔204/穿孔466可以是凹陷的，使得層334中的焊料材料的一些部分延伸到穿孔204/穿孔466的最上表面及/或介電層304的表面的下方。在一些實施例中，空隙336的寬度大於鄰接層334中的焊料材料的穿孔204/穿孔466的寬度。
圖4M繪示圖3的接合接點300的另一配置300M。本實施例與先前圖4L的實施例相似，不同之處在於，在本實施例中，空隙336的寬度小於與層334中的焊料材料鄰接的穿孔204/穿孔466的寬度。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4N繪示圖3的接合接點300的另一配置300N。本實施例與先前圖4L的實施例相似，不同之處在於，在本實施例中，空隙336的寬度與鄰接層334中的焊料材料的穿孔204/穿孔466的寬度相等。關於本實施例與前述實施例類似的細節在此不再贅述。
圖4O繪示圖3的接合接點300的另一配置300O。本實施例與先前圖4J的實施例類似，不同之處在於，在本實施例中，省略了凹進的接墊312，且層334中的焊料材料直接耦合至金屬化層306。關於本實施例與前述實施例類似的細節在此不再贅述。
在圖4A、圖4B、圖4C、圖4E至圖4O的每種配置中，混合接合包括藉由將積體電路晶粒輕壓在一起，以使得在晶粒的主動側上的絕緣層（例如，絕緣層310、絕緣層328、絕緣層340及/或絕緣層342）預先接合。在預接合之後，執行回焊製程以引起焊料層334的回焊。
在圖5中，在圖3的各種構件上形成包封體390。包封體390可以是模塑化合物、環氧樹脂、氧化物或其類似物，並且可以藉由壓縮模塑（compression molding）、轉移模塑（transfer molding）、層壓、可流動CVD或其類似製程來形成。在一些實施例中，舉例來說，包封體可以是氧化物層，例如氧化矽、四乙氧基矽烷（tetraethylorthosilicate, TEOS）氧化矽或其類似物。在一些實施例中，舉例來說，包封體可以是氮化物層，例如氮化矽或其類似物。在一些實施例中，包封體可以是有機和無機包封體的複合物或其類似物。包封體390可以形成在包括積體電路晶粒100的晶圓上，使得導電柱106和積體電路晶粒200被埋入或被覆蓋。接著可固化包封體390。積體電路晶粒100的半導體基底102可具有約775μm的厚度T1。
在圖6中，半導體基底102可被薄化至小於厚度T1的厚度T2。薄化製程可包括研磨製程，例如機械研磨、CMP、蝕刻製程或其組合。在一些實施例中，厚度T2在約50μm至約150μm的範圍內。
在薄化製程之後，包括積體電路晶粒100和積體電路晶粒200的封裝可（例如藉由鋸切（saw）或切割（dice））被單體化（singulated），以形成多個封裝392。每個封裝392包括至少一個積體電路晶粒100和一個積體電路晶粒200。在一些實施例中，單體化發生在封裝區之間的切割道區。
圖7繪示載板基底400、形成在載板基底400上的離型層（release layer）402以及形成在離型層402上的介電層404。載板基底400可以是玻璃載板基底、陶瓷載板基底或其類似物。載板基底400可以是晶圓，使得在載板基底400上可同時形成多個封裝。離型層402可由基於聚合物的材料形成，所述基於聚合物的材料可以與載板基底400一起從將在後續步驟中形成的上覆結構移除。在一些實施例中，離型層402是一種基於環氧樹脂的熱釋放（thermal-release）材料，其在受熱時失去其黏性，例如是光熱轉化（light-to-heat-conversion, LTHC）離型塗層。在其他實施例中，離型層402可以是紫外光膠（ultra-violet glue, UV glue），當暴露於紫外光時失去其黏性。離型層402可為以液體點膠（dispense）並被固化、可為層壓到載板基底400上的層壓膜或其類似物。離型層402的頂面可被平坦化並可具有高平坦度。
介電層404形成在離型層402上。介電層404的底面可與離型層402的頂面接觸。在一些實施例中，介電層404由聚合物形成。聚合物例如是PBO、聚醯亞胺、BCB或其類似物。在其他實施例中，介電層404由氮化物（例如氮化矽）、氧化物（例如氧化矽）、PSG、BSG、BPSG或其類似物形成。介電層404可由任何可接受的沉積製程（例如旋轉塗佈、化學氣相沉積CVD、層壓或其類似製程或其組合）形成。在一些實施例中，在介電層404之上或之中形成一個或多個金屬化圖案，以形成重佈線結構。此重佈線結構可被稱為背側重佈線結構。
在圖7中，更形成電連接件406。電連接件406將延伸穿過隨後形成的包封體408（見圖9），並且在下文中可被稱為穿孔。作為形成穿孔（電連接件406）的例子，在下方結構（例如介電層404）上形成晶種層。在一些實施例中，晶種層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包含鈦層和位於鈦層上的銅層。晶種層可以使用例如PVD或類似製程來形成。在晶種層上形成光阻並將其圖案化。光阻可藉由旋轉塗佈、層壓或其類似製程來形成，並可暴露於光照以被圖案化。光阻的圖案對應於穿孔（電連接件406）。所述圖案化形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及暴露出的部分晶種層上形成導電材料。導電材料可以藉由鍍覆（例如電鍍、無電鍍覆或類似製程）來形成。導電材料可包括金屬，例如銅、鈦、鎢、鋁或其類似物。移除光阻和其上未形成導電材料的部分晶種層。光阻可藉由可接受的灰化或剝離製程（例如使用氧電漿或其類似物）來移除。在移除光阻之後，例如藉由使用可接受的蝕刻製程（例如濕式或乾式蝕刻）移除暴露出的部分晶種層。晶種層的剩餘部分和導電材料形成穿孔（電連接件406）。
在圖8中，將封裝392貼附到介電層404。儘管繪示貼附一個封裝392，但應理解，可在每個封裝區中貼附更多或更少的封裝392。雖然未繪示，但封裝392可以藉由黏合層（未繪示）而被貼附。該黏合層可以是任何合適的黏合劑、環氧樹脂、晶粒貼附膜（die attach film, DAF）或其類似物。
在圖9中，在各種構件上形成包封體408。包封體408可以是模塑化合物、環氧樹脂或其類似物，並可藉由壓縮模塑、層壓、轉移模塑或其類似製程來形成。包封體408可形成在載板基底400上，使得電連接件406和封裝392被埋入或被覆蓋。接著可固化包封體408。包封體408和包封體390可由相同的材料或不同的材料製成。
在圖10中，包封體408可經歷研磨製程，以暴露出電連接件406、導電柱106和穿孔204。在研磨製程之後，電連接件406的表面、導電柱106的表面、穿孔204的表面、半導體基底202的表面和包封體408的表面齊平。在一些實施例中，舉例來說，如果電連接件406、導電柱106和穿孔204已暴露，則可省略研磨。下文中，可將電連接件406和導電柱106分別稱為穿孔和穿孔。
在圖11中，形成前側重佈線結構410。前側重佈線結構410包括一個或多個介電層414和一個或多個金屬化圖案412。
前側重佈線結構410的形成可開始於藉由在包封體408、穿孔（電連接件406）、穿孔204和穿孔（導電柱106）上沉積介電層414。在一些實施例中，穿孔（導電柱106）和穿孔204可具有形成在其頂部上的導電接墊，以幫助上覆的金屬化圖案412著陸（land）並電耦合至相應的穿孔（導電柱106）和穿孔204（參見例如具有接墊494的圖23）。在一些實施例中，介電層414由聚合物形成，所述聚合物可以是可使用微影罩幕被圖案化的光敏材料，例如PBO、聚醯亞胺、BCB或其類似物。在其他實施例中，介電層414由氮化物（例如氮化矽）、氧化物（例如氧化矽）、PSG、BSG、BPSG或其類似物形成。介電層414可以藉由旋轉塗佈、層壓、CVD、其類似製程或其組合來形成。
接著，介電層414被圖案化。所述圖案化形成開口，以暴露出部分穿孔（電連接件406）、部分穿孔（導電柱106）及部分穿孔204。圖案化可藉由可接受的製程來實現，例如當介電層414是光敏材料時藉由將介電層414暴露於光；或者藉由使用剝蝕（ablation）（例如雷射剝蝕（laser ablation）；或者藉由使用蝕刻（例如非等向性蝕刻）。如果介電層414是光敏材料，則可在曝光介電層414之後對其進行顯影。
接下來，在介電層414上形成具有通孔的金屬化圖案412。作為形成金屬化圖案412的例子，在介電層414上以及穿過介電層414的開口中形成晶種層（未繪示）。在一些實施例中，晶種層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和位於鈦層上的銅層。晶種層可以使用例如PVD或其類似製程來形成。然後在晶種層上形成光阻並將其圖案化。光阻可藉由旋轉塗佈或其類似製程形成，並可暴露於光照而被圖案化。光阻的圖案對應於金屬化圖案412。所述圖案化形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及暴露的部分晶種層上形成導電材料。導電材料可以藉由鍍覆（例如電鍍或無電鍍覆或其類似製程）形成。導電材料可以包含金屬，例如銅、鈦、鎢、鋁或其類似物。然後，移除光阻和其上未形成導電材料的部分晶種層。可藉由可接受的灰化或剝離製程（例如使用氧電漿或其類似物）來移除光阻。在移除光阻之後，例如藉由使用可接受的蝕刻製程（例如濕式或乾式蝕刻）來移除暴露的部分晶種層。晶種層的剩餘部分和導電材料形成金屬化圖案412和通孔。通孔形成在穿過介電層414至例如穿孔（電連接件406）、穿孔（導電柱106）和穿孔204的開口中。
可重複此製程，以形成更多的介電層414和更多的金屬化圖案和通孔412，以繼續形成重佈線結構410。用於形成重佈線結構410的這些層的材料和製程可以類似於上述的材料和製程，在此不再贅述。在一些實施例中，重佈線結構410藉由鑲嵌製程形成。在一些實施例中，重佈線結構410的一些層藉由雙鑲嵌製程形成，而其他層由前述段落中描述的製程（例如，半加成製程（semi-additive process, SAP））形成。
繪示前側重佈線結構410做為示例。更多或更少的介電層和金屬化圖案可形成在前側重佈線結構410中。如果要形成更少的介電層和金屬化圖案，則可省略上述步驟和製程。如果要形成更多的介電層和金屬化圖案，則可重複上述步驟和製程。本領域的普通技術人員將容易地理解哪個步驟和製程將被省略或重複。
在圖12中，在前側重佈線結構410的外側形成接墊（未繪示），並在接墊上形成導電連接件416。接墊用於耦合至導電連接件416，且可被稱為凸塊下金屬（under bump metallurgie, UBM）。接墊可被形成為穿過重佈線結構410的最上層介電層414的開口至最上層的金屬化圖案412。作為形成接墊的例子，在介電層414上形成晶種層（未繪示）。在一些實施例中，晶種層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和位於鈦層上的銅層。晶種層可以使用例如PVD或其類似製程來形成。然後在晶種層上形成光阻並將其圖案化。光阻可藉由旋轉塗佈或其類似製程形成，並可暴露於光照而被圖案化。光阻的圖案對應於接墊。所述圖案化形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及暴露的部分晶種層上形成導電材料。導電材料可以藉由鍍覆（例如電鍍或無電鍍覆或其類似製程）形成。導電材料可以包含金屬，例如銅、鈦、鎢、鋁或其類似物。然後，移除光阻和其上未形成導電材料的部分晶種層。可藉由可接受的灰化或剝離製程（例如使用氧電漿或其類似物）來移除光阻。在移除光阻之後，例如藉由使用可接受的蝕刻製程（例如濕式或乾式蝕刻）來移除暴露的部分晶種層。晶種層的剩餘部分和導電材料形成接墊。在實施例中，當形成不同的接墊時，可以使用更多的光阻和圖案化步驟。
在圖12中，更形成導電連接件416於接墊/UBM上。導電連接件416可以是球柵陣列（ball grid array, BGA）連接件、焊球（solder ball）、金屬柱（metal pillar）、受控塌陷晶片連接（controlled collapse chip connection, C4）凸塊、微凸塊（micro bump）、藉由無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique, ENEPIG）形成的凸塊或其類似物。導電連接件416可包括導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似物或其組合。在一些實施例中，導電連接件416是藉由如下製程來形成的：首先藉由常用方法（例如蒸鍍、電鍍、印刷、焊料轉移、植球或其類似製程）形成一層焊料。在結構上形成了一層焊料之後，進行回焊，以將材料成形為所需的凸塊形狀。在另一實施例中，導電連接件416為金屬柱（例如，銅柱），且由濺鍍、印刷、電鍍、無電鍍覆、CVD或其類似製程形成，並可被稱為金屬柱連接件。金屬柱可以是無焊料的，且具有大體上垂直的側壁。在一些實施例中，在金屬柱連接件416的頂部形成金屬頂蓋層（未繪示）。金屬頂蓋層可包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、其類似物或其組合，且可藉由鍍覆製程來形成。
在圖13中，執行載板基底脫離（de-bonding），以將載板基底400從介電層404分離（脫離）。由此在載板的每個封裝區中形成第一封裝420。根據一些實施例，所述脫離包括在離型層402上投射光線（例如雷射光線或UV光線），使得離型層402在光熱作用下分解，並使載板基底400脫離。形成穿過介電層404的開口，以暴露出部分金屬化圖案穿孔（電連接件406）。舉例來說，開口可使用雷射鑽孔、蝕刻或其類似製程形成。
圖14繪示根據一些實施例的封裝結構的剖視圖。所述封裝結構可被稱為疊層封裝結構。在圖14中，將第二封裝450貼附到第一封裝420。第二封裝450包括基底430及耦合至基底430的一個或多個堆疊晶粒440（晶粒440A和晶粒440B）。儘管繪示單一堆疊晶粒440（晶粒440A和晶粒440B），但在其他實施例中，多個堆疊晶粒440（各自具有一個或多個堆疊晶粒）可並排（side by side）耦合至基底430的同一表面。基底430可由半導體材料形成，所述半導體材料例如是矽、鍺、金剛石或其類似物。在一些實施例中，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳鍺化矽（silicon germanium carbide）、磷砷化鎵（gallium arsenic phosphide）、磷銦化鎵（gallium indium phosphide）、這些的組合及其類似物。另外，基底430可以是絕緣層上矽（silicon-on-insulator, SOI）基底。通常，絕緣層上矽基底包括一層半導體材料，例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺（silicon germanium on insulator, SGOI）或其組合。在另一實施例中，基底430是基於絕緣芯（insulating core），例如玻璃纖維增強型樹脂芯（fiberglass reinforced resin core）。一種示例性芯體材料是玻璃纖維樹脂，例如FR4。其他芯體材料包括雙馬來醯亞胺三嗪（bismaleimide-triazine, BT）樹脂或其他印刷電路板（printed circuit board, PCB）材料或膜。構成膜（build up film）（例如味之素構成膜（Ajinomoto build-up film, ABF））或其他層壓材料（laminates）也可用於基底430。
基底430可包括主動和被動元件（未繪示）。本領域的普通技術人員應理解，可使用各種各樣的元件，例如電晶體、電容器、電阻器、這些元件的組合及其類似物，以產生設計用於第二封裝450的結構和功能要求。這些元件可以使用任何合適的方法來形成。
基底430還可包括金屬化層（未繪示）和穿孔432。金屬化層可形成在主動元件和被動元件之上，且被設計成連接各種元件以形成功能電路。金屬化層可以由介電（例如低k介電材料）和導電材料（例如銅）的交替層形成，且具有通孔以互連導電材料層，並可藉由任何合適的製程（例如沉積、鑲嵌、雙鑲嵌或其類似製程）來形成。在一些實施例中，基底430是大體上沒有主動元件和被動元件的。
基底430可具有在基底430的第一側的接合墊434，以耦合至堆疊晶粒440，以及具有在基底430的第二側（第二側與第一側相對）的接合墊436，以耦合至導電連接件438。在一些實施例中，接合墊434和接合墊436是藉由以下製程來形成：在基底430的第一側和第二側的介電層（未繪示）中形成凹陷（未繪示）。凹陷可被形成為允許接合墊434和接合墊436嵌入介電層中。在其他實施例中，接合墊434和接合墊436可形成在介電層上，因此可省略凹陷。在一些實施例中，接合墊434和接合墊436包括由銅、鈦、鎳、金、鈀、其類似物或其組合形成的薄晶種層（未繪示）。接合墊434和接合墊436的導電材料可沉積在薄晶種層上。導電材料可藉由電化學鍍覆製程、無電鍍覆製程、CVD、ALD、PVD、其類似物或其組合來形成。在一個實施例中，接合墊434和接合墊436的導電材料為銅、鎢、鋁、銀、金、其類似物或其組合。
在實施例中，接合墊434和接合墊436是包括三層導電材料（例如鈦層、銅層和鎳層）的UBM。然而，本領域的普通技術人員應理解，有許多適於形成接合墊434和接合墊436的材料和層的合適的佈置，例如鉻/鉻-銅合金/銅/金的佈置、鈦/鈦鎢/銅的佈置或者銅/鎳/金的佈置。任何可用於接合墊434和接合墊436的合適的材料或材料層都意欲完全包括在本申請的範圍內。在一些實施例中，穿孔432延伸穿過基底430並將至少一個接合墊434連接到至少一個接合墊436。
在所示的實施例中，堆疊晶粒440藉由打線（wire bond）442耦合至基底430，但也可以使用其他連接件，例如導電凸塊。在實施例中，堆疊晶粒440為堆疊記憶體晶粒。舉例來說，堆疊晶粒440可以是記憶體晶粒，例如低功率雙倍資料速率（low-power double data rate, LPDDR）記憶體模組（例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似的記憶體模組）。
堆疊晶粒440和打線442可被模塑材料444包封。舉例來說，可使用壓縮模塑法將模塑材料444模塑（mold）於堆疊晶粒440和打線442上。在一些實施例中，模塑材料444是模塑化合物、聚合物、環氧樹脂、氧化矽填充材料、其類似物或其組合。可執行固化步驟以固化模塑材料444，其中所述固化可以是熱固化、UV固化、其類似製程或其組合。
在一些實施例中，堆疊晶粒440和打線442埋入模塑材料444中，並且在模塑材料444固化之後，進行平坦化步驟（例如研磨），以移除模塑材料444的多餘部分並提供大體上平坦的表面，以形成第二封裝450。
在形成第二封裝450之後，第二封裝450藉由導電連接件438、接合墊436和穿孔（電連接件406）（或背側重佈線結構（如果存在））機械地以及電性地接合到第一封裝420。在一些實施例中，堆疊晶粒440可藉由打線442、接合墊434和接合墊436、穿孔432、導電連接件438、穿孔（電連接件406）和重佈線結構410耦合到封裝392（圖6）。
導電連接件438可以類似於上述的導電連接件416，在此不再贅述，但導電連接件438與導電連接件416不必相同。導電連接件438可設置在基底430的設置有堆疊晶粒440的相對側上。在一些實施例中，也可在與堆疊晶粒440相對的基底的一側上形成阻焊劑（solder resist）（未單獨標示）。導電連接件438可設置在阻焊劑的開口中，以與基底430中的導電特徵（例如，接合墊436）電性和機械耦合。阻焊劑可用於保護基底430的區域免受外部損傷。
在一些實施例中，在接合導電連接件438之前，導電連接件438被助焊劑（flux）（未繪示）塗覆，例如免清洗助焊劑（no-clean flux）。導電連接件438可浸入助焊劑中，或者助焊劑可被噴射（jet）到導電連接件438上。在另一個實施例中，助焊劑可應用於穿孔（電連接件406）的表面（或者背側重佈線結構（如果存在））。
在一些實施例中，導電連接件438可以具有在回焊導電連接件438之前選擇性地形成於其上的環氧助焊劑（epoxy flux）（未繪示），且在第二封裝450貼附至第一封裝420之後，所述環氧助焊劑的至少一些環氧部分保留。
底部填充劑（underfill）（未繪示）可形成於第一封裝420和第二封裝450之間，並圍繞導電連接件438。底部填充劑可以減小應力並保護由導電連接件438的回焊所形成的接點。底部填充劑可在貼附第二封裝450之後藉由毛細流動製程（capillary flow process）形成，或者可在貼附第二封裝450之前藉由合適的沉積方法形成。在形成有環氧助焊劑的實施例中，環氧助焊劑可以作為底部填充劑。
第二封裝450和第一封裝420之間的接合可以是焊料接合。在實施例中，第二封裝450藉由回焊製程接合到第一封裝420。在回焊製程期間，導電連接件438與接合墊436和穿孔（電連接件406）（或背側重佈線結構（如果存在））接觸，以將第二封裝450物理耦合及電耦合至第一封裝420。在接合製程之後，在穿孔（電連接件406）（或背側重佈線結構（如果存在））與導電連接件438的界面處以及導電連接件438與接合墊436之間的界面處可形成金屬間化合物（intermetallic compound, IMC）（未繪示）。在實施例中，在接合製程之後，可使用底部填充材料覆蓋導電連接件，以提供額外的保護，防止不利環境條件，例如濕氣（moisture）、顆粒（particle）與化學腐蝕（chemical corrosion）或其類似物。
沿切割道區（例如在封裝區之間）進行單體化製程（singulation process）。由此從一個封裝區產生被單體化的第一封裝420和第二封裝450。在一些實施例中，在第二封裝450貼附到第一封裝420之後執行單體化製程。在其他實施例（未繪示）中，在第二封裝450貼合到第一封裝420之前（例如在載板基底400脫離之後）執行單體化製程。
可對圖15的封裝結構執行進一步的製程。舉例來說，可使用導電連接件416將圖15的封裝結構安裝到封裝基底。
圖15至圖21繪示根據一些實施例的另一種封裝結構的剖視圖。圖15至圖21中的實施例與圖1至圖14所示的實施例相似，不同之處在於，在本實施例中，積體電路晶粒100中包括穿孔466，而積體電路晶粒200不包含穿孔。另外，積體電路晶粒100和積體電路晶粒200在封裝結構中是相反定向的。舉例來說，在將積體電路晶粒100和積體電路晶粒200貼附至載板基底400（見圖18）時，積體電路晶粒100位於積體電路晶粒200上方。關於本實施例與前述實施例類似的細節在此不再贅述。
在圖15中，積體電路晶粒100被繪示為包括穿孔466。在此不再重複關於與前述實施例的積體電路晶粒100類似的本實體例的積體電路晶粒100的細節。
在本實施例中，穿孔466從積體電路晶粒100的主動側的接墊104延伸到積體電路晶粒100的半導體基底102中。穿孔466的形成可以類似於前述實施例中的積體電路晶粒200的穿孔204，在此不再贅述。
儘管在積體電路晶粒100中繪示兩個穿孔466，但應理解，在每個積體電路晶粒100中可存在更多或更少的穿孔466。
圖16繪示對圖15的結構的進一步製程。這兩個圖之間的製程與參考圖2和圖3所示和所述的製程類似，圖3是與圖16等同的中間步驟，且在此不再贅述。
在圖16中，積體電路晶粒100和積體電路晶粒200藉由接合接點300接合在一起。接合接點300可以是圖4A至圖4O中的接合接點配置300A至300O中的任何一個。
圖17繪示對圖16的結構的進一步製程。這兩個圖之間的製程類似於參考圖3至圖5所示和所述的製程，圖5是與圖17等同的中間步驟，於此不再贅述。用包封體464包封接合的積體電路晶粒100和積體電路晶粒200，以形成封裝470。
圖18繪示將封裝470貼附至載板基底400上，這類似於上述在圖7和8中所描述的那樣，且在此不再贅述。在圖18中，封裝470貼附至載板基底400時，積體電路晶粒200比積體電路晶粒100更靠近載板基底400。
圖19繪示對圖18的結構的進一步製程。這兩個圖之間的製程類似於以上參考圖9和圖10所示和所述的製程，其中圖10是與圖19等同的中間步驟，且在此不再贅述。封裝470被包封體472包封，且上表面被平坦化。
在圖19中，包封體472可經受研磨製程，以暴露出電連接件406和穿孔466。在研磨製程之後，電連接件406的表面、穿孔466的表面、半導體基底102的表面和包封體472的表面齊平。
圖20繪示對圖19的結構的進一步製程。這兩個圖之間的製程類似於參考圖10和圖11所示和所述的製程，其中圖11是與圖20等同的中間步驟，且在此不再贅述。在圖20中，重佈線結構410形成於穿孔（電連接件406）和穿孔466上並電耦合到穿孔（電連接件406）和穿孔466。
圖21繪示對圖20的結構的進一步製程。這兩個圖之間的製程類似於參考圖12至圖14所示和所述的製程，其中圖14是與圖21等同的中間步驟，且在此不再贅述。在圖21中，第二封裝450被接合到圖20的封裝結構476。
可對圖21的封裝結構進行進一步的製程。舉例來說，可使用導電連接件416將圖21的封裝結構安裝到封裝基底。
圖22至圖28繪示根據一些實施例的另一封裝結構的剖視圖。圖22至圖28中的實施例類似於圖15至圖21所示的實施例，不同之處在於，在本實施例中，積體電路晶粒100和積體電路晶粒200是面對背（face-to-back）接合，而不是面對面（face-to-face）接合。另外，積體電路晶粒100包括位於積體電路晶粒100的主動側的接墊104上的晶粒連接件488和絕緣層490。這些晶粒連接件488和絕緣層490可在隨後的平坦化製程期間保護接墊104。關於本實施例與前述實施例類似的細節在此不再贅述。
晶粒連接件488可以由與上述接墊104相似的材料和類似的製程形成，於此不再贅述。在本實施例中，晶粒連接件488可為銅柱，接墊104可以是鋁接觸墊。絕緣層490可類似於上述絕緣層208，於此不再贅述。
在圖23中，將積體電路晶粒100的主動側貼附至載板基底498。載板基底498與上述的載板基底400相似，於此不再贅述。積體電路晶粒100的背側被薄化，以暴露出穿孔466。所述薄化可類似於上述在圖6中描述的薄化製程，於此不再贅述。在薄化製程之後，在積體電路晶粒100的背側形成絕緣層492和絕緣層496以及接墊494。絕緣層492和絕緣層496以及接墊494將用於將積體電路晶粒100接合到積體電路晶粒200。接墊494電耦合到暴露的穿孔466。接墊494可由與上述接墊104類似的材料和製程形成，於此不再贅述。絕緣層492和絕緣層496可由與上述絕緣層208相似的材料和製程形成，於此不再贅述。
在圖24中，積體電路晶粒100被接合至積體電路晶粒200。所述接合在以上圖2和圖3中描述，且在此不再贅述。在圖24中，積體電路晶粒100和積體電路晶粒200藉由接合接點300接合在一起。接合接點300可以是圖4A至圖4O中的接合接點配置300A至300O中的任意一個。
圖25繪示對圖24的結構的進一步製程。這兩個圖之間的製程類似於以上參考圖3至圖5所示和所述的製程，其中圖5是與圖25等同的中間步驟，於此不再贅述。接合的積體電路晶粒100和積體電路晶粒200被包封體499包封，以形成封裝500。
圖26繪示將封裝500貼附至載板基底400，這類似於以上在圖7和圖8中所描述的，且在此不再贅述。在圖26中，封裝500是以積體電路晶粒200比積體電路晶粒100更靠近載板基底400的狀態貼附至載板基底400。
圖26繪示對圖25的結構的進一步製程。這兩個圖之間的製程與參考圖9和圖10所示和所述的製程類似，其中圖10是與圖26等同的中間步驟，且在此不再贅述。封裝500被包封體502包封，且上表面被平坦化。
在圖26中，包封體502可經受研磨製程，以暴露出電連接件406和晶粒連接件488。在研磨製程之後，電連接件406的表面、晶粒連接件488的表面、絕緣層490的表面和包封體502的表面齊平。
圖27繪示對圖26的結構的進一步製程。這兩個圖之間的製程與參考圖10和圖11所示和所述的製程類似，其中圖11是與圖27等同的中間步驟，且在此不再贅述。在圖27中，重佈線結構410被形成為覆蓋並電耦合至穿孔（電連接件406）和晶粒連接件488。
圖28繪示對圖27的結構的進一步製程。這兩個圖之間的製程與參考圖12至圖14所示和所述的製程類似，其中圖14是與圖28等同的中間步驟，且在此不再贅述。在圖28中，第二封裝450被接合至圖27的封裝結構510。
可對圖28的封裝結構執行進一步的製程。舉例來說，可使用導電連接件416將圖28的封裝結構安裝到封裝基底。
圖29至圖34繪示根據一些實施例的另一封裝結構的剖視圖。圖29至圖34的實施例與圖22至圖28所示的實施例相似，不同之處在於，在本實施例中，積體電路晶粒100不包括位於積體電路晶粒100的主動側的接墊104上的晶粒連接件488及絕緣層490。晶粒連接件488和絕緣層490的移除需要額外的載板基底接合/脫離，以保護接墊104。關於本實施例與前述實施例類似的細節在此不再贅述。
圖29繪示如上圖24中所述的將積體電路晶粒100接合到積體電路晶粒200，於此不再贅述。所述接合在圖2和圖3中描述，且在此不再贅述。在圖29中，積體電路晶粒100和積體電路晶粒200藉由接合接點300接合在一起。接合接點300可以是圖4A至圖4O中的接合接點配置300A至300O中的任意一個。
圖30繪示對圖29的結構的進一步製程。這兩個圖之間的製程類似於參考圖3至圖8所示和所述的製程，其中圖8是與圖30等同的中間步驟，於此不再贅述。接合的積體電路晶粒100和積體電路晶粒200被包封體522包封，以形成封裝524。
圖30進一步繪示將封裝524貼附至載板基底400，此類似於以上在圖7和圖8中所描述的，且在此不再贅述。在圖30中，封裝524貼合至載板基底400時，積體電路晶粒100比積體電路晶粒200更靠近載板基底400。
圖31繪示對圖30的結構的進一步製程。這兩個圖之間的製程與參考圖9和圖10所示和所述的製程類似，其中圖10是與圖31等同的中間步驟，且在此不再贅述。封裝524被包封體526包封，且上表面被平坦化。
在圖31中，包封體526可經歷研磨製程，以暴露出電連接件406。在研磨製程之後，電連接件406的表面和包封體526的表面齊平。
圖32繪示圖31的結構的進一步製程。在圖32中，載板基底400脫離，且結構翻轉並接合至另一載板基底530。以上描述了脫離製程，且在此不再贅述。在圖32中，封裝524是以積體電路晶粒200比積體電路晶粒100更靠近載板基底530的狀態貼附至載板基底530。在圖32中，包封體526的暴露的表面、電連接件406的暴露的表面和接墊104的暴露的表面以及半導體基底102的暴露的表面齊平，且沒有經過研磨製程。
圖33繪示圖32的結構的進一步製程。這兩個圖之間的製程類似於參考圖10和11所示和所述的製程，其中圖11是與圖33等同的中間步驟，於此不再贅述。在圖33中，重佈線結構410和導電連接件416被形成為覆蓋且電耦合至穿孔（電連接件406）和接墊104。
圖34繪示對圖33的結構的進一步製程。這兩個圖之間的製程類似於參考圖12至圖14所示和所述的製程，其中圖14是與圖34等同的中間步驟，於此不再贅述。在圖34中，第二封裝450接合到圖33的封裝結構540。
可對圖34的封裝結構執行進一步的製程。舉例來說，可使用導電連接件416將圖34的封裝結構安裝到封裝基底。
圖35至圖38繪示根據一些實施例的另一封裝結構的剖視圖。圖35至圖38中的實施例與圖1至圖14所示的實施例相似，不同之處在於，在本實施例中，在積體電路晶粒100與積體電路晶粒200接合之後，在積體電路晶粒100的介電層與積體電路晶粒200的介電層之間存在間隙。關於本實施例與前述實施例類似的細節在此不再贅述。
圖35繪示如上圖2和圖3中所描述的將積體電路晶粒100接合到積體電路晶粒200，於此不再贅述。在圖35中，積體電路晶粒100和積體電路晶粒200藉由接合接點300接合在一起。本實施例中的接合接點300為圖4D中的接合接點配置300D。本實施例包括積體電路晶粒100的介電層與積體電路晶粒200的介電層之間的間隔間隙（standoff gap）。
圖36繪示對圖35的結構的進一步製程。在圖36中，在各種構件上形成密封層546，以密封積體電路晶粒100和積體電路晶粒200之間的接合界面。與未密封該結構中的接合界面相比，接合界面的密封可有助於本實施例的可靠度。密封層546可由與上述絕緣層208相似的材料和製程形成，且在此不再贅述。根據實施例，密封層可由聚合物材料形成。聚合物材料例如是聚對二甲苯、聚醯亞胺、BCB、PBO或其類似物。其形成方法可以是噴塗（spraying）、噴射（jetting）、塗佈或其類似製程。
圖37繪示對圖36的結構的進一步製程。這兩個圖之間的製程與參考圖5所示和所述的製程類似，其中圖5是與圖37等同的中間步驟，且在此不再贅述。接合的積體電路晶粒100和積體電路晶粒200被包封體548包封，以形成封裝。
圖38繪示對圖37的結構的進一步製程。這兩個圖之間的製程類似於以上參考圖5至圖14所示和所述的製程，其中圖14是與圖38等同的中間步驟，於此不再贅述。在圖38中，第二封裝450接合到封裝結構562，封裝結構562包括圖37的接合積體電路晶粒。
可對圖38的封裝結構執行進一步的製程。舉例來說，可使用導電連接件416將圖38的封裝結構安裝到封裝基底。
藉由利用焊料的混合接合技術（而不是典型的混合接合的銅與銅接合）來形成包括接合在一起的晶粒的PoP結構。混合接合的接合溫度可以顯著降低。此外，結構的接合墊可凹陷，以降低封裝結構的高度。晶粒可以面對面（F2F）或面對背（F2B）地接合在一起。舉例來說，在F2F接合配置中，晶粒的主動表面（面（face））接合在一起，而在F2B接合配置中，一個晶粒的主動表面接合到另一個晶粒的背表面。
在一個實施例中，封裝包括第一封裝結構。第一封裝結構包括具有第一主動側和第一背側的第一晶粒，第一主動側包括第一接合墊和第一絕緣層；第二晶粒，與第一晶粒接合，第二晶粒具有第二主動側和第二背側，第二主動側包括第二接合墊和第二絕緣層，第二晶粒的二主動側面向第一晶粒的第一主動側，第二絕緣層藉由介電質對介電質的接合鍵而與第一絕緣層接合；以及導電接合材料，與第一接合墊和第二接合墊接合，導電接合材料的回焊溫度低於第一接合墊的回焊溫度和第二接合墊的回焊溫度。
實施例可包括一個或多個以下特徵。在所述封裝中，第一絕緣層藉由相應的包括O-H鍵的接合鍵與第二絕緣層接合。在所述封裝中，第一接合墊凹進於第一絕緣層中。在上述封裝中，第一絕緣層和第二絕緣層均由聚合物形成。在上述封裝中，第一絕緣層和第二絕緣層均由氮化矽、氧化矽、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼摻雜磷矽玻璃（BPSG）或其組合形成。在上述封裝中，存在有空隙，空隙環繞導電接合材料以及位在第一接合墊和第二接合墊之間。在上述封裝中，第一封裝結構更包括第一晶粒的第一主動側上的導電接墊；與導電接墊電耦合的第一穿孔；第一密封體，位於第一晶粒上，且側向地包封第二晶粒和第一穿孔，第一穿孔延伸穿過第一包封體；以及第一重佈線結構，位於第二晶粒、第一穿孔和第一包封體上，第一重佈線電結構電耦合至第一穿孔。在上述封裝中，第一封裝結構更包括：鄰近第一晶粒的第二穿孔；以及第二包封體，包封第一晶粒、第一包封體和第二穿孔，第二穿孔延伸穿過第二包封體，第一重佈線結構電耦合到第二穿孔。在上述封裝中，更包括藉由第一導電連接件接合至第二穿孔的第二封裝結構。
在一個實施例中，一種方法包括形成第一封裝，包括藉由導電接合材料與第一絕緣層及第二絕緣層將第一晶粒的第一側接合到第二晶粒的第二側，第一側包括第一接合墊和第一絕緣層，第二側包括第二接合墊和第二絕緣層，第二晶粒的第二側面對第一晶粒的第一側，第二絕緣層藉由介電質對介電質的接合鍵與第一絕緣層接合，導電接合材料與第一接合墊和第二接合墊接合，導電接合材料的回焊溫度低於第一接合墊的回焊溫度和第二接合墊的回焊溫度。
實施例可能包括一個或多個以下特徵。在上述方法中，形成第一封裝更包括：在第一晶粒的第一側上的第三接合墊上形成第一導電柱，且第一導電柱電耦合至第三接合墊；以及藉由第一包封體包封第一晶粒、第二晶粒及第一導電柱。在上述方法中，其中形成第一封裝更包括：在載板基底上形成電連接件；將經接合的第一晶粒和第二晶粒貼附至載板基底並鄰近電連接件，第一晶粒鄰近載板基底；使用第二包封體包封經接合的第一晶粒和第二晶粒、第一包封體以及電連接件；以及在第一晶粒、第二晶粒、第一包封體、第二包封體以及電連接件上形成第一重佈線結構，第一重佈線結構電耦合至第一導電柱和電連接件。在上述方法中，更包括：移除載板基底；以及使用第一導電連接件將第二封裝接合至第一封裝的電連接件，第二封裝靠近第一晶粒。在上述方法中，形成第一封裝更包括：在第一晶粒中形成通孔；藉由第一包封體包封第一晶粒和第二晶粒；在載板基底上形成電連接件；將第一包封體以及經接合的第一晶粒和第二晶粒貼附至載板基底並鄰近電連接件，第二晶粒鄰近載板基底；藉由第二包封體包封經接合的第一晶粒和第二晶粒、第一包封體以及電連接件；平坦化第二包封體，其中在平坦化之後，電連接件和第一晶粒中的通孔暴露出來；在第一晶粒、第二晶粒、第一包封體、第二包封體以及電連接件上形成第一重佈線結構，第一重佈線結構電耦合至第一晶粒中的通孔和電連接件；以及在第一重佈線結構上形成導電連接件，導電連接件電耦合至第一重佈線結構。在上述方法中，其中第一絕緣層和第二絕緣層均由聚合物形成。在上述方法中，其中第一絕緣層和第二絕緣層均由氮化矽、氧化矽、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼摻雜磷矽玻璃（BPSG）或其組合形成。
在一個實施例中，一種方法包括在第一晶圓的第一側上形成第一絕緣層；圖案化第一絕緣層，以在第一絕緣層中形成凹陷；在凹陷和第一絕緣層上共形地沉積導電材料，導電材料的厚度小於第一絕緣層的厚度；移除位於凹陷外的部分導電材料，以形成第一接合墊，第一接合墊和第一絕緣層位於第一晶圓的第一晶粒的第一主動側上；形成第二晶粒，第二晶粒包括第二主動側，第二主動側包括第二接合墊和第二絕緣層；在第二接合墊上形成導電凸塊，導電凸塊的回焊溫度低於第一接合墊的回焊溫度和第二接合墊的回焊溫度；將第二接合墊上的導電凸塊接合至第一接合墊；以及將第二晶粒的第二絕緣層接合至第一絕緣層。
實施例可能包括一個或多個以下特徵。在上述方法中，更包括：在第一晶粒的第一主動側上的第三接合墊上形成第一導電柱，第一導電柱電耦合至第三接合墊；藉由第一包封體包封第一晶圓、第二晶粒和第一導電柱；以及將第一晶圓和第一包封體單體化，單體化形成第一封裝結構，第一封裝結構包括第一晶粒、第二晶粒、第一導電柱和第一包封體。在上述方法中，更包括：在載板基底上形成電連接件；將第一封裝結構貼附至載板基底並鄰近電連接件，第一晶粒鄰近載板基底；藉由第二包封體包封第一封裝結構和電連接件；以及在第一封裝結構、第二包封體和電連接件上形成第一重佈線結構，第一重佈線體結構電耦合至第一導電柱和電連接件。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本揭露的各個方面。所屬領域中的技術人員應知，他們可容易地使用本揭露做為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不悖離本揭露的精神及範圍，而且他們可在不悖離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
100、200‧‧‧積體電路晶粒
102、302、320‧‧‧半導體基底
104、206‧‧‧接墊
106‧‧‧導電柱
202‧‧‧基底
204、432、466‧‧‧穿孔
208、490、492、496‧‧‧絕緣層
300‧‧‧接合接點
300A、300B、300C、300D、300E、300F、300G、300H、300I、300J、300K、300L、300M、300N、300O‧‧‧配置
304、308、310、322、326、328、404、414‧‧‧介電層
306‧‧‧金屬化層
312‧‧‧接墊
312A‧‧‧晶種層
312B‧‧‧擴散阻擋層
312C‧‧‧導電材料層
324‧‧‧金屬化層
330‧‧‧接合墊
332‧‧‧層
334‧‧‧層
336‧‧‧空隙
340、342‧‧‧聚合物層
350‧‧‧界面
390、408、464、472、499、502、522、526、548‧‧‧包封體
392、470、500、524‧‧‧封裝
400、498、530‧‧‧載板基底
402‧‧‧離型層
406‧‧‧電連接件
410‧‧‧重佈線結構
412‧‧‧金屬化圖案
416‧‧‧連接件
420‧‧‧第一封裝
430‧‧‧基底
434、436‧‧‧接合墊
438‧‧‧導電連接件
440、440A、440B‧‧‧堆疊晶粒
442‧‧‧打線
444‧‧‧模塑材料
450‧‧‧第二封裝
476、510、540、562‧‧‧封裝結構
488‧‧‧晶粒連接件
494‧‧‧接墊
546‧‧‧密封層
T1、T2‧‧‧厚度
結合附圖閱讀以下詳細說明會最好地理解本揭露的各個方面。值得注意的是，根據業界的標準慣例，各種特徵並未按比例繪製。事實上，為了討論的清楚起見，各種特徵的尺寸可以任意增加或減小。 圖1至圖3、圖4A至圖4O以及圖5至圖14繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。 圖15至圖21繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。 圖22至圖28繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。 圖29至圖34繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。 圖35至圖38繪示根據一些實施例的用於形成封裝結構的製程期間的中間步驟的剖視圖。

Claims (20)

  1. 一種封裝，包括： 第一封裝結構，包括： 第一晶粒，具有第一主動側和第一背側，所述第一主動側包括第一接合墊和第一絕緣層； 第二晶粒，與所述第一晶粒接合，所述第二晶粒具有第二主動側和第二背側，所述第二主動側包括第二接合墊和第二絕緣層，所述第二晶粒的所述第二主動側面對所述第一晶粒的所述第一主動側，所述第二絕緣層藉由介電質對介電質的接合鍵而接合到所述第一絕緣層；以及 導電接合材料，與所述第一接合墊和所述第二接合墊接合，所述導電接合材料的回焊溫度低於所述第一接合墊的回焊溫度及所述第二接合墊的回焊溫度。
  2. 如申請專利範圍第1項所述的封裝，其中所述第一絕緣層藉由相應的包括O-H鍵的接合鍵與所述第二絕緣層接合。
  3. 如申請專利範圍第1項所述的封裝，其中所述第一接合墊凹進於所述第一絕緣層中。
  4. 如申請專利範圍第1項所述的封裝，其中所述第一絕緣層和所述第二絕緣層均由聚合物形成。
  5. 如申請專利範圍第1項所述的封裝，其中所述第一絕緣層和所述第二絕緣層均由氮化矽、氧化矽、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼摻雜磷矽玻璃（BPSG）或其組合形成。
  6. 如申請專利範圍第1項所述的封裝，其中存在有空隙，所述空隙環繞所述導電接合材料以及位在所述第一接合墊和所述第二接合墊之間。
  7. 如申請專利範圍第1項所述的封裝，其中所述第一封裝結構更包括： 導電接墊，位於所述第一晶粒的所述第一主動側上； 第一穿孔，電耦合至所述導電接墊； 第一包封體，位於所述第一晶粒上，且側向地包封所述第二晶粒和所述第一穿孔，所述第一穿孔延伸穿過所述第一包封體；以及 第一重佈線結構，位於所述第二晶粒、所述第一穿孔和所述第一包封體上方，所述第一重佈線結構電耦合至所述第一穿孔。
  8. 如申請專利範圍第7項所述的封裝，其中所述第一封裝結構更包括： 第二穿孔，鄰近所述第一晶粒；以及 第二包封體，包封所述第一晶粒、所述第一包封體和所述第二穿孔，所述第二穿孔延伸穿過所述第二包封體，所述第一重佈線結構電耦合至所述第二穿孔。
  9. 如申請專利範圍第8項所述的封裝，更包括： 第二封裝結構，藉由第一導電連接件接合至所述第二穿孔。
  10. 如申請專利範圍第1項所述的封裝，其中所述導電接合材料為焊料材料，其中所述第一接合墊和所述第二接合墊包括銅或鋁。
  11. 一種封裝的形成方法，包括： 形成第一封裝，包括： 藉由導電接合材料與第一絕緣層及第二絕緣層將第一晶粒的第一側接合到第二晶粒的第二側，所述第一側包括第一接合墊和所述第一絕緣層，所述第二側包括第二接合墊和所述第二絕緣層，所述第二晶粒的所述第二側面對所述第一晶粒的所述第一側，所述第二絕緣層藉由介電質對介電質的接合鍵與所述第一絕緣層接合，所述導電接合材料與所述第一接合墊和所述第二接合墊接合，所述導電接合材料的回焊溫度低於所述第一接合墊的回焊溫度和所述第二接合墊的回焊溫度。
  12. 如申請專利範圍第11項所述的封裝的形成方法，其中形成所述第一封裝更包括： 在所述第一晶粒的所述第一側上的第三接合墊上形成第一導電柱，且所述第一導電柱電耦合至所述第三接合墊；以及 藉由第一包封體包封所述第一晶粒、所述第二晶粒及所述第一導電柱。
  13. 如申請專利範圍第12項所述的封裝的形成方法，其中形成所述第一封裝更包括： 在載板基底上形成電連接件； 將經接合的所述第一晶粒和所述第二晶粒貼附至所述載板基底並鄰近所述電連接件，所述第一晶粒鄰近所述載板基底； 使用第二包封體包封經接合的所述第一晶粒和所述第二晶粒、所述第一包封體以及所述電連接件；以及 在所述第一晶粒、所述第二晶粒、所述第一包封體、所述第二包封體以及所述電連接件上形成第一重佈線結構，所述第一重佈線結構電耦合至所述第一導電柱和所述電連接件。
  14. 如申請專利範圍第13項所述的封裝的形成方法，更包括： 移除所述載板基底；以及 使用第一導電連接件將第二封裝接合至所述第一封裝的所述電連接件，所述第二封裝靠近所述第一晶粒。
  15. 如申請專利範圍第11項所述的封裝的形成方法，其中形成所述第一封裝更包括： 在所述第一晶粒中形成通孔； 藉由第一包封體包封所述第一晶粒和所述第二晶粒； 在載板基底上形成電連接件； 將所述第一包封體以及經接合的所述第一晶粒和所述第二晶粒貼附至所述載板基底並鄰近所述電連接件，所述第二晶粒鄰近所述載板基底； 藉由第二包封體包封經接合的所述第一晶粒和所述第二晶粒、所述第一包封體以及所述電連接件； 平坦化所述第二包封體，其中在所述平坦化之後，所述電連接件和所述第一晶粒中的所述通孔暴露出來； 在所述第一晶粒、所述第二晶粒、所述第一包封體、所述第二包封體以及所述電連接件上形成第一重佈線結構，所述第一重佈線結構電耦合至所述第一晶粒中的所述通孔和所述電連接件；以及 在所述第一重佈線結構上形成導電連接件，所述導電連接件電耦合至所述第一重佈線結構。
  16. 如申請專利範圍第11項所述的封裝的形成方法，其中所述第一絕緣層和所述第二絕緣層均由聚合物形成。
  17. 如申請專利範圍第11項所述的封裝的形成方法，其中所述第一絕緣層和所述第二絕緣層均由氮化矽、氧化矽、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼摻雜磷矽玻璃（BPSG）或其組合形成。
  18. 一種封裝的形成方法，包括： 在第一晶圓的第一側上形成第一絕緣層； 圖案化所述第一絕緣層，以在所述第一絕緣層中形成凹陷； 在所述凹陷和所述第一絕緣層上共形地沉積導電材料，所述導電材料的厚度小於所述第一絕緣層的厚度； 移除位於所述凹陷外的部分所述導電材料，以形成第一接合墊，所述第一接合墊和所述第一絕緣層位於所述第一晶圓的第一晶粒的第一主動側上； 形成第二晶粒，所述第二晶粒包括第二主動側，所述第二主動側包括第二接合墊和第二絕緣層； 在所述第二接合墊上形成導電凸塊，所述導電凸塊的回焊溫度低於所述第一接合墊的回焊溫度和所述第二接合墊的回焊溫度； 將所述第二接合墊上的所述導電凸塊接合至所述第一接合墊；以及 將所述第二晶粒的所述第二絕緣層接合至所述第一絕緣層。
  19. 如申請專利範圍第18項所述的封裝的形成方法，更包括： 在所述第一晶粒的所述第一主動側上的第三接合墊上形成第一導電柱，所述第一導電柱電耦合至所述第三接合墊； 藉由第一包封體包封所述第一晶圓、所述第二晶粒和所述第一導電柱；以及 將所述第一晶圓和所述第一包封體單體化，所述單體化形成第一封裝結構，所述第一封裝結構包括所述第一晶粒、所述第二晶粒、所述第一導電柱和所述第一包封體。
  20. 如申請專利範圍第19項所述的封裝的形成方法，更包括： 在載板基底上形成電連接件； 將所述第一封裝結構貼附至所述載板基底並鄰近所述電連接件，所述第一晶粒鄰近所述載板基底； 藉由第二包封體包封所述第一封裝結構和所述電連接件；以及 在所述第一封裝結構、所述第二包封體和所述電連接件上形成第一重佈線結構，所述第一重佈線體結構電耦合至所述第一導電柱和所述電連接件。
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