WO2022110936A1 - 一种功率元件封装结构及其制备方法 - Google Patents

一种功率元件封装结构及其制备方法 Download PDF

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Publication number
WO2022110936A1
WO2022110936A1 PCT/CN2021/114631 CN2021114631W WO2022110936A1 WO 2022110936 A1 WO2022110936 A1 WO 2022110936A1 CN 2021114631 W CN2021114631 W CN 2021114631W WO 2022110936 A1 WO2022110936 A1 WO 2022110936A1
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Prior art keywords
power
grooves
carrier
layer
thermally conductive
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PCT/CN2021/114631
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English (en)
French (fr)
Inventor
沈旭
冯仁国
王宏晨
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苏州矽锡谷半导体科技有限公司
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Publication of WO2022110936A1 publication Critical patent/WO2022110936A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L23/4012—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws for stacked arrangements of a plurality of semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/405—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands

Definitions

  • the invention relates to the technical field of semiconductor packaging, in particular to a power element packaging structure and a preparation method thereof.
  • the stacked package structure includes a PIP package structure and a POP stack structure.
  • the chips in the package are stacked on the substrate by gold wire bonding, and the same stack is bonded by gold wires to the substrate between the two stacks. , and then the entire package into a component is the PIP package structure.
  • the profile height of the PiP package structure is low, and the standard SMT circuit board assembly process can be used, and the assembly cost of a single device is low.
  • the purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art, and to provide a power component packaging structure and a preparation method thereof.
  • a preparation method of a power component packaging structure comprising the following steps:
  • the power component has an active surface and a non-active surface, the active surface of the power component has a conductive pad, and then the power component is The power element is mounted on the first carrier board in a manner that the active surface faces the first carrier board;
  • a mask layer is arranged on the first carrier, the mask has a plurality of openings arranged at intervals, and the openings expose the inactive surface of the power element, and then the mask layer is used etching the power element to form a plurality of first grooves arranged at intervals, wherein a plurality of the first grooves are arranged in a row, and the depth of the first groove located in the middle position of the row is the largest, while the depth of the first grooves located at both ends of the row is the smallest, and the depths of the plurality of first grooves gradually decrease from the intermediate position to each of the ends;
  • a second carrier is provided, the second carrier is bonded to the upper surface of the first encapsulation layer, the first carrier is removed, and a circuit board is arranged on the power element , the circuit board is electrically connected to the power element, and then a plurality of second grooves arranged at intervals are formed on the circuit board, and then a plurality of second heat conduction pillars are respectively formed in the plurality of second grooves , the top surfaces of the plurality of second thermally conductive pillars are located on the same horizontal plane, and then the second carrier plate is removed to form a first package assembly;
  • a radiator the upper surface of the radiator is provided with a plurality of accommodating cavities arranged in parallel, a strip groove is provided on the opposite two sides of each of the accommodating cavities, and then each accommodating cavity is provided with a strip groove.
  • a first package component is disposed in each of the accommodating cavities, and a plurality of the first thermally conductive pillars and a plurality of the second thermally conductive pillars are respectively embedded in the corresponding strip-shaped grooves, so as to forming a first power stack;
  • a conductive substrate is provided, and a first power stack is provided on both the upper surface and the lower surface of the conductive substrate, so that both the first power stacks are electrically connected to the conductive substrate, and then A second encapsulation layer is formed that encapsulates the conductive substrate and the two first power stacks.
  • an organic functional layer is first formed in the central area of the first carrier, and then an adhesive layer is formed on the surface of the first carrier and the organic functional layer, so that The adhesive force between the adhesive layer and the organic functional layer is less than the adhesive force between the adhesive layer and the first carrier board, and then the adhesive layer is bonded and arranged the power element.
  • the mask layer is a photoresist mask layer
  • the first groove is formed by wet etching or dry etching, and is located in the middle of the row.
  • the depth of the first groove is 40-60 microns, and the depth of the first grooves at both ends of the row is 10-30 microns.
  • the material of the first heat-conducting column is one or more of silver, copper, aluminum, iron, tin, and lead, and the first heat-conducting column is formed by chemical vapor deposition, Formed by one or more of physical vapor deposition, electroplating, and electroless plating.
  • the material of the first encapsulation layer is epoxy resin, and the ratio of the height of the protruding portion of the first thermal conductive column to the height of the first thermal conductive column is 0.2-0.4 .
  • the power element and the circuit board are electrically connected through conductive bumps, the depth of the second groove is 50-80 microns, and the second thermally conductive post Protruding from the surface of the circuit board, the ratio of the height of the protruding portion of the second thermal conductive column to the height of the second thermal conductive column is 0.15-0.3.
  • a thermally conductive insulating material is injected into the accommodating cavity, so that the thermally conductive insulating material fills the accommodating cavity a gap between the cavity and the first package assembly.
  • a thinning process is performed on the second encapsulation layer, so that the bottom surface of the heat sink is exposed.
  • the present invention also provides a power component packaging structure, which is prepared and formed by the above method.
  • the present invention has the following advantages:
  • the plurality of first grooves are arranged in a row, located in the inactive surface of the power element.
  • the depth of the first groove at the middle position of the row is the largest, and the depth of the first groove at the ends of the row is the smallest, and the depth from the middle position to each of the ends is the smallest.
  • each of the first grooves is gradually reduced; then a plurality of first heat-conducting pillars are respectively formed in the plurality of first grooves, and the top surfaces of the plurality of first heat-conducting pillars are located on the same horizontal plane; A plurality of second grooves arranged at intervals are formed on the circuit board, and then a plurality of second heat-conducting pillars are respectively formed in the plurality of second grooves, and the top surfaces of the plurality of second heat-conducting pillars are located on the same horizontal plane.
  • the arrangement of the above structure facilitates the heat dissipation of the power components, and the upper surface of the radiator is provided with a plurality of accommodating cavities arranged in parallel, and a strip-shaped groove is arranged on the opposite two sides of each of the accommodating cavities.
  • a first package component is disposed in each of the accommodating cavities, and a plurality of the first heat-conducting columns and a plurality of the second heat-conducting columns are respectively embedded in the corresponding strip-shaped grooves,
  • the power stack has excellent heat dissipation performance
  • the upper surface of the heat sink is provided with a plurality of accommodating cavities arranged in parallel, and each first package component is longitudinally embedded in the accommodating cavity , to improve the integration of the power component packaging structure.
  • FIGS 1-7 are schematic structural diagrams of the power component packaging structure in the manufacturing process of the present invention.
  • first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited by these terms. These terms are only used to distinguish semiconductor chips from one another.
  • a first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, a second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of the embodiments of the present invention.
  • this embodiment provides a method for manufacturing a power component packaging structure, and the manufacturing method includes the following steps:
  • a first carrier board 1 and a power element 2 are provided.
  • the power element 1 has an active surface and a non-active surface.
  • the active surface has conductive pads, and then the power element 2 is mounted on the first carrier board in a manner that the active surface of the power element 2 faces the first carrier board 1 .
  • an organic functional layer 11 is firstly formed in the central area of the first carrier 1 , and then an adhesive layer 12 is formed on the surfaces of the first carrier 1 and the organic functional layer 11 .
  • the adhesive force between the adhesive layer 12 and the organic functional layer 11 is smaller than the adhesive force between the adhesive layer 12 and the first carrier 1 , and then the adhesive The power element 2 is adhered on the adhesive layer 12 .
  • the first carrier board 1 may be one of a semiconductor substrate, a metal substrate, a ceramic substrate, a glass substrate or a plastic substrate.
  • the organic functional layer 11 can be specifically perfluorododecyltrichlorosilane, perfluorooctyltrichlorosilane, tetrahydrooctyltriethoxysilane or tetrahydrooctylmethyldichlorosilane.
  • the thickness of the organic functional layer 11 is preferably 10-20 nm. The arrangement of the organic functional layer 11 facilitates the subsequent stripping process.
  • a mask layer 3 is then disposed on the first carrier 1 , the mask layer 3 has a plurality of openings arranged at intervals, and the openings expose the The non-active surface of the power element 2, and then the power element 2 is etched by using the mask layer 3 to form a plurality of first grooves 21 arranged at intervals, wherein the plurality of the first grooves 21 are arranged in a In a row, the depth of the first groove 21 at the middle position of the row is the largest, and the depth of the first groove 21 at both ends of the row is the smallest. The depths of the plurality of first grooves of each of the end portions gradually decrease.
  • the mask layer 3 is a photoresist mask layer
  • the first groove 21 is formed by wet etching or dry etching, and is located in all the middle positions of the rows.
  • the depth of the first grooves 21 is 40-60 ⁇ m, and the depth of the first grooves 21 at both ends of the row is 10-30 ⁇ m. More preferably, the depths of the first grooves 21 located in the middle of the row are 40 microns, 45 microns, 50 microns, 55 microns, 60 microns, and the first grooves 21 located at both ends of the row
  • the depths of the grooves 21 are 10 microns, 15 microns, 20 microns, 25 microns, 30 microns.
  • the photoresist mask layer 3 is formed by coating a photoresist solution on the first carrier 1, and performing an exposure and development process, and then using the photoresist mask The layer 3 performs wet etching on the power element 2 to form a plurality of the first grooves 21 respectively.
  • a plurality of first heat-conducting pillars 4 are respectively formed in the plurality of first grooves 21 , and the top surfaces of the plurality of first heat-conducting pillars 4 are located at the same level.
  • the material of the first heat-conducting column 4 is one or more of silver, copper, aluminum, iron, tin, and lead, and the first heat-conducting column 4 is deposited by chemical vapor deposition , physical vapor deposition, electroplating, and one or more processes of electroless plating.
  • the material of the first thermal conductive column 4 is copper or aluminum, and is formed by an evaporation process.
  • step (4) a first encapsulation layer 5 is then disposed on the first carrier board 1 , and a plurality of the first thermally conductive pillars 4 protrude from the first encapsulation layer 1 . upper surface.
  • the material of the first encapsulation layer 5 is epoxy resin, and the ratio of the height of the protruding portion of the first thermal conductive column 4 to the height of the first thermal conductive column 4 is 0.2 -0.4.
  • the ratio of the height of the protruding portion of the first thermal conductive column 4 to the height of the first thermal conductive column 4 is 0.2, 0.25, 0.3, 0.35 or 0.4.
  • a first encapsulation layer may be formed on the first carrier, and then a photoresist mask layer may be formed on the first encapsulation layer.
  • the photoresist mask layer a plurality of openings are arranged at intervals, the openings expose the first encapsulation layer, and then the first encapsulation layer and the power element are etched using the photoresist mask layer to form in the power element
  • a plurality of grooves arranged at intervals, wherein a plurality of the grooves are arranged in a row, the grooves located in the middle of the row have the largest depth, and the grooves located at both ends of the row and the depth of the plurality of grooves decreases gradually from the intermediate position to each of the ends, and then a thermally conductive material is deposited in the grooves to form a first thermally conductive column, and the first thermally conductive column is formed.
  • a thermally conductive post protrudes from the first encapsulation layer, and then the photoresist mask layer is removed to
  • a second carrier 6 is provided, and the second carrier 6 is bonded to the upper surface of the first encapsulation layer 5 , and then the first carrier is removed.
  • the power element 2 and the circuit board 7 are electrically connected through conductive bumps, the depth of the second groove 71 is 50-80 microns, the second The thermally conductive post 8 protrudes from the surface of the circuit board 7 , and the ratio of the height of the protruding portion of the second thermally conductive post 8 to the height of the second thermally conductive post 8 is 0.15-0.3.
  • the conductive bumps may be solder balls, and the depths of the second grooves 71 are preferably 50 microns, 55 microns, 60 microns, 65 microns, 70 microns, 75 microns and 80 microns.
  • the ratio of the height of the protruding portion of the second thermally conductive pillar 8 to the height of the second thermally conductive pillar 8 is preferably 0.15, 0.2, 0.25, 0.3.
  • the middle area of the second carrier board 6 has an opening passing through the second carrier board 6, so that the plurality of the first thermally conductive pillars 4 can pass through the second carrier board 6 , a resin protection layer may also be provided between the power element 2 and the circuit board 7 , and the resin protection layer may protect the conductive bumps.
  • an organic functional layer (not shown) is formed in the central area of the second carrier 6 , and then an adhesive layer is formed on the surface of the second carrier 6 and the organic functional layer (not shown), the adhesive force between the adhesive layer and the organic functional layer is smaller than the adhesive force between the adhesive layer and the second carrier substrate, and then the adhesive The adhesive layer is bonded to the upper surface of the first encapsulation layer.
  • the second carrier 6 may be one of a semiconductor substrate, a metal substrate, a ceramic substrate, a glass substrate or a plastic substrate.
  • the organic functional layer may specifically be perfluorododecyltrichlorosilane, perfluorooctyltrichlorosilane, tetrahydrooctyltriethoxysilane or tetrahydrooctylmethyldichlorosilane, and the organic functional layer may be
  • the thickness of the functional layer is preferably 10-20 nm. The arrangement of the organic functional layer facilitates the subsequent stripping process.
  • the specific step of peeling off the first carrier board 1 is: cutting a part of the first encapsulation layer 5 and a part of the first carrier board 1 , so that the first carrier board 1 and the adhesive The adhesive area of the adhesive layer 12 is completely removed, and since the adhesive force between the adhesive adhesive layer 12 and the organic functional layer 11 is small, the first layer can be peeled off under the action of a small external force.
  • a carrier substrate 1, so the first carrier substrate 1 can be peeled off without using a CMP process, which effectively reduces the cost of the peeling process.
  • the material of the second heat-conducting column 8 is one or more of silver, copper, aluminum, iron, tin, and lead, and the second heat-conducting column 8 is deposited by chemical vapor deposition or physical vapor deposition. , electroplating, and one or more of electroless plating.
  • the material of the second thermal conductive column 8 is copper or aluminum, and is formed by an evaporation process.
  • a radiator 9 is provided.
  • the upper surface of the radiator 9 is provided with a plurality of accommodating cavities 91 arranged in parallel.
  • a strip-shaped groove is arranged on both sides of the cavities, and then a first package component is arranged in each of the accommodating cavities 91, so that a plurality of the first thermally conductive pillars 4 and a plurality of the first packaging components are arranged.
  • the two thermally conductive pillars 8 are respectively embedded in the corresponding strip-shaped grooves to form a first power stack.
  • a thermally conductive insulating material is injected into the accommodating cavity 91, so that the thermally conductive insulating material fills the accommodating cavity 91 and the first package component to seal the first package component, effectively eliminate the gap between the first package component and the accommodating cavity 91, and effectively improve the heat dissipation performance.
  • heat dissipation channels there are mutually communicating heat dissipation channels between the adjacent accommodating cavities 91 in the heat sink 9 and one side of the heat sink, so that heat dissipation fluid can circulate in the heat dissipation channels, so
  • the two sides of the radiator 9 are provided with an injection port and a discharge port for the cooling fluid.
  • step (7) a conductive substrate 10 is provided, and a first power stack is provided on both the upper surface and the lower surface of the conductive substrate 10 , so that two first power stacks are provided.
  • the power stacks are all electrically connected to the conductive substrate 10 , and then a second packaging layer 50 is formed.
  • the second packaging layer 50 wraps the conductive substrate 10 and the two first power stacks.
  • the second encapsulation layer 50 is thinned so that the bottom surface of the heat sink 9 is exposed, and the second encapsulation layer 50 may be epoxy resin.
  • the present invention also provides a power component packaging structure, which is prepared and formed by the above method.
  • the plurality of first grooves are arranged in a row, located in the inactive surface of the power element.
  • the depth of the first groove at the middle position of the row is the largest, and the depth of the first groove at the ends of the row is the smallest, and the depth from the middle position to each of the ends is the smallest.
  • each of the first grooves is gradually reduced; then a plurality of first heat-conducting pillars are respectively formed in the plurality of first grooves, and the top surfaces of the plurality of first heat-conducting pillars are located on the same horizontal plane; A plurality of second grooves arranged at intervals are formed on the circuit board, and then a plurality of second heat-conducting pillars are respectively formed in the plurality of second grooves, and the top surfaces of the plurality of second heat-conducting pillars are located on the same horizontal plane.
  • the arrangement of the above structure facilitates the heat dissipation of the power components, and the upper surface of the radiator is provided with a plurality of accommodating cavities arranged in parallel, and a strip-shaped groove is arranged on the opposite two sides of each of the accommodating cavities.
  • a first package component is disposed in each of the accommodating cavities, and a plurality of the first heat-conducting columns and a plurality of the second heat-conducting columns are respectively embedded in the corresponding strip-shaped grooves,
  • the power stack has excellent heat dissipation performance
  • the upper surface of the heat sink is provided with a plurality of accommodating cavities arranged in parallel, and each first package component is longitudinally embedded in the accommodating cavity , to improve the integration of the power component packaging structure.
  • the invention provides a power element packaging structure and a preparation method thereof.
  • Embodiment 1 A preparation method of a power component packaging structure, comprising the following steps:
  • the power component has an active surface and a non-active surface, the active surface of the power component has a conductive pad, and then the power component is The power element is mounted on the first carrier board in a manner that the active surface faces the first carrier board;
  • a mask layer is arranged on the first carrier, the mask has a plurality of openings arranged at intervals, and the openings expose the inactive surface of the power element, and then the mask layer is used etching the power element to form a plurality of first grooves arranged at intervals, wherein a plurality of the first grooves are arranged in a row, and the depth of the first groove located in the middle position of the row is the largest, while the depth of the first grooves located at both ends of the row is the smallest, and the depths of the plurality of first grooves gradually decrease from the intermediate position to each of the ends;
  • a second carrier is provided, the second carrier is bonded to the upper surface of the first encapsulation layer, the first carrier is removed, and a circuit board is arranged on the power element , the circuit board is electrically connected to the power element, and then a plurality of second grooves arranged at intervals are formed on the circuit board, and then a plurality of second heat conduction pillars are respectively formed in the plurality of second grooves , the top surfaces of the plurality of second thermally conductive pillars are located on the same horizontal plane, and then the second carrier plate is removed to form a first package assembly;
  • a radiator the upper surface of the radiator is provided with a plurality of accommodating cavities arranged in parallel, a strip-shaped groove is provided on the opposite two sides of each of the accommodating cavities, and then each accommodating cavity is provided with a strip groove.
  • a first package component is disposed in each of the accommodating cavities, and a plurality of the first thermally conductive pillars and a plurality of the second thermally conductive pillars are respectively embedded in the corresponding strip-shaped grooves, so as to forming a first power stack;
  • a conductive substrate is provided, and a first power stack is provided on both the upper surface and the lower surface of the conductive substrate, so that both the first power stacks are electrically connected to the conductive substrate, and then A second encapsulation layer is formed that encapsulates the conductive substrate and the two first power stacks.
  • Embodiment 2 In the step 1), firstly, an organic functional layer is formed in the central area of the first carrier, and then an adhesive layer is formed on the surface of the first carrier and the organic functional layer, The adhesive force between the adhesive adhesive layer and the organic functional layer is smaller than the adhesive force between the adhesive adhesive layer and the first carrier board, and then the adhesive adhesive layer is bonded Set the power element.
  • Embodiment 3 In the step 2), the mask layer is a photoresist mask layer, the first groove is formed by wet etching or dry etching, and is located in the middle of the row The depth of the first groove is 40-60 microns, and the depth of the first grooves located at both ends of the row is 10-30 microns.
  • Embodiment 4 In the step 3), the material of the first thermal conductive column is one or more of silver, copper, aluminum, iron, tin, and lead, and the first thermal conductive column is deposited by chemical vapor deposition. , physical vapor deposition, electroplating, and one or more processes of electroless plating.
  • Embodiment 5 In the step 4), the material of the first encapsulation layer is epoxy resin, and the ratio of the height of the protruding portion of the first thermal conductive column to the height of the first thermal conductive column is 0.2- 0.4.
  • Embodiment 6 In the step 5), the power element and the circuit board are electrically connected through conductive bumps, the depth of the second groove is 50-80 microns, and the second heat conduction The post protrudes from the surface of the circuit board, and the ratio of the height of the protruding portion of the second heat conductive post to the height of the second heat conductive post is 0.15-0.3.
  • Embodiment 7 In the step 6), after the first packaging component is placed in the accommodating cavity, a thermally conductive insulating material is injected into the accommodating cavity, so that the thermally conductive insulating material fills the accommodating cavity. a gap between the cavity and the first package assembly.
  • Embodiment 8 in the step 7), thinning processing is performed on the second encapsulation layer, so that the bottom surface of the heat sink is exposed.
  • Embodiment 9 The present invention also provides a power component packaging structure, which is prepared and formed by the above method.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种功率元件封装结构及其制备方法，该方法包括以下步骤：将功率元件(2)安装在第一载板(1)上，在功率元件上形成多个间隔设置的第一凹槽(21)，在多个第一凹槽中分别形成多个第一导热柱(4)，接着设置第一封装层(5)，在功率元件上设置一电路板(7)，在电路板上形成多个间隔设置的第二凹槽(71)，并在多个第二凹槽中分别形成多个第二导热柱(8)，以形成第一封装组件，在散热器(9)的上表面设置多个平行排列的容置腔(91)，在每个容置腔中均设置一第一封装组件，以形成第一功率堆叠件，在导电基板(10)的上表面和下表面均设置一第一功率堆叠件，接着形成一第二封装层(50)，第二封装层包裹导电基板以及两个第一功率堆叠件。

Description

一种功率元件封装结构及其制备方法 技术领域
本发明涉及半导体封装技术领域，特别是涉及一种功率元件封装结构及其制备方法。
背景技术
在现有的堆叠封装结构中，元器件内芯片的堆叠大部分是采用金线键合的方式,堆叠层数可以从2层到8层。堆叠封装结构包括PIP封装结构以及POP堆叠结构，其中，在PIP封装结构中，封装内芯片通过金线键合堆叠到基板上,同样的堆叠通过金线再将两个堆叠之间的基板键合,然后整个封装成一个元件便是PIP封装结构。PiP封装结构的外形高度较低，可以采用标准的SMT电路板装配工艺，单个器件的装配成本较低。但由于在封装之前单个芯片不可以单独测试，所以总成本会高；在POP堆叠结构中，在底部封装结构上面再放置封装结构，外形高度会稍微高些，但是装配前各个封装结构可以单独测试，保障了更高的良品率，总的堆叠装配成本可降至最低。如何改善现有的堆叠封装结构，以提高堆叠封装结构的综合性能。
发明内容
本发明的目的是克服上述现有技术的不足，提供一种功率元件封装结构及其制备方法。
为实现上述目的，本发明采用的技术方案是：
一种功率元件封装结构的制备方法，包括以下步骤：
(1)提供一第一载板以及一功率元件，所述功率元件具有有源面和非有源面，所述功率元件的所述有源面具有导电焊盘，接着以所述功率元件的有源面朝向所述第一载板的方式将所述功率元件安装在所述第一载板上；
(2)接着在所述第一载板上设置一掩膜层，所述掩膜具有间隔设置多个开口，所述开口暴露所述功率元件的非有源面，接着利用所述掩膜层刻蚀所述功率元件以形成多个间隔设置的第一凹槽，其中，多个所述第一凹槽排列成一行，位于所述行的中间位置的所述第一凹槽的深度最大，而位于所述行的两端部的所述第一凹槽的深度最小，且从所述中间位置到每个所述端部的多个所述第一凹槽的深度逐渐减小；
(3)接着在多个所述第一凹槽中分别形成多个第一导热柱，多个所述第一导热柱的顶面位于同一水平面；
(4)接着在所述第一载板上设置第一封装层，多个所述第一导热柱突出于所述第一封装层的上表面；
(5)接着提供一第二载板，将所述第二载板接合至所述第一封装层的上表面，接着去除所述第一载板，接着在所述功率元件上设置一电路板，所述电路板电连接至所述功率元件，接着在所述电路板上形成多个间隔设置的第二凹槽，接着在多个所述第二凹槽中分别形成多个第二导热柱，多个所述第二导热柱的顶面位于同一水平面，接着去除所述第二载板，以形成第一封装组件；
(6)提供一散热器，所述散热器的上表面设置多个平行排列的容置腔，在每个所述容置腔的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔中均设置一所述第一封装组件，并使得多个所述第一导热柱和多个所述第二导热柱分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件；
(7)提供一导电基板，在所述导电基板的上表面和下表面均设置一所述第一功率堆叠件，使得两个所述第一功率堆叠件均与所述导电基板电连接，接着形成一第二封装层，所述第二封装层包裹所述导电基板以及两个所述第一功率堆叠件。
作为优选，在所述步骤1)中，首先在所述第一载板的中心区域形成一有机功能层，接着在所述第一载板以及所述有机功能层表面形成粘合胶层，所述粘合胶层与所述有机功能层的之间粘附力小于所述粘合胶层与所述第一载板之间的粘附力，接着在所述粘合胶层上粘结设置所述功率元件。
作为优选，在所述步骤2)中，所述掩膜层为光刻胶掩膜层，所述第一凹槽通过湿法刻蚀或干法刻蚀形成，位于所述行的中间位置的所述第一凹槽的深度为40-60微米，位于所述行的两端部的所述第一凹槽的深度为10-30微米。
作为优选，在所述步骤3)中，所述第一导热柱的材料为银、铜、铝、铁、锡、铅中的一种或多种，所述第一导热柱通过化学气相沉积、物理气相沉积、电镀以及化学镀中的一种或多种工艺形成。
作为优选，在所述步骤4)中，所述第一封装层的材料为环氧树脂，所述第一导热柱的突出部分的高度与所述第一导热柱的高度的比值为0.2-0.4。
作为优选，在所述步骤5)中，所述功率元件与所述电路板之间通过导电凸块进行电连接，所述第二凹槽的深度为50-80微米，所述第二导热柱突 出于所述电路板的表面，所述第二导热柱的突出部分的高度与所述第二导热柱的高度的比值为0.15-0.3。
作为优选，在所述步骤6)中，将所述第一封装组件置于所述容置腔之后，在所述容置腔中注入导热绝缘材料，使得所述导热绝缘材料充满所述容置腔与所述第一封装组件之间的间隙。
作为优选，在所述步骤7)中，对所述第二封装层进行减薄处理，使得所述散热器的底面露出。
本发明还提出一种功率元件封装结构，其采用上述方法制备形成的。
本发明与现有技术相比具有下列优点：
在本发明的功率元件封装结构的制备过程中，通过在所述功率元件的非有源面形成多个间隔设置的第一凹槽，多个所述第一凹槽排列成一行，位于所述行的中间位置的所述第一凹槽的深度最大，而位于所述行的两端部的所述第一凹槽的深度最小，且从所述中间位置到每个所述端部的多个所述第一凹槽的深度逐渐减小；接着在多个所述第一凹槽中分别形成多个第一导热柱，多个所述第一导热柱的顶面位于同一水平面；接着在所述电路板上形成多个间隔设置的第二凹槽，接着在多个所述第二凹槽中分别形成多个第二导热柱，多个所述第二导热柱的顶面位于同一水平面，上述结 构的设置便于功率元件散热，而散热器的上表面设置多个平行排列的容置腔，在每个所述容置腔的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔中均设置一所述第一封装组件，并使得多个所述第一导热柱和多个所述第二导热柱分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件，该功率堆叠件具有优异的散热性能，且该散热器的上表面设置多个平行排列的容置腔，每个第一封装组件纵向嵌入到所述容置腔中，提高了功率元件封装结构的集成度。
附图说明
图1-图7为本发明的功率元件封装结构的制备过程中的结构示意图。
具体实施方式
为了更好的理解本发明的技术方案，下面结合附图对本发明实施例进行详细描述。
应当明确，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形 式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
应当理解，本文中使用的术语“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应当理解，尽管在本发明实施例中可能采用术语第一、第二等来描述半导体芯片，但这些半导体芯片不应限于这些术语。这些术语仅用来将半导体芯片彼此区分开。例如，在不脱离本发明实施例范围的情况下，第一半导体芯片也可以被称为第二半导体芯片，类似地，第二半导体芯片也可以被称为第一半导体芯片。
请参阅图1～图7。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1～图7所示，本实施例提供一种功率元件封装结构的制备方法，该制备方法包括以下步骤：
首先如图1所示，在步骤(1)中，提供一第一载板1以及一功率元件2，所述功率元件1具有有源面和非有源面，所述功率元件2的所述有源面具有导电焊盘，接着以所述功率元件2的有源面朝向所述第一载板1的方式将所述功率元件2安装在所述第一载板上。
在所述步骤1)中，首先在所述第一载板1的中心区域形成一有机功能层11，接着在所述第一载板1以及所述有机功能层11表面形成粘合胶层12，所述粘合胶层12与所述有机功能层11的之间粘附力小于所述粘合胶层12与所述第一载板1之间的粘附力，接着在所述粘合胶层12上粘结设置所述功率元件2。
在本实施例中，所述第一载板1可以为半导体基板、金属基板、陶瓷基板、玻璃基板或塑料基板中的一种。所述有机功能层11具体可以为全氟十二烷基三氯硅烷、全氟辛烷基三氯硅烷、四氢辛基三乙氧基硅烷或四氢辛基甲基二氯硅烷，所述有机功能层11的厚度优选为10-20纳米。所述有机功能层11的设置便于后续剥离工艺的进行。
接着如图2所示，在步骤(2)中，接着在所述第一载板1上设置一掩膜层3，所述掩膜层3具有间隔设置多个开口，所述开口暴露所述功率元件2的非有源面，接着利用所述掩膜层3刻蚀所述功率元件2以形成多个间隔 设置的第一凹槽21，其中，多个所述第一凹槽21排列成一行，位于所述行的中间位置的所述第一凹槽21的深度最大，而位于所述行的两端部的所述第一凹槽21的深度最小，且从所述中间位置到每个所述端部的多个所述第一凹槽的深度逐渐减小。
在所述步骤2)中，所述掩膜层3为光刻胶掩膜层，所述第一凹槽21通过湿法刻蚀或干法刻蚀形成，位于所述行的中间位置的所述第一凹槽21的深度为40-60微米，位于所述行的两端部的所述第一凹槽21的深度为10-30微米。更优选的，位于所述行的中间位置的所述第一凹槽21的深度为40微米、45微米、50微米、55微米、60微米，位于所述行的两端部的所述第一凹槽21的深度为10微米、15微米、20微米、25微米、30微米。
在具体的实施例中，通过在所述第一载板1上涂覆光刻胶溶液，进行通过曝光显影工艺以形成所述光刻胶掩膜层3，进而利用所述光刻胶掩膜层3对所述功率元件2进行湿法刻蚀处理，以分别形成多个所述第一凹槽21。
接着如图3所示，在步骤(3)中，接着在多个所述第一凹槽21中分别形成多个第一导热柱4，多个所述第一导热柱4的顶面位于同一水平面。其中，在所述步骤3)中，所述第一导热柱4的材料为银、铜、铝、铁、锡、铅中的一种或多种，所述第一导热柱4通过化学气相沉积、物理气相沉积、 电镀以及化学镀中的一种或多种工艺形成。在具体的实施例中，在具体的实施例中，所述第一导热柱4的材料为铜或铝，且通过蒸镀工艺形成。
接着如图4所示，在步骤(4)中，接着在所述第一载板1上设置第一封装层5，多个所述第一导热柱4突出于所述第一封装层1的上表面。
其中，在所述步骤4)中，所述第一封装层5的材料为环氧树脂，所述第一导热柱4的突出部分的高度与所述第一导热柱4的高度的比值为0.2-0.4。
在优选的实施例中，所述第一导热柱4的突出部分的高度与所述第一导热柱4的高度的比值为0.2、0.25、0.3、0.35或0.4，通过优化所述第一导热柱4的突出部分的高度与所述第一导热柱4的高度的比值，有效确保了所述第一导热柱4的稳定性和导热性能。
在其它的实施例中，还可以在所述第一载板上先形成一第一封装层，接着在所述第一封装层上形成光刻胶掩膜层，所述光刻胶掩膜层具有间隔设置多个开口，所述开口暴露所述第一封装层，接着利用所述光刻胶掩膜层刻蚀所述第一封装层和所述功率元件，以在所述功率元件中形成多个间隔设置的凹槽，其中，多个所述凹槽排列成一行，位于所述行的中间位置的所述凹槽的深度最大，而位于所述行的两端部的所述凹槽的深度最小， 且从所述中间位置到每个所述端部的多个所述凹槽的深度逐渐减小，接着在所述凹槽中沉积导热材料以形成第一导热柱，所述第一导热柱突出于所述第一封装层，进而去除所述光刻胶掩膜层，以得到与所述步骤4类似的结构。
接着如图5所示，在步骤(5)中，接着提供一第二载板6，将所述第二载板6接合至所述第一封装层5的上表面，接着去除所述第一载板1，接着在所述功率元件2上设置一电路板7，所述电路板7电连接至所述功率元件2，接着在所述电路板7上形成多个间隔设置的第二凹槽71，接着在多个所述第二凹槽71中分别形成多个第二导热柱8，多个所述第二导热柱8的顶面位于同一水平面，接着去除所述第二载板6，以形成第一封装组件。
其中，在所述步骤5)中，所述功率元件2与所述电路板7之间通过导电凸块进行电连接，所述第二凹槽71的深度为50-80微米，所述第二导热柱8突出于所述电路板7的表面，所述第二导热柱8的突出部分的高度与所述第二导热柱8的高度的比值为0.15-0.3。在优选的实施例中，所述导电凸块可以为焊球，所述第二凹槽71的深度优选为50微米、55微米、60微米、65微米、70微米、75微米、80微米。所述第二导热柱8的突出部分的高度与所述第二导热柱8的高度的比值优选为0.15、0.2、0.25、0.3，通 过优化所述第二导热柱8的突出部分的高度与所述第二导热柱8的高度的比值，有效确保了所述第二导热柱8的稳定性和导热性能。
在所述步骤5)中，所述第二载板6的中间区域具有贯穿所述第二载板6的开口，以便于多个所述第一导热柱4穿过所述第二载板6，在所述功率元件2与所述电路板7之间还可以具有树脂保护层，该树脂保护层可以保护所述导电凸块。
在具体的实施例中，在所述第二载板6的中心区域形成一有机功能层(未图示)，接着在所述第二载板6以及所述有机功能层表面形成粘合胶层(未图示)，所述粘合胶层与所述有机功能层的之间粘附力小于所述粘合胶层与所述第二载体基板之间的粘附力，接着将所述粘合胶层粘结至所述所述第一封装层的上表面。
在本实施例中，所述第二载板6可以为半导体基板、金属基板、陶瓷基板、玻璃基板或塑料基板中的一种。所述有机功能层具体可以为全氟十二烷基三氯硅烷、全氟辛烷基三氯硅烷、四氢辛基三乙氧基硅烷或四氢辛基甲基二氯硅烷，所述有机功能层的厚度优选为10-20纳米。所述有机功能层的设置便于后续剥离工艺的进行。
在具体的实施例中，剥离所述第一载板1的具体步骤为：切割部分所述第一封装层5和部分所述第一载板1，使得所述第一载板1与粘合胶层12的粘合区域被完全去除，且由于所述粘合胶层12与所述有机功能层11的之间粘附力较小，进而在较小的外力作用下即可剥离所述第一载体基板1，因而不使用CMP工艺即可剥离第一载体基板1，有效降低了剥离工艺的成本。
在本实施例中，所述第二导热柱8的材料为银、铜、铝、铁、锡、铅中的一种或多种，所述第二导热柱8通过化学气相沉积、物理气相沉积、电镀以及化学镀中的一种或多种工艺形成。在具体的实施例中，在具体的实施例中，所述第二导热柱8的材料为铜或铝，且通过蒸镀工艺形成。
接着如图6所示，在步骤(6)中，提供一散热器9，所述散热器9的上表面设置多个平行排列的容置腔91，在每个所述容置腔91的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔91中均设置一所述第一封装组件，并使得多个所述第一导热柱4和多个所述第二导热柱8分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件。
在所述步骤6)中，将所述第一封装组件置于所述容置腔91之后，在所述容置腔91中注入导热绝缘材料，使得所述导热绝缘材料充满所述容置 腔91与所述第一封装组件之间的间隙，以密封所述第一封装组件，有效消除所述第一封装组件与所述容置腔91之间的空隙，有效提高了散热性能。
在具体的实施例中，所述散热器9中相邻的容置腔91之间以及所述散热器的一侧具有相互连通的散热通道，进而在所述散热通道中可以流通散热流体，所述散热器9的两侧则具有散热流体的注入口和排出口。
接着如图7所示，在步骤(7)中，提供一导电基板10，在所述导电基板10的上表面和下表面均设置一所述第一功率堆叠件，使得两个所述第一功率堆叠件均与所述导电基板10电连接，接着形成一第二封装层50，所述第二封装层50包裹所述导电基板10以及两个所述第一功率堆叠件。
在所述步骤7)中，对所述第二封装层50进行减薄处理，使得所述散热器9的底面露出，且所述第二封装层50可以为环氧树脂。
如图7所示，本发明还提出一种功率元件封装结构，其采用上述方法制备形成的。
在本发明的功率元件封装结构的制备过程中，通过在所述功率元件的非有源面形成多个间隔设置的第一凹槽，多个所述第一凹槽排列成一行，位于所述行的中间位置的所述第一凹槽的深度最大，而位于所述行的两端部的所述第一凹槽的深度最小，且从所述中间位置到每个所述端部的多个 所述第一凹槽的深度逐渐减小；接着在多个所述第一凹槽中分别形成多个第一导热柱，多个所述第一导热柱的顶面位于同一水平面；接着在所述电路板上形成多个间隔设置的第二凹槽，接着在多个所述第二凹槽中分别形成多个第二导热柱，多个所述第二导热柱的顶面位于同一水平面，上述结构的设置便于功率元件散热，而散热器的上表面设置多个平行排列的容置腔，在每个所述容置腔的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔中均设置一所述第一封装组件，并使得多个所述第一导热柱和多个所述第二导热柱分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件，该功率堆叠件具有优异的散热性能，且该散热器的上表面设置多个平行排列的容置腔，每个第一封装组件纵向嵌入到所述容置腔中，提高了功率元件封装结构的集成度。
本发明提出一种功率元件封装结构及其制备方法。
实施例1：一种功率元件封装结构的制备方法，包括以下步骤：
(1)提供一第一载板以及一功率元件，所述功率元件具有有源面和非有源面，所述功率元件的所述有源面具有导电焊盘，接着以所述功率元件的有源面朝向所述第一载板的方式将所述功率元件安装在所述第一载板上；
(2)接着在所述第一载板上设置一掩膜层，所述掩膜具有间隔设置多个开口，所述开口暴露所述功率元件的非有源面，接着利用所述掩膜层刻蚀所述功率元件以形成多个间隔设置的第一凹槽，其中，多个所述第一凹槽排列成一行，位于所述行的中间位置的所述第一凹槽的深度最大，而位于所述行的两端部的所述第一凹槽的深度最小，且从所述中间位置到每个所述端部的多个所述第一凹槽的深度逐渐减小；
(3)接着在多个所述第一凹槽中分别形成多个第一导热柱，多个所述第一导热柱的顶面位于同一水平面；
(4)接着在所述第一载板上设置第一封装层，多个所述第一导热柱突出于所述第一封装层的上表面；
(5)接着提供一第二载板，将所述第二载板接合至所述第一封装层的上表面，接着去除所述第一载板，接着在所述功率元件上设置一电路板，所述电路板电连接至所述功率元件，接着在所述电路板上形成多个间隔设置的第二凹槽，接着在多个所述第二凹槽中分别形成多个第二导热柱，多个所述第二导热柱的顶面位于同一水平面，接着去除所述第二载板，以形成第一封装组件；
(6)提供一散热器，所述散热器的上表面设置多个平行排列的容置腔， 在每个所述容置腔的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔中均设置一所述第一封装组件，并使得多个所述第一导热柱和多个所述第二导热柱分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件；
(7)提供一导电基板，在所述导电基板的上表面和下表面均设置一所述第一功率堆叠件，使得两个所述第一功率堆叠件均与所述导电基板电连接，接着形成一第二封装层，所述第二封装层包裹所述导电基板以及两个所述第一功率堆叠件。
实施例2：在所述步骤1)中，首先在所述第一载板的中心区域形成一有机功能层，接着在所述第一载板以及所述有机功能层表面形成粘合胶层，所述粘合胶层与所述有机功能层的之间粘附力小于所述粘合胶层与所述第一载板之间的粘附力，接着在所述粘合胶层上粘结设置所述功率元件。
实施例3：在所述步骤2)中，所述掩膜层为光刻胶掩膜层，所述第一凹槽通过湿法刻蚀或干法刻蚀形成，位于所述行的中间位置的所述第一凹槽的深度为40-60微米，位于所述行的两端部的所述第一凹槽的深度为10-30微米。
实施例4：在所述步骤3)中，所述第一导热柱的材料为银、铜、铝、铁、锡、铅中的一种或多种，所述第一导热柱通过化学气相沉积、物理气相沉积、电镀以及化学镀中的一种或多种工艺形成。
实施例5：在所述步骤4)中，所述第一封装层的材料为环氧树脂，所述第一导热柱的突出部分的高度与所述第一导热柱的高度的比值为0.2-0.4。
实施例6：在所述步骤5)中，所述功率元件与所述电路板之间通过导电凸块进行电连接，所述第二凹槽的深度为50-80微米，所述第二导热柱突出于所述电路板的表面，所述第二导热柱的突出部分的高度与所述第二导热柱的高度的比值为0.15-0.3。
实施例7：在所述步骤6)中，将所述第一封装组件置于所述容置腔之后，在所述容置腔中注入导热绝缘材料，使得所述导热绝缘材料充满所述容置腔与所述第一封装组件之间的间隙。
实施例8：在所述步骤7)中，对所述第二封装层进行减薄处理，使得所述散热器的底面露出。
实施例9：本发明还提出一种功率元件封装结构，其采用上述方法制备形成的。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

  1. 一种功率元件封装结构的制备方法，其特征在于：包括以下步骤：
    (1)提供一第一载板以及一功率元件，所述功率元件具有有源面和非有源面，所述功率元件的所述有源面具有导电焊盘，接着以所述功率元件的有源面朝向所述第一载板的方式将所述功率元件安装在所述第一载板上；
    (2)接着在所述第一载板上设置一掩膜层，所述掩膜具有间隔设置多个开口，所述开口暴露所述功率元件的非有源面，接着利用所述掩膜层刻蚀所述功率元件以形成多个间隔设置的第一凹槽，其中，多个所述第一凹槽排列成一行，位于所述行的中间位置的所述第一凹槽的深度最大，而位于所述行的两端部的所述第一凹槽的深度最小，且从所述中间位置到每个所述端部的多个所述第一凹槽的深度逐渐减小；
    (3)接着在多个所述第一凹槽中分别形成多个第一导热柱，多个所述第一导热柱的顶面位于同一水平面；
    (4)接着在所述第一载板上设置第一封装层，多个所述第一导热柱突出于所述第一封装层的上表面；
    (5)接着提供一第二载板，将所述第二载板接合至所述第一封装层的上表面，接着去除所述第一载板，接着在所述功率元件上设置一电路板，所述 电路板电连接至所述功率元件，接着在所述电路板上形成多个间隔设置的第二凹槽，接着在多个所述第二凹槽中分别形成多个第二导热柱，多个所述第二导热柱的顶面位于同一水平面，接着去除所述第二载板，以形成第一封装组件；
    (6)提供一散热器，所述散热器的上表面设置多个平行排列的容置腔，在每个所述容置腔的相对的两个侧面上均设置一条形沟槽，接着在每个所述容置腔中均设置一所述第一封装组件，并使得多个所述第一导热柱和多个所述第二导热柱分别嵌入到相应的所述条形沟槽中，以形成第一功率堆叠件；
    (7)提供一导电基板，在所述导电基板的上表面和下表面均设置一所述第一功率堆叠件，使得两个所述第一功率堆叠件均与所述导电基板电连接，接着形成一第二封装层，所述第二封装层包裹所述导电基板以及两个所述第一功率堆叠件。
  2. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤1)中，首先在所述第一载板的中心区域形成一有机功能层，接着在所述第一载板以及所述有机功能层表面形成粘合胶层，所述粘合胶层与 所述有机功能层的之间粘附力小于所述粘合胶层与所述第一载板之间的粘附力，接着在所述粘合胶层上粘结设置所述功率元件。
  3. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤2)中，所述掩膜层为光刻胶掩膜层，所述第一凹槽通过湿法刻蚀或干法刻蚀形成，位于所述行的中间位置的所述第一凹槽的深度为40-60微米，位于所述行的两端部的所述第一凹槽的深度为10-30微米。
  4. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤3)中，所述第一导热柱的材料为银、铜、铝、铁、锡、铅中的一种或多种，所述第一导热柱通过化学气相沉积、物理气相沉积、电镀以及化学镀中的一种或多种工艺形成。
  5. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤4)中，所述第一封装层的材料为环氧树脂，所述第一导热柱的突出部分的高度与所述第一导热柱的高度的比值为0.2-0.4。
  6. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤5)中，所述功率元件与所述电路板之间通过导电凸块进行电连接，所述第二凹槽的深度为50-80微米，所述第二导热柱突出于所述电路板的表 面，所述第二导热柱的突出部分的高度与所述第二导热柱的高度的比值为0.15-0.3。
  7. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤6)中，将所述第一封装组件置于所述容置腔之后，在所述容置腔中注入导热绝缘材料，使得所述导热绝缘材料充满所述容置腔与所述第一封装组件之间的间隙。
  8. 根据权利要求1所述的功率元件封装结构的制备方法，其特征在于：在所述步骤7)中，对所述第二封装层进行减薄处理，使得所述散热器的底面露出。
  9. 一种功率元件封装结构，其特征在于，采用权利要求1-8任一项所述的方法制备形成的。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1619787A (zh) * 2003-09-19 2005-05-25 卡西欧计算机株式会社 半导体装置
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 系统级封装
CN104037153A (zh) * 2013-03-08 2014-09-10 台湾积体电路制造股份有限公司 3d封装件及其形成方法
CN111564411A (zh) * 2020-06-08 2020-08-21 侯立东 一种半导体装置及其形成方法
CN112420641A (zh) * 2020-11-26 2021-02-26 苏州矽锡谷半导体科技有限公司 一种功率元件封装结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1619787A (zh) * 2003-09-19 2005-05-25 卡西欧计算机株式会社 半导体装置
CN102439719A (zh) * 2009-05-14 2012-05-02 米辑电子股份有限公司 系统级封装
CN104037153A (zh) * 2013-03-08 2014-09-10 台湾积体电路制造股份有限公司 3d封装件及其形成方法
CN111564411A (zh) * 2020-06-08 2020-08-21 侯立东 一种半导体装置及其形成方法
CN112420641A (zh) * 2020-11-26 2021-02-26 苏州矽锡谷半导体科技有限公司 一种功率元件封装结构及其制备方法

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