TWI733619B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI733619B
TWI733619B TW109140644A TW109140644A TWI733619B TW I733619 B TWI733619 B TW I733619B TW 109140644 A TW109140644 A TW 109140644A TW 109140644 A TW109140644 A TW 109140644A TW I733619 B TWI733619 B TW I733619B
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Taiwan
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chip
circuit
layer
conductive
connection pad
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TW109140644A
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TW202221864A (zh
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張簡上煜
林南君
徐宏欣
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力成科技股份有限公司
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Priority to TW109140644A priority Critical patent/TWI733619B/zh
Priority to CN202011527139.3A priority patent/CN114520205A/zh
Priority to US17/330,416 priority patent/US11973037B2/en
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Publication of TWI733619B publication Critical patent/TWI733619B/zh
Publication of TW202221864A publication Critical patent/TW202221864A/zh

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Abstract

一種封裝結構，其包括第一晶片、第二晶片、介電體、導電端子、線路層以及圖案化絕緣層。第二晶片配置於第一晶片上。第二晶片的第二主動面面向第一晶片的第一主動面。介電體覆蓋第一晶片。導電端子位於介電體上且相對於第二晶片。線路層包括第一線路部分以及第二線路部分。第一線路部分貫穿介電體。第一晶片藉由第一線路部分電性連接於導電端子。第二線路部分嵌入介電體。第二晶片藉由第二線路部分電性連接於第一晶片。圖案化絕緣層覆蓋線路層且嵌入介電體。一種封裝結構的製造方法亦被提供。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有多個晶片的封裝結構及其製造方法。
為了使得電子產品能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。
而在具有多個晶片的晶片封裝結構中，如何提升晶片與晶片之間訊號傳輸品質或效率，實已成目前亟欲解決的課題。
本發明提供一種晶片封裝結構及晶片封裝結構的製造方法，其具有較佳的訊號傳輸品質或效率。
本發明的封裝結構包括第一晶片、第二晶片、介電體、導電端子、第一線路層以及第一圖案化絕緣層。第一晶片具有第一主動面。第二晶片具有第二主動面。第二晶片以其第二主動面 面向第一主動面的方式配置於第一晶片上。介電體覆蓋第一晶片。導電端子位於介電體上且相對於第二晶片。第一線路層包括第一線路部分以及第二線路部分。第一線路部分貫穿介電體。第一晶片藉由第一線路部分電性連接於導電端子。第二線路部分嵌入介電體。第二晶片藉由第二線路部分電性連接於第一晶片。第一圖案化絕緣層覆蓋線路層且嵌入介電體。
本發明的封裝結構的製造方法包括以下步驟：提供載板；配置第一晶片於載板上；形成介電體於載板上，以覆蓋第一晶片；形成第一線路層於載板上，且第一線路層包括第一線路部分以及第二線路部分，其中第一線路部分貫穿介電體，且第二線路部分嵌入介電體；形成第一圖案化絕緣層於載板上，以覆蓋線路層且嵌入介電體；配置第二晶片於第一晶片上，第二晶片的第二主動面面向第一晶片的第一主動面，且使第二晶片藉由第二線路部分電性連接於第一晶片；以及移除載板，以於相對於第二晶片的介電體上形成導電端子，且使第一晶片藉由第一線路部分電性連接於導電端子。
基於上述，本發明的晶片封裝結構及晶片封裝結構的製造方法可以具有較佳的訊號傳輸品質或效率。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
100、200、300:封裝結構
110:第一晶片
110a:第一主動面
110b:第一背面
110c:第一側面
120:第二晶片
120a:第二主動面
120b:第二背面
120c:第二側面
111、121:基材
112、122:晶片連接墊
113、123:晶片絕緣層
124:晶片保護層
125:晶片端子
125s:種子層
125p:鍍覆層
125r:導電連接層
130:重佈線路層
131、133:導電層
132、134:絕緣層
134d:開口
140:介電體
140d、140e:介電開口
140a:介電頂面
140b:介電底面
150:第一線路層
150a:導電頂面
150b:導電底面
150c:導電側面
151:第一線路部分
152:第二線路部分
151s、152s、153s:種子層
151p、152p、153p:鍍覆層
160:第一圖案化絕緣層
160d:絕緣開口
178:導電連接件
179:導電端子
184:黏著層
181:填充層
282、382:模封體
383:熱界面材料
384:散熱件
92:離型層
91:載板
F1、F2:界面
R1:區域
圖1A至圖1E是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
圖1F是依照本發明的第一實施例的一種封裝結構的剖視示意圖。
圖1G是依照本發明的第一實施例的一種封裝結構的部分剖視示意圖。
圖2是依照本發明的第二實施例的一種封裝結構的剖視示意圖。
圖3是依照本發明的第三實施例的一種封裝結構的剖視示意圖。
本文所使用之方向用語(例如，上、下、右、左、前、後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。
除非另有限制，否則術語「配置(disposed)」、「連接(connected)」、「接觸(contacted)」和其他在本文中的類似用語是廣義上使用的並且涵蓋直接和間接配置、連接、接觸和其他類似用語。類似地，術語「面向(facing、faces)」和其在本文中的類似用語是廣義上使用的並且涵蓋直接和間接面向。因此，附圖 和描述應被視為在本質上是說明性而非限制性的。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1E是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
請參照圖1A，提供載板91。本發明對於載板91並無特別的限制，只要載板91可以適於承載形成於其上膜層或配置於其上的元件即可。
在本實施例中，載板91上可以具有離型層92，但本發明不限於此。離型層92例如是光熱轉換(light to heat conversion；LTHC)黏著層或其他類似的膜層。
請繼續參照圖1A，在本實施例中，可以於載板91上形成重佈線路層130。重佈線路層130可以包括導電層131、133以及絕緣層132、134。最頂的絕緣層134(即，重佈線路層130中最遠離載板91的絕緣層；可以被稱為：第二圖案化絕緣層)可以具有多個開口134d，且開口134d可以暴露出最頂的導電層133(即，重佈線路層130中最遠離載板91的導電層；可以被稱為： 第二線路層)。重佈線路層130可以藉由一般常用的半導體製程(如：沉積製程、微影製程及/或蝕刻製程)形成，故於此不加以贅述。
請繼續參照圖1A，於載板91上配置第一晶片110。在本實施例中，第一晶片110可以被配置於重佈線路層130上，但本發明不限於此。
在本實施例中，第一晶片110可以包括基材111、多個晶片連接墊112(可以被稱為：第一晶片連接墊)以及晶片絕緣層113(可以被稱為：第一晶片絕緣層)。基材111的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為第一主動面110a。相對於第一主動面110a的表面可以被稱為第一背面110b。連接於第一主動面110a及第一背面110b之間的表面可以被稱為第一側面110c。晶片連接墊112可以位於第一主動面110a上。晶片絕緣層113可以覆蓋晶片連接墊112，且晶片絕緣層113暴露出晶片連接墊112的一部分。在一般晶片設計中，元件區內的元件(如：第一晶片110的元件區內的元件)可以藉由對應的後段金屬內連線(Back End of Line Interconnect；BEOL Interconnect)電性連接於對應的晶片連接墊(die pad；如：第一晶片110的部分晶片連接墊112)。
在本實施例中，晶片連接墊112例如為鋁墊、銅墊或其他適宜的晶片連接墊，但本發明不限於此。
在一實施例中，第一晶片110的第一背面110b上可以具 有黏著層184，但本發明不限於此。黏著層184可以包括晶片黏著膜(die attach film；DAF)，但本發明不限於此。
請參照圖1A至圖1B，於載板91上形成介電體140。介電體140可以覆蓋第一晶片110。舉例而言，介電體140可以覆蓋第一晶片110的第一主動面110a及第一側面110c。介電體140可以具有暴露出晶片連接墊112的第二介電開口140e。在一實施例中，介電體140可以藉由塗佈法或其他適宜的製程形成，但本發明不限於此。
在本實施例中，介電體140可以被形成於重佈線路層130上，但本發明不限於此。介電體140可以具有暴露出最頂的導電層134的第一介電開口140d。舉例而言，可以將光敏介電材(photoimageable dielectric material；PID material)塗佈於重佈線路層130上。然後，可以藉由光聚合(photopolymerization)及/或烘烤(baking)的方式固化部分的光敏介電材。並且，於固化部分的光敏介電材之後，藉由濕清洗(wet clean)或其他適宜的方式以移除未被固化的其餘光敏介電材。如此一來，可以藉由上述的方式而形成具有第一介電開口140d及第二介電開口140e的介電體140。
在一實施例中，介電體140的形成方式可以依據其性質而加以調整，於本發明並不加以限制。
請參照圖1B至圖1C，於載板91上形成第一線路層150。第一線路層150可以覆蓋介電體140，且第一線路層150可以填入 介電體140的第一介電開口140d(標示於圖1B)及第二介電開口140e(標示於圖1B)。
在本實施例中，第一線路層150可以藉由濺鍍製程、微影製程、電鍍製程及/或蝕刻製程形成，但本發明不限於此。舉例而言，可以藉由濺鍍製程於介電體140的表面上形成種子層(seed layer)。然後，可以藉由微影製程於種子層上形成圖案化光阻層。然後，可以在藉由電鍍製程以在圖案化光阻層所暴露出的部分種子層上形成鍍覆層。然後，可以藉由蝕刻製程移除圖案化光阻層及未被鍍覆層覆蓋於其上的另一部分種子層。圖案化的種子層151s、152s、153s(標示於圖1G)及位於其上的圖案化的鍍覆層151p、152p、153p(標示於圖1G)可以構成圖案化的第一線路層150。
在本實施例中，第一線路層150可以包括第一線路部分151。第一線路部分151可以位於介電體140的第一介電開口140d(標示於圖1B)內。位於第一介電開口140d內的部分第一線路部分151可以共形覆蓋(conformally covered)第一介電開口140d的底部及側壁。
在本實施例中，第一線路部分151可以完全填入絕緣層134的開口134d(標示於圖1B)。第一線路部分151可以直接接觸重佈線路層130中最頂的導電層133。舉例而言，屬於第一線路部分151的圖案化種子層151s(標示於圖1G)可以直接接觸部分的導電層133。
在本實施例中，第一線路部分151與導電層133是藉由不同的步驟所形成。如此一來，相接觸的第一線路部分151與導電層133之間可以具有界面(interface)F1(標示於圖1G)。舉例而言，屬於第一線路部分151的部分圖案化種子層151s(標示於圖1G)與導電層133之間可以具有界面F1。
在本實施例中，第一線路層150可以包括第二線路部分152。第二線路部分152可以位於介電體140的第二介電開口140e(標示於圖1B)內，且第二線路部分152可以完全填入第二介電開口140e。第二線路部分152可以直接接觸第一晶片110的晶片連接墊112。舉例而言，屬於第二線路部分152的圖案化種子層152s(標示於圖1G)可以直接接觸第一晶片110的晶片連接墊112。
請參照圖1C至圖1D，於載板91上形成第一圖案化絕緣層160。第一圖案化絕緣層160的材料可以包含無機材料、有機材料、其他適宜的絕緣材料或上述之堆疊，於本發明並不加以限制。在一實施例中，第一圖案化絕緣層160的形成方式可以依據其性質而加以調整，於本發明並不加以限制。
在本實施例中，第一圖案化絕緣層160可以覆蓋第一線路層150。第一圖案化絕緣層160可以具有多個絕緣開口160d，以暴露出部分的第一線路層150。舉例而言，絕緣開口160d可以暴露出部分的第二線路部分152。
在本實施例中，第一圖案化絕緣層160可以接觸介電體140。舉例而言，第一圖案化絕緣層160可以直接接觸介電體140 的部分介電頂面140a(即，第一圖案化絕緣層160最遠離載板91或重佈線路層130的表面)。
在本實施例中，第一圖案化絕緣層160與介電體140是藉由不同的步驟所形成。如此一來，相接觸的第一圖案化絕緣層160與介電體140之間可以具有界面F2(標示於圖1G)。
在本實施例中，部分的第一圖案化絕緣層160可以填入介電體140的第一介電開口140d(標示於圖1B)。如此一來，可以降低位於第一介電開口140d內的第一線路部分151剝離(peeling)的可能。並且，在形成第一線路層150時，可以降低鍍覆的厚度，而可以提升封裝結構的製造效率。
請參照圖1D至圖1E，在形成第一圖案化絕緣層160之後，可以將第二晶片120配置於第一晶片110上。第二晶片120可以藉由導電連接件178電性連接第一晶片110。
在本實施例中，第二晶片120可以包括基材121、多個晶片連接墊122(可以被稱為：第二晶片連接墊)、晶片絕緣層123(可以被稱為：第二晶片絕緣層)、晶片保護層124以及多個晶片端子125。基材121的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為第二主動面120a。相對於第二主動面120a的表面可以被稱為第二背面120b。連接於第二主動面120a及第二背面120b之間的表面可以被稱為第二側面120c。晶片連接墊122可以位於第二主動面120a上。晶片絕緣層123可以覆蓋晶片連接墊122，晶片保護層124可以覆蓋晶片絕緣層123，且晶片絕緣層123 及晶片保護層124可以暴露出晶片連接墊122的一部分。在一般晶片設計中，元件區內的元件(如：第二晶片120的元件區內的元件)可以藉由對應的後段金屬內連線(Back End of Line Interconnect；BEOL Interconnect)電性連接於對應的連接墊(如：第二晶片120的部分晶片連接墊122)。晶片端子125可以包括種子層125s(標示於圖1G)、鍍覆層125p(標示於圖1G)以及導電連接層125r(標示於圖1G)，但本發明不限於此。在一實施例中，晶片端子125的種子層125s可以直接接觸晶片連接墊122，且鍍覆層125p可以位於種子層125s與導電連接層125r之間，但本發明不限於此。晶片連接墊122可以藉由對應的晶片端子125電性連接於對應的導電連接件178。
在一實施例中，導電連接件178可以是焊球(solder ball)、導電凸塊(conductive bump)或具有其他形式或形狀的導電連接件。導電連接件178可以經由置球(ball placement)、迴焊(reflow)及/或其他適宜的製程來形成。
在本實施例中，第二晶片120與第一圖案化絕緣層160之間可以形成填充層181。填充層181可以包括毛細底部填膠(capillary underfill；CUF)或其他適宜的底膠(underfill)，但本發明不限於此。
請繼續參照圖1D至圖1E，在本實施例中，在移除載板91之後，可以形成多個導電端子179。導電端子179可以是導電柱(conductive pillar)、焊球(solder ball)、導電凸塊(conductive bump)或具有其他形式或形狀的導電端子179。導電端子179可以經由電鍍、沉積、置球(ball placement)、迴焊(reflow)及/或其他適宜的製程來形成。導電端子179可以藉由重佈線路層130中對應的線路電性連接於第一線路層150中對應的第一線路部分151。
請參照圖1E，在本實施例中，可以經由單一化製程(singulation process)，以至少切穿重佈線路層130、介電體140以及第一圖案化絕緣層160。單一化製程例如可以包括切割製程(dicing process/cutting process)，但本發明不限於此。
值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件。舉例而言，第一晶片110(如圖1D所示)於單一化後可以為第一晶片110(如圖1E所示)，重佈線路層130(如圖1D所示)於單一化後可以為重佈線路層130(如圖1E所示)，介電體140(如圖1D所示)於單一化後可以為介電體140(如圖1E所示)，第一圖案化絕緣層160(如圖1D所示)於單一化後可以為第一圖案化絕緣層160(如圖1E所示)，諸如此類。其他單一化後的元件將依循上述相同的元件符號規則，於此不加以贅述或特別繪示。
值得注意的是，本發明並未限定配置第二晶片120、形成多個導電端子179以及單一化製程(若有)的順序。舉例而言，可以在配置第二晶片120之後形成多個導電端子179，然後進行單一化製程。又舉例而言，可以在配置第二晶片120之後進行單一 化製程，然後形成多個導電端子179。
圖1F是依照本發明的第一實施例的一種封裝結構的剖視示意圖。圖1G是依照本發明的第一實施例的一種封裝結構的部分剖視示意圖。圖1G可以是對應於圖1F中區域R1的放大圖。請參照圖1F及圖1G，經過上述步驟後即可大致上完成本實施例的封裝結構100的製作。
封裝結構100包括第一晶片110、第二晶片120、介電體140、導電端子179以及第一線路層150。第二晶片120以第二主動面120a面向第一主動面110a的方式配置於第一晶片110上。介電體140覆蓋第一晶片110。導電端子179位於介電體140上且相對於第二晶片120。第一線路層150包括第一線路部分151以及第二線路部分152。第一線路部分151貫穿介電體140。第一晶片110藉由第一線路部分151電性連接於導電端子179。第二線路部分152嵌入介電體140。第二晶片120藉由第二線路部分152電性連接於第一晶片110。第一圖案化絕緣層160覆蓋第一線路層150且嵌入介電體140。
在本實施例中，第一線路層150可以具有導電頂面150a、導電底面150b及導電側面150c。導電頂面150a可以是第一線路層150中最遠離重佈線路層130的表面。導電底面150b可以是第一線路層150中最接近重佈線路層130的表面。導電側面150c可以是連接導電頂面150a及導電底面150b的表面。第一圖案化絕緣層160可以覆蓋第一線路層150的部分導電頂面150a及部分導 電側面150c。如此一來，可以降低位於第一線路層150剝離(peeling)的可能。
在本實施例中，介電底面140b的位置(泛指自其延伸的虛擬面)可以介於導電頂面150a的位置(泛指自其延伸的虛擬面)與導電底面150b的位置(泛指自其延伸的虛擬面)之間，且介電頂面140a的位置(泛指自其延伸的虛擬面)可以介於導電頂面150a的位置(泛指自其延伸的虛擬面)與導電底面150b的位置(泛指自其延伸的虛擬面)之間。也就是說，第一線路層150的導電底面150b與介電體140的介電底面140b(即，介電體140最接近重佈線路層130的表面)不共面，且第一線路層150的導電頂面150a與介電體140的介電頂面140a不共面。
在本實施例中，第一晶片110與第二晶片120之間的訊號傳輸距離基本上相同於第一晶片110與第二晶片120之間的物理距離。舉例而言，第一晶片110與第二晶片120之間的訊號可以藉由對應的導電件(如：對應的導電連接件178及對應的第二線路部分152)傳輸，且第一晶片110的晶片連接墊112與第二晶片120的晶片端子125之間的距離基本上等於前述的導電件的高度或厚度(如：對應的導電連接件178的高度及對應的第二線路部分152的厚度)。如此一來，可能可以提升第一晶片110與第二晶片120之間訊號傳輸的品質及效率。
一般而言，在多個導電結構所構成的導體中，沿著導體傳輸的信號會因為多個導電結構之間的不連續(如：可能因材質 或晶格的不同而具有介面或阻抗不匹配)而會有對應的反射訊號。這種現象可以被稱為回波損耗(return loss)。因此，相較於以一般重佈線路的方式進行晶片間的訊號傳輸，藉由對應的導電連接件178及對應的第二線路部分152可能可以提升第一晶片110與第二晶片120之間訊號傳輸的品質及效率。
在一實施例中，第一晶片110及第二晶片120可以是具有相同或不同功能(function)的晶粒(die)、封裝後晶片(packaged chip)、堆疊式的晶片封裝件(stacked chip package)或是特殊應用積體電路(Application-Specific Integrated Circuit；ASIC)，但本發明不限於此。
在一實施例中，第一晶片110及第二晶片120之間可以是異質的(heterogeneous)晶片。舉例而言，第一晶片110及第二晶片120的其中之一可以是動態隨機存取記憶體晶片(dynamic random access memory，DRAM)、靜態隨機存取記憶體晶片(static random access memory，SRAM)或高頻寬記憶體(High Bandwidth Memory，HBM)晶片，第一晶片110及第二晶片120的其中另一可以是特殊應用積體電路晶片(Application-specific integrated circuit，ASIC)、應用處理器(application processor，AP)、系統晶片(system on chip，SoC)或其他類似的高效能運算(High Performance Computing，HPC)晶片，但本發明不限於此。
圖2是依照本發明的第二實施例的一種封裝結構的剖視示意圖。第二實施例的封裝結構200與第一實施例的封裝結構100 相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖2，封裝結構200可以包括第一晶片110、第二晶片120、介電體140、導電端子179、第一線路層150以及模封體282。模封體282覆蓋第二晶片120。舉例而言，模封體282可以覆蓋第二晶片120的第二側面120c。在一實施例中，模封體282的材質可以包括環氧樹脂(epoxy resin)或其他適宜的模塑化合物(molding compound)，但本發明不限於此。模封體282例如是藉由模塑製程(molding process)所形成，但本發明不限於此。
在本實施例中，模封體282可以更覆蓋第二晶片120的第二背面120b，但本發明不限於此。
圖3是依照本發明的第三實施例的一種封裝結構的剖視示意圖。第三實施例的封裝結構300與第二實施例的封裝結構200相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖3，封裝結構300可以包括第一晶片110、第二晶片120、介電體140、導電端子179、第一線路層150、模封體382以及散熱件384。模封體382可以暴露出第二晶片120的第二背面120b。散熱件384可以熱耦接於第二晶片120。
在本實施例中，第二晶片120的第二背面120b與散熱件384之間可以具有熱界面材料(Thermal Interface Material；TIM)383，但本發明不限於此。
在一實施例中，第二晶片120的第二背面120b可以直接接觸散熱件384，但本發明不限於此。
在一實施例中，類似於散熱件384的散熱件可以具有鰭片(fins)，但本發明不限於此。
綜上所述，本發明的晶片封裝結構及晶片封裝結構的製造方法可以具有較佳的訊號傳輸品質或效率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:封裝結構
110:第一晶片
110a:第一主動面
110b:第一背面
120:第二晶片
120a:第二主動面
120b:第二背面
130:重佈線路層
131、133:導電層
132、134:絕緣層
140:介電體
150:第一線路層
150a:導電頂面
150b:導電底面
150c:導電側面
151:第一線路部分
152:第二線路部分
160:第一圖案化絕緣層
178:導電連接件
179:導電端子
181:填充層
184:黏著層
R1:區域

Claims (10)

  1. 一種封裝結構，包括：第一晶片，具有第一主動面；第二晶片，具有第二主動面，且所述第二晶片以所述第二主動面面向所述第一主動面的方式配置於所述第一晶片上；介電體，覆蓋所述第一晶片；導電端子，位於所述介電體上且相對於所述第二晶片；第一線路層，包括第一線路部分以及第二線路部分，其中：所述第一線路部分貫穿所述介電體，且所述第一晶片藉由所述第一線路部分電性連接於所述導電端子；且所述第二線路部分嵌入所述介電體，且所述第二晶片藉由所述第二線路部分電性連接於所述第一晶片；第一圖案化絕緣層，覆蓋所述第一線路層且嵌入所述介電體；以及導電連接件，配置於所述第一晶片與所述第二晶片之間，且所述第一晶片更藉由所述導電連接件電性連接於所述第二晶片，其中：所述第一晶片包括位於所述第一主動面上的第一連接墊及第一晶片絕緣層，所述第一晶片絕緣層暴露出部分的所述第一連接墊，且所述第二線路部分直接接觸所述第一連接墊；或所述第二晶片包括位於所述第二主動面上的第二連接墊、第二晶片絕緣層及晶片端子，所述第二晶片絕緣層暴露出部 分的所述第二連接墊，所述晶片端子直接接觸所述第二連接墊，且所述第一晶片藉由所述導電連接件電性連接於所述第二晶片的所述晶片端子。
  2. 如請求項1所述的封裝結構，其中所述第一晶片包括位於所述第一主動面上的所述第一連接墊及所述第一晶片絕緣層，所述第一晶片絕緣層暴露出部分的所述第一連接墊，且所述第二線路部分直接接觸所述第一連接墊。
  3. 如請求項1所述的封裝結構，其中所述第二晶片包括位於所述第二主動面上的所述第二連接墊、所述第二晶片絕緣層及所述晶片端子，所述第二晶片絕緣層暴露出部分的所述第二連接墊，所述晶片端子直接接觸所述第二連接墊。
  4. 如請求項1所述的封裝結構，其中所述介電體具有介電底面，所述第一線路層具有導電底面，且所述介電底面及所述導電底面不共面。
  5. 如請求項1所述的封裝結構，其中所述第一圖案化絕緣層覆蓋所述第一線路層的導電頂面及導電側面。
  6. 如請求項1所述的封裝結構，其中所述介電體與所述第一圖案化絕緣層相接觸，且所述介電體與所述第一圖案化絕緣層之間具有界面。
  7. 如請求項1所述的封裝結構，更包括：第二線路層，位於所述介電體的介電底面上，且所述導電端子藉由所述第二線路層電性連接於所述第一線路部分。
  8. 如請求項7所述的封裝結構，更包括：第二圖案化絕緣層，覆蓋所述第二線路層，所述第二圖案化絕緣層具有絕緣開口，且所述第一線路部分填入所述絕緣開口以接觸所述第二線路層。
  9. 如請求項8所述的封裝結構，其中所述第二線路層與所述第一線路部分之間具有界面。
  10. 一種封裝結構的製造方法，包括：提供載板；配置第一晶片於所述載板上；形成介電體於所述載板上，以覆蓋所述第一晶片；形成第一線路層於所述載板上，且所述第一線路層包括第一線路部分以及第二線路部分，其中所述第一線路部分貫穿所述介電體，且所述第二線路部分嵌入所述介電體；形成第一圖案化絕緣層於所述載板上，以覆蓋所述第一線路層且嵌入所述介電體；配置第二晶片於所述第一晶片上，所述第二晶片的第二主動面面向所述第一晶片的第一主動面，所述第一晶片與所述第二晶片之間具有導電連接件，且使所述第二晶片藉由所述第二線路部分及所述導電連接件電性連接於所述第一晶片；以及移除所述載板，以於相對於所述第二晶片的所述介電體上形成導電端子，且使所述第一晶片藉由所述第一線路部分電性連接於所述導電端子，其中： 所述第一晶片包括位於所述第一主動面上的第一連接墊及第一晶片絕緣層，所述第一晶片絕緣層暴露出部分的所述第一連接墊，且所述第二線路部分直接接觸所述第一連接墊；或所述第二晶片包括位於所述第二主動面上的第二連接墊、第二晶片絕緣層及晶片端子，所述第二晶片絕緣層暴露出部分的所述第二連接墊，所述晶片端子直接接觸所述第二連接墊，且所述第一晶片藉由所述導電連接件電性連接於所述第二晶片的所述晶片端子。
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Publication number Priority date Publication date Assignee Title
US20170170154A1 (en) * 2015-12-10 2017-06-15 Seung-Kwan Ryu Semiconductor package and method of fabricating the same
US20180151477A1 (en) * 2016-11-28 2018-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
WO2018122995A1 (ja) * 2016-12-28 2018-07-05 株式会社野田スクリーン 薄膜キャパシタ、および半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170170154A1 (en) * 2015-12-10 2017-06-15 Seung-Kwan Ryu Semiconductor package and method of fabricating the same
US20180151477A1 (en) * 2016-11-28 2018-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
WO2018122995A1 (ja) * 2016-12-28 2018-07-05 株式会社野田スクリーン 薄膜キャパシタ、および半導体装置

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