US10170389B2 - Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods - Google Patents

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods Download PDF

Info

Publication number
US10170389B2
US10170389B2 US14/825,009 US201514825009A US10170389B2 US 10170389 B2 US10170389 B2 US 10170389B2 US 201514825009 A US201514825009 A US 201514825009A US 10170389 B2 US10170389 B2 US 10170389B2
Authority
US
United States
Prior art keywords
dies
semiconductor
thermal transfer
die
transfer feature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/825,009
Other versions
US20150348956A1 (en
Inventor
Steven K. Groothuis
Jian Li
Haojun Zhang
Paul A. Silvestri
Xiao Li
Shijian Luo
Luke G. England
Brent Keeth
Jaspreet S. Gandhi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US14/825,009 priority Critical patent/US10170389B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of US20150348956A1 publication Critical patent/US20150348956A1/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Priority to US16/229,257 priority patent/US10741468B2/en
Application granted granted Critical
Publication of US10170389B2 publication Critical patent/US10170389B2/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR PRODUCTS, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Priority to US16/936,639 priority patent/US11594462B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544Design considerations for via connections, e.g. geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the disclosed embodiments relate to semiconductor die assemblies.
  • the present technology relates to stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods.
  • Packaged semiconductor dies including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering.
  • the die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features.
  • the bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
  • TSVs through-silicon vias
  • a challenge associated with vertically stacked die packages is that the heat generated by the individual dies combines and increases the operating temperatures of the individual dies, the junctions therebetween, and the package as a whole. This can cause the stacked dies to reach temperatures above their maximum operating temperatures (T max ), especially as the density of the dies in the package increases.
  • T max maximum operating temperatures
  • FIG. 1 is a cross-sectional view of a semiconductor die assembly configured in accordance with embodiments of the present technology.
  • FIG. 2A is a schematic partial side view illustrating a temperature profile of a hybrid memory cube assembly without multiple thermal paths.
  • FIG. 2B is a schematic partial side view illustrating a temperature profile of a hybrid memory cube assembly configured in accordance with embodiments of the present technology.
  • FIG. 3 is a cross-sectional view of a semiconductor die assembly configured in accordance with other embodiments of the present technology.
  • FIG. 4 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with further embodiments of the present technology.
  • FIG. 5 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with still further embodiments of the present technology.
  • FIG. 6 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with additional embodiments of the present technology.
  • FIG. 7 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with other embodiments of the present technology.
  • FIG. 8 is a schematic view of a system that includes a semiconductor die assembly configured in accordance with embodiments of the present technology.
  • semiconductor die generally refers to a die having integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates.
  • semiconductor dies can include integrated circuit memory and/or logic circuitry.
  • Semiconductor dies and/or other features in semiconductor die packages can be said to be in “thermal contact” with one another if the two structures can exchange energy through heat.
  • the terms “vertical,” “lateral,” “upper” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations.
  • FIG. 1 is a cross-sectional view of a semiconductor die assembly 100 (“assembly 100 ”) configured in accordance with embodiments of the present technology.
  • the assembly 100 can include one or a plurality of first semiconductor dies 102 arranged in a stack 104 on a second semiconductor die 106 and carried by a package substrate 130 .
  • the second semiconductor die 106 can have a larger footprint than the stacked first semiconductor dies 102 .
  • the second semiconductor die 106 therefore, includes a peripheral portion 108 extending laterally outward beyond at least one side of the first semiconductor dies 102 (e.g., beyond the length and/or width of the first semiconductor dies 102 ).
  • the assembly 100 can further include a first thermal transfer feature 110 a at the peripheral portion 108 of the second semiconductor die 106 and an optional second thermal transfer feature 110 b superimposed with the first semiconductor dies 102 .
  • thermal energy can flow away from the second semiconductor die 106 through the first semiconductor dies 102 via a first thermal path (e.g., as illustrated by arrow T 1 ) and through the first thermal transfer feature 110 a via a second thermal path (e.g., illustrated by arrows T 2 ) separate from the first thermal path T 1 .
  • the second thermal path T 2 of the embodiment shown in FIG. 1 is accordingly spaced laterally apart from the perimeter edges of the first semiconductor dies 102 .
  • the first and second semiconductor dies 102 and 106 can include various types of semiconductor components and functional features, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuits, imaging components, and/or other semiconductor features.
  • the assembly 100 can be configured as a hybrid memory cube (HMC) in which the stacked first semiconductor dies 102 are DRAM dies or other memory dies that provide data storage and the second semiconductor die 106 is a high-speed logic die that provides memory control (e.g., DRAM control) within the HMC.
  • the first and second semiconductor dies 102 and 106 may include other semiconductor components and/or the semiconductor components of the individual first semiconductor dies 102 in the stack 104 may differ.
  • the dies 102 , 106 can be rectangular, circular, and/or other suitable shapes and may have various different dimensions.
  • the individual first semiconductor dies 102 can each have a length L 1 of about 10-11 mm (e.g., 10.7 mm) and a width of about 8-9 mm (e.g., 8.6 mm, 8.7 mm).
  • the second semiconductor die 106 can have a length L 2 of about 12-13 mm (e.g., 12.67 mm) and a width of about 8-9 mm (e.g., 8.5 mm, 8.6 mm, etc.).
  • the first and second semiconductor dies 102 and 106 can have other suitable dimensions and/or the individual first semiconductor dies 102 may have different dimensions from one another.
  • the peripheral portion 108 (known to those skilled in the art as a “porch” or “shelf”) of the second semiconductor die 106 can be defined by the relative dimensions of the first and second semiconductor dies 102 and 106 and the position of the stack 104 on a forward-facing surface 112 of the second semiconductor die 106 .
  • the stack 104 is centered with respect to the length L 2 of the second semiconductor die 106 such that the peripheral portion 108 extends laterally beyond two opposite sides of the stack 104 .
  • the peripheral portion 108 will extend about 0.5 mm beyond either side of the centered first semiconductor dies 102 .
  • the stack 104 may also be centered with respect to the width of the second semiconductor die 106 and, in embodiments where both the width and length of the second semiconductor die 106 are greater than those of the centered stack 104 , the peripheral portion 108 may extend around the entire perimeter of the first semiconductor dies 102 .
  • the stack 104 may be offset with respect to the forward-facing surface 112 of the second semiconductor die 106 and/or the peripheral portion 108 of the second semiconductor die 106 may extend around less than the full perimeter of the stack 104 .
  • the first and second semiconductor dies 102 and 106 can be circular, and therefore the relative diameters of the first and second semiconductor dies 102 and 106 define the peripheral portion 108 .
  • the first semiconductor dies 102 can be electrically coupled to one another in the stack 104 and to the underlying second semiconductor die 106 by a plurality of electrically conductive elements 114 positioned between adjacent dies 102 , 106 .
  • the stack 104 shown in FIG. 1 includes eight first semiconductor dies 102 electrically coupled together, in other embodiments the stack 104 can include fewer than eight dies (e.g., three dies, four dies, etc.) or more than eight dies (e.g., ten dies, twelve dies, etc.).
  • the electrically conductive elements 114 can have various suitable structures, such as pillars, columns, studs, bumps, and can be made from copper, nickel, solder (e.g., SnAg-based solder), conductor-filled epoxy, and/or other electrically conductive materials.
  • the electrically conductive elements 114 can be copper pillars, whereas in other embodiments the electrically conductive elements 114 can include more complex structures, such as bump-on-nitride structures.
  • the individual first semiconductor dies 102 can each include a plurality of TSVs 116 aligned on one or both sides with corresponding electrically conductive elements 114 to provide electrical connections at opposing sides of the first semiconductor dies 102 .
  • Each TSV 116 can include an electrically conductive material (e.g., copper) that passes completely through the individual first semiconductor dies 102 and an electrically insulative material surrounding the electrically conductive material to electrically isolate the TSVs 116 from the remainder of the die 102 .
  • the second semiconductor die 106 can also include a plurality of TSVs 116 to electrically couple the second semiconductor die 106 to higher level circuitry.
  • the TSVs 116 and the electrically conductive elements 114 can serve as thermal conduits through which heat can be transferred away from the first and second semiconductor dies 102 and 106 (e.g., through the first thermal path T 1 ).
  • the dimensions of the electrically conductive elements 114 and/or the TSVs 116 can be increased to enhance thermal contact conductance of the stack 104 .
  • the individual electrically conductive elements 114 can each have a diameter of about 15-30 ⁇ m or other suitable dimensions to enhance the thermal path away from the dies 102 , 106 .
  • the first semiconductor dies 102 can be electrically coupled to one another and to the second semiconductor die 106 using other types of electrical connectors (e.g., wirebonds) that may also serve as thermal pathways through the stack 104 .
  • a dielectric underfill material 118 can be deposited or otherwise formed around and/or between the first and second semiconductor dies 102 and 106 to electrically isolate the electrically conductive elements 114 and/or enhance the mechanical connection between the semiconductor dies 102 , 106 .
  • the underfill material 118 can be a non-conductive epoxy paste (e.g., XS8448-171 manufactured by Namics Corporation of Niigata, Japan), a capillary underfill, a non-conductive film, a molded underfill, and/or include other suitable electrically-insulative materials.
  • the underfill material 118 can be selected based on its thermal conductivity to enhance heat dissipation through the stack 104 .
  • the assembly 100 may also include a plurality of thermally conductive elements 120 (shown in broken lines) positioned interstitially between the electrically conductive elements 114 .
  • the individual thermally conductive elements 120 can be at least generally similar in structure and composition as that of the electrically conductive elements 114 (e.g., copper pillars).
  • the thermally conductive elements 120 are not electrically coupled to the TSVs 116 , and therefore do not provide electrical connections between the first semiconductor dies 102 .
  • the thermally conductive elements 120 serve to increase the overall thermal conductivity of the stack 104 , thereby facilitating heat transfer through the stack 104 (e.g., along the first thermal path T 1 ).
  • the addition of the thermally conductive elements 120 between the electrically conductive elements 114 has been shown to decrease the operating temperature of the HMC by several degrees (e.g., about 6-7° C.).
  • the package substrate 130 can provide the dies 102 , 106 with electrical connections to external electrical components (e.g., higher-level packaging; not shown).
  • the package substrate 130 can be an interposer or printed circuit board that includes semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive components (e.g., various ceramic substrates, such as aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), etc.), and/or conductive portions (e.g., interconnecting circuitry, TSVs, etc.).
  • semiconductor components e.g., doped silicon wafers or gallium arsenide wafers
  • non-conductive components e.g., various ceramic substrates, such as aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), etc.
  • conductive portions e.g., interconnecting circuitry, TSVs, etc.
  • the package substrate 130 is electrically coupled to the second semiconductor die 106 at a first side 132 a of the package substrate 130 via a first plurality of electrical connectors 134 a and to external circuitry (not shown) at a second side 132 b of the package substrate 130 via a second plurality of electrical connectors 134 b (collectively referred to as “the electrical connectors 134 ”).
  • the electrical connectors 134 can be solder balls, conductive bumps and pillars, conductive epoxies, and/or other suitable electrically conductive elements.
  • a dielectric underfill (e.g., FP4585 manufactured by Henkel of Diisseldorf, Germany; not shown) can be spaced between the second semiconductor die 106 and the package substrate 130 for enhanced mechanical connection and electrical isolation of the first plurality of electrical connectors 134 a .
  • the package substrate 130 can be made from a material with a relatively high thermal conductivity to enhance heat dissipation at the back side of the second semiconductor die 106 .
  • the first thermal transfer feature 110 a can thermally contact the peripheral portion 108 of the second semiconductor die 106 to remove heat along the second thermal path T 2
  • the second thermal transfer feature 110 b can thermally contact the uppermost die 102 in the stack 104 to remove heat along the first thermal path T 1
  • the first thermal transfer feature 110 a has a pillar-like structure that extends vertically from the peripheral portion 108 to an elevation generally corresponding to that of the outermost die 102 in the stack 104 to define a substantially vertical thermal path from which heat can be removed from the peripheral portion 108 . As shown in FIG.
  • the underfill material 118 and/or other thermally transmissive materials may be spaced between the first thermal transfer feature 110 a and the peripheral portion 108 (e.g., for adhesive purposes).
  • the first thermal transfer feature 110 a can extend vertically a lesser or greater elevation with respect to the elevation of the stacked first semiconductor dies 102 to define other vertical thermal paths.
  • the first thermal transfer feature 110 a can have different configurations and may define thermal paths that transfer heat laterally outward (i.e., rather than vertically away) from the peripheral portion 108 .
  • the second thermal transfer feature 110 b extends across a forward-facing surface 111 of the first semiconductor die 102 spaced furthest from the second semiconductor die 106 (e.g., the uppermost die 102 in the stack 104 ).
  • the second thermal transfer feature 110 b can therefore absorb heat directly from the stack 104 (e.g., through the electrically conductive elements 114 and TSVs 116 ) and transfer it away from the dies 102 , 106 .
  • the second thermal transfer element 110 b can have other suitable configurations, and/or the first and second thermal transfer elements 110 a and 110 b can be an integral structure formed on the peripheral portion 108 and over the stack 104 .
  • the second thermal transfer feature 110 a can be omitted.
  • the thermal transfer features 110 can be made from materials with relatively high thermal conductivities to increase the thermal conductance of heat away from the dies 102 , 106 .
  • the first thermal transfer feature 110 a can be made from blank silicon, which can have a thermal conductivity dependent on temperature (e.g., about 149 W/m° K at 25° C. and/or about 105 W/m ° K at 100° C.).
  • the first and/or second thermal transfer features 110 can be made from what are known in the art as “thermal interface materials” or “TIMs”, which are designed to increase the thermal contact conductance at surface junctions (e.g., between a die surface and a heat spreader).
  • TIMs can include silicone-based greases, gels, or adhesives that are doped with conductive materials (e.g., carbon nano-tubes, solder materials, diamond-like carbon (DLC), etc.), as well as phase-change materials.
  • conductive materials e.g., carbon nano-tubes, solder materials, diamond-like carbon (DLC), etc.
  • phase-change materials e.g., phase-change materials.
  • the second thermal transfer feature 110 b can be made from X-23-7772-4 TIM manufactured by Shin-Etsu MicroSi, Inc. of Phoenix, Ariz., which has a thermal conductivity of about 3-4 W/m° K.
  • the thermal transfer features 110 can be made from metals (e.g., copper) and/or other suitable thermally conductive materials.
  • the thermal transfer features 110 can be pre-formed members (e.g., pads, pillars, and/or other suitable structures) that can be attached to the peripheral portion 108 of the second semiconductor die 106 and/or superimposed with the first semiconductor dies 102 (e.g., via a thermally transmissive adhesive, curing, etc.).
  • the thermal transfer features 110 may be deposited or otherwise formed on the forward-facing surface 112 of the peripheral portion 108 and/or on the forward-facing surface 111 of the stack 104 using formation methods known to those in the art, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).
  • the first and second thermal transfer features 110 a and 110 b can thermally contact a thermally conductive casing 122 (“casing 122 ”) that extends at least partially around the first and second semiconductor dies 102 and 106 .
  • the casing 122 can include an outer portion 124 spaced laterally apart from the second semiconductor die 106 on the package substrate 130 and a cap portion 126 carried by the outer portion 124 .
  • the outer portion 124 and the cap portion 126 form a recess 136 configured such that both the vertically-extending first thermal transfer feature 110 a and the second thermal transfer feature 110 b thermally contact an underside of the cap portion 126 .
  • the casing 122 and/or the thermal transfer features 110 can have other suitable configurations such that the thermal transfer features 110 thermally contact other portions of the casing 122 .
  • the casing 122 can serve as a heat spreader to absorb and dissipate the heat from the first and second thermal paths T 1 and T 2 .
  • the casing 122 can accordingly be made from a thermally conductive material, such as nickel, copper, aluminum, ceramic materials with high thermal conductivities (e.g., aluminum nitride), and/or other suitable thermally conductive materials.
  • the outer portion 124 and the cap portion 126 can be joined together and to the underlying package substrate 130 using an adhesive 128 .
  • the adhesive 128 may be the same material as the underfill material 118 , a TIM (e.g., the TIM used for thermal transfer features 110 ), another thermally transmissive adhesive, and/or other suitable adhesive materials.
  • the casing 122 can be formed integrally and/or have other suitable cross-sectional shapes.
  • the casing 122 may include a heat sink (not shown) with a plurality of fins and/or other surface enhancing structures for enhanced heat dissipation.
  • FIG. 1 Several embodiments of the assembly 100 shown in FIG. 1 can provide enhanced thermal properties that lower the operating temperatures of the individual dies 102 , 106 in the assembly 100 such that they stay below their designated maximum temperatures (T max ).
  • T max maximum temperatures
  • the heat generated by the semiconductor dies is typically dispersed through a single thermal path provided by the die stack. Therefore, the heat generated at a peripheral portion of a larger underlying semiconductor die must travel laterally inward toward the die stack before being transferred vertically away from the underlying die. This extended thermal path results in a concentration of heat at the peripheral portion.
  • the larger underlying logic die typically operates at a much higher power level than the memory dies stacked above it (e.g., 5.24 W compared to 0.628 W), and therefore the logic die generates a significant amount of heat that concentrates at the peripheral portion.
  • the logic die may also have a higher power density at the peripheral portion, resulting in a further concentration of heat and temperature rise at the peripheral portion.
  • FIG. 2A is a schematic partial side view illustrating a temperature profile of a HMC assembly 200 a with stacked memory dies 202 and an underlying logic die 206 .
  • thermal energy is removed from a peripheral portion 208 of the logic die 206 along a thermal path (illustrated by arrow T) that first extends laterally inward toward a medial portion 231 of the logic die 206 and then vertically through the stacked memory dies 202 .
  • this single thermal path and the high power density of the logic die 206 (especially at the peripheral portion 208 ) concentrate thermal energy at the peripheral portion 208 .
  • FIG. 1 is a schematic partial side view illustrating a temperature profile of a HMC assembly 200 a with stacked memory dies 202 and an underlying logic die 206 .
  • the operational temperature of the logic die 206 is at its highest (e.g., above 113° C.) at the peripheral portion 208 of the logic die 206 , and may exceed the maximum operating temperature (T max ) of the logic die 206 .
  • FIG. 2B is a schematic partial side view illustrating a temperature profile of an HMC assembly 200 b configured in accordance with the present technology. As shown in FIG.
  • the stacked memory dies 202 provide a first thermal path (indicated by arrow T 1 ) that transfers heat vertically away from a medial portion 231 of the logic die 206 , and a thermal transfer feature 210 provides a second thermal path (indicated by arrow T 2 ) spaced laterally apart from the stacked memory dies 202 that transfers heat vertically away from a peripheral portion 208 of the logic die 206 .
  • the addition of the separate second thermal path T 2 which is thermally isolated from the first thermal path T 1 at the logic die 206 , can reduce the operational temperature at peripheral portion 208 of the logic die 206 (where the power density of the logic die 206 may be the highest), and the operating temperatures of the logic die 206 as a whole and/or the stacked memory dies 202 several degrees such that they can be maintained below their respective maximum operating temperatures (T max ).
  • T max maximum operating temperatures
  • the addition of the second thermal path T 2 lowers the operating temperature at the peripheral portion 208 of the logic die 206 from over 113° C. ( FIG. 2A ) to less than 93° C., and lowers the maximum temperature seen by the logic die 206 from over 113° C.
  • the addition of the thermal transfer feature 210 at the peripheral portion 208 of the logic die 206 can accordingly reduce the overall temperature of the logic die 206 within an acceptable range and below maximum temperature specifications.
  • FIG. 3 is a cross-sectional view of a semiconductor die assembly 300 (“assembly 300 ”) configured in accordance with other embodiments of the present technology.
  • the assembly 300 can include features generally similar to the features of the assembly 100 described above with reference to FIG. 1 .
  • the assembly 300 can include a plurality of first semiconductor dies 302 (e.g., memory dies) arranged in a stack 304 and a larger underlying second semiconductor die 306 (e.g., a high-speed logic die) carried by a package substrate 330 .
  • first semiconductor dies 302 e.g., memory dies
  • second semiconductor die 306 e.g., a high-speed logic die
  • the first semiconductor dies 302 are offset with respect to length on a forward-facing surface 312 of the second semiconductor die 306 such that a peripheral portion 308 of the second semiconductor die 306 extends laterally beyond one side of the first semiconductor dies 302 (e.g., a single side).
  • a thermal transfer feature 310 extends vertically from the peripheral portion 308 to an elevation corresponding to that of the outermost die 302 in the stack 304 .
  • the assembly 300 can therefore include a first thermal path (indicated by arrow T 1 ) provided by the stack 304 and a second thermal path (indicated by arrow T 2 ) provided by the thermal transfer feature 310 , and therefore allows heat to be removed vertically away from the peripheral portion 308 of the second semiconductor die 306 .
  • the peripheral portion 308 may also extend beyond the width of the first semiconductor dies 302 (from one or both sides) with the thermal transfer feature 310 positioned thereon.
  • the assembly 300 further includes a thermally conductive casing 322 (“casing 322 ”) attached to the package substrate 330 via an adhesive 328 (e.g., similar to the adhesive 128 of FIG. 1 ).
  • the casing 322 includes an outer portion 324 spaced laterally outward from the first and second semiconductor dies 302 and 306 and extending around the perimeter of the stacked semiconductor dies 302 , 306 .
  • the casing 322 may be configured to dissipate heat laterally or radially outward from the semiconductor dies 302 , 306 and vertically away from the assembly 300 .
  • the casing 322 can include a thermally conductive cap (e.g., the cap portion 126 of FIG. 1 ) and/or a second thermal transfer feature (e.g., the second thermal transfer feature 110 b of FIG. 1 ) that can be positioned on the stack 304 to further facilitate thermal energy transfer away from the stacked dies 302 , 306 .
  • a thermally conductive cap e.g., the cap portion 126 of FIG. 1
  • a second thermal transfer feature e.g., the second thermal transfer feature 110 b of FIG. 1
  • FIG. 4 is a partially schematic cross-sectional view of a semiconductor die assembly 400 (“assembly 400 ”) configured in accordance with further embodiments of the present technology.
  • the assembly 400 can include features generally similar to the features of the assemblies 100 , 300 shown in FIGS. 1 and 3 .
  • the assembly 400 can include a stack 404 of first semiconductor dies (shown schematically), a larger underlying second semiconductor die 406 , and a thermally conductive casing 422 (“casing 422 ”) extending at least partially around the stack 404 and the second semiconductor die 406 .
  • the assembly 400 can also include a first thermal transfer feature 410 a aligned with a peripheral portion 408 of the second semiconductor die 406 to facilitate thermal energy transfer directly from the peripheral portion 408 (e.g., rather than through the stack 404 ).
  • the first thermal transfer feature 410 a has a thickness (e.g., about 50 ⁇ m) such that the casing 422 interfaces with the first thermal transfer feature 410 a proximate to the peripheral portion 408 .
  • the first thermal transfer feature 410 a can be a thin pre-formed tab or may be deposited as a thin layer on a forward-facing surface 412 of the peripheral portion 408 .
  • An optional second thermal transfer feature 410 b can be spaced between the stack 404 and the casing 422 to facilitate heat transfer therebetween.
  • the first and second thermal transfer features 410 a and 410 b can have the same thickness, whereas in other embodiments their thicknesses may differ.
  • the casing 422 can be generally similar to the casing 122 described above with reference to FIG. 1 .
  • the casing 422 can be made from a thermally conductive material (e.g., copper) and can be attached to an underlying package substrate 430 with an adhesive 428 (e.g., an adhesive TIM).
  • the casing 422 can include a cavity 436 that is configured to at least generally surround or encase the perimeter of the die stack 404 and the second semiconductor die 406 .
  • the cavity 436 includes a notched or stepped portion 438 that extends around the peripheral portion 408 of the second semiconductor die 406 and a main cavity portion 439 that receives the die stack 404 .
  • the cavity 436 can also be configured such that the stepped portion 438 is spaced laterally outward from the second semiconductor die 406 on the package substrate 430 by a relatively small distance D (e.g., about 0.5 mm). This proximity to the second semiconductor die 406 can further enhance heat dissipation, as well as reduce the overall package size.
  • D relatively small distance
  • the casing 422 can be made from a metal material and the cavity 436 can be formed by a plurality of metal coining steps known to persons skilled in the art. This allows the cavity 436 to be customized for the particular arrangement of the stacked dies 402 , 406 , and may facilitate thermal management of 3D integration (3DI) multi-die packages.
  • the casing 422 can be formed using other suitable casing formation methods known to those skilled in the art.
  • the multi-tiered cavity 436 shown in FIG. 4 allows the casing 422 to thermally contact the first thermal transfer feature 410 a at the peripheral portion 408 of the second semiconductor die 406 , the second thermal transfer feature 410 b at the top of the stack 404 , and the package substrate 430 proximate the peripheral portion 408 .
  • the casing 422 can overlap the peripheral portion 408 of the second semiconductor die 406 by about 0.4-0.5 mm on each side.
  • This additional contact provides a greater surface area with which the casing 422 can transfer thermal energy and reduce the thermal resistance of the assembly 400 .
  • the casing 422 with the cavity 436 has been shown to reduce the operating temperature at the peripheral portion 408 of a HMC assembly by about 3-5° C. or more (e.g., 10° C.).
  • FIG. 5 is a partially schematic cross-sectional view of a semiconductor die assembly 500 (“assembly 500 ”) configured in accordance with still further embodiments of the present technology.
  • the assembly 500 can include features generally similar to the features of the assembly 400 described above with reference to FIG. 4 .
  • the assembly 500 can include a thermally conductive casing 522 (“casing 522 ”) having a cavity 536 that receives a die stack 504 and a second semiconductor die 506 .
  • the casing 522 can thermally contact a first thermal transfer feature 510 a at a peripheral portion 508 of the second semiconductor die 506 and a second thermal transfer feature 510 b at an upper portion of a die stack 504 .
  • the cavity 536 can also be configured to position the casing 522 proximate to the second semiconductor die 506 at a package substrate 530 to decrease the overall size of the package.
  • the casing 522 illustrated in FIG. 5 includes an outer portion 540 and one or more thermally conductive members 542 positioned within the cavity 536 of the outer portion 540 .
  • the outer portion 540 can extend around the die stack 504 and the second semiconductor die 506 such that it thermally couples to the top of the stack 504 (e.g., via the second thermal transfer feature 510 b ) and the underlying package substrate 530 (e.g., via a thermally transmissive adhesive 528 ).
  • the conductive members 542 can be pillars, cylinders, rectangular prisms, and/or other suitable structures spaced between the outer portion 540 and the first thermal transfer feature 510 a to direct thermal energy away from the peripheral portion 508 of the second semiconductor die 506 .
  • the outer portion 540 can be designed to have a generally standard shape and/or size, whereas the thermally conductive members 542 can be configured to adapt the standard outer portion 540 to a specific configuration of the stacked dies 504 , 506 .
  • the casing 522 shown in FIG. 5 can simplify manufacturing and provide a cavity 536 that closely fits the stack of semiconductor dies 504 , 506 to enhance heat transfer from the dies 504 , 506 .
  • FIG. 6 is a partially schematic cross-sectional view of a semiconductor die assembly 600 (“assembly 600 ”) configured in accordance with additional embodiments of the present technology.
  • the assembly 600 can include features generally similar to the features of the assemblies 400 and 500 described above with reference to FIGS. 4 and 5 .
  • the assembly 600 can include a package substrate 630 , a stack 604 of first semiconductor dies (shown schematically), a second semiconductor die 606 , and a thermally conductive casing 622 (“casing 622 ”) having a cavity 636 configured to receive the stack 604 .
  • casing 622 thermally conductive casing 622
  • the casing 622 terminates a distance from the package substrate 630 such that a base portion 644 of the casing 622 can overlap a peripheral portion 608 of the second semiconductor die 606 .
  • An adhesive 628 and/or other underfill material can be used to attach the casing 622 to the underlying package substrate 630 .
  • the casing 622 can thermally contact a first thermal transfer feature 610 a at the peripheral portion 608 of the second semiconductor die 606 and a second thermal transfer feature 610 b at the top of the die stack 604 to provide separate thermal paths (as indicated by the arrows) through which heat can be absorbed and spread through the casing 622 .
  • the casing 622 can therefore have a substantially standardized cavity shape around the stack 604 , but still provide thermal contact proximate the peripheral portion 608 of the second semiconductor die 606 to facilitate heat dissipation from the second semiconductor die 606 .
  • FIG. 7 is a partially schematic cross-sectional view of a semiconductor die assembly 700 (“assembly 700 ”) configured in accordance with other embodiments of the present technology.
  • the assembly 700 can include features generally similar to the features of the assemblies 400 , 500 , 600 described above with reference to FIGS. 4-6 , such as a stack 704 of first semiconductor dies (shown schematically) carried by a second semiconductor die 706 having a larger footprint than that of the stack 704 .
  • the assembly 700 includes a thermally conductive casing 722 (“casing 722 ”) having a cavity 736 and one or more flanges 746 extending laterally into the cavity 736 .
  • the flange 746 can be in thermal contact with a first thermal transfer feature 710 a at a peripheral portion 708 of the second semiconductor die 706
  • an underside 748 of the casing 722 can in thermal contact with a second thermal transfer feature 710 b on the stack 704 .
  • the casing 722 therefore provides an increased thermal contact area with at least two separate thermal paths, one being directed laterally outward via the flanged portion 746 and another being directed vertically through the die stack 704 to the casing 722 .
  • the assembly 700 can reduce the concentration of heat at the peripheral portion 708 of the second semiconductor die 706 and reduce the operating temperature of the second semiconductor die 706 .
  • any one of the stacked semiconductor die assemblies described above with reference to FIGS. 1-7 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 800 shown schematically in FIG. 8 .
  • the system 800 can include a semiconductor die assembly 810 , a power source 820 , a driver 830 , a processor 840 , and/or other subsystems or components 850 .
  • the semiconductor die assembly 810 can include features generally similar to those of the stacked semiconductor die assemblies described above, and can therefore include multiple thermal paths that enhance heat dissipation.
  • the resulting system 800 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions.
  • representative systems 800 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances.
  • Components of the system 800 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network).
  • the components of the system 800 can also include remote devices and any of a wide variety of computer readable media.
  • the semiconductor die assemblies can be configured as other memory devices or other types of stacked die assemblies.
  • the semiconductor die assemblies illustrated in FIGS. 1-7 include a plurality of first semiconductor dies arranged in a stack on the second semiconductor die. In other embodiments, however, the semiconductor die assemblies can include one first semiconductor die stacked on the second semiconductor die. Certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments.

Abstract

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. application Ser. No. 13/613,540 filed Sep. 13, 2012, which claims priority to U.S. Provisional Application No. 61/559,659 filed Nov. 14, 2011, and U.S. Provisional Application No. 61/559,664 filed Nov. 14, 2011, each of which is incorporated herein by reference in its entirety. This application is directed to subject matter related to that disclosed in U.S. application Ser. No. 13/307,591 filed concurrently herewith, which is commonly owned and which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
The disclosed embodiments relate to semiconductor die assemblies. In particular, the present technology relates to stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods.
BACKGROUND
Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
Market pressures continually drive semiconductor manufacturers to reduce the size of die packages to fit within the space constraints of electronic devices, while also pressuring them to increase the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies using through-silicon vias (TSVs).
A challenge associated with vertically stacked die packages is that the heat generated by the individual dies combines and increases the operating temperatures of the individual dies, the junctions therebetween, and the package as a whole. This can cause the stacked dies to reach temperatures above their maximum operating temperatures (Tmax), especially as the density of the dies in the package increases.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a semiconductor die assembly configured in accordance with embodiments of the present technology.
FIG. 2A is a schematic partial side view illustrating a temperature profile of a hybrid memory cube assembly without multiple thermal paths.
FIG. 2B is a schematic partial side view illustrating a temperature profile of a hybrid memory cube assembly configured in accordance with embodiments of the present technology.
FIG. 3 is a cross-sectional view of a semiconductor die assembly configured in accordance with other embodiments of the present technology.
FIG. 4 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with further embodiments of the present technology.
FIG. 5 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with still further embodiments of the present technology.
FIG. 6 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with additional embodiments of the present technology.
FIG. 7 is a partially schematic cross-sectional view of a semiconductor die assembly configured in accordance with other embodiments of the present technology.
FIG. 8 is a schematic view of a system that includes a semiconductor die assembly configured in accordance with embodiments of the present technology.
DETAILED DESCRIPTION
Specific details of several embodiments of stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are described below. The term “semiconductor die” generally refers to a die having integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. For example, semiconductor dies can include integrated circuit memory and/or logic circuitry. Semiconductor dies and/or other features in semiconductor die packages can be said to be in “thermal contact” with one another if the two structures can exchange energy through heat. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to FIGS. 1-8.
As used herein, the terms “vertical,” “lateral,” “upper” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations.
FIG. 1 is a cross-sectional view of a semiconductor die assembly 100 (“assembly 100”) configured in accordance with embodiments of the present technology. The assembly 100 can include one or a plurality of first semiconductor dies 102 arranged in a stack 104 on a second semiconductor die 106 and carried by a package substrate 130. As shown in FIG. 1, the second semiconductor die 106 can have a larger footprint than the stacked first semiconductor dies 102. The second semiconductor die 106, therefore, includes a peripheral portion 108 extending laterally outward beyond at least one side of the first semiconductor dies 102 (e.g., beyond the length and/or width of the first semiconductor dies 102). The assembly 100 can further include a first thermal transfer feature 110 a at the peripheral portion 108 of the second semiconductor die 106 and an optional second thermal transfer feature 110 b superimposed with the first semiconductor dies 102. During operation, thermal energy can flow away from the second semiconductor die 106 through the first semiconductor dies 102 via a first thermal path (e.g., as illustrated by arrow T1) and through the first thermal transfer feature 110 a via a second thermal path (e.g., illustrated by arrows T2) separate from the first thermal path T1. The second thermal path T2 of the embodiment shown in FIG. 1 is accordingly spaced laterally apart from the perimeter edges of the first semiconductor dies 102.
The first and second semiconductor dies 102 and 106 (collectively referred to as “ dies 102, 106”) can include various types of semiconductor components and functional features, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuits, imaging components, and/or other semiconductor features. In various embodiments, for example, the assembly 100 can be configured as a hybrid memory cube (HMC) in which the stacked first semiconductor dies 102 are DRAM dies or other memory dies that provide data storage and the second semiconductor die 106 is a high-speed logic die that provides memory control (e.g., DRAM control) within the HMC. In other embodiments, the first and second semiconductor dies 102 and 106 may include other semiconductor components and/or the semiconductor components of the individual first semiconductor dies 102 in the stack 104 may differ.
The dies 102, 106 can be rectangular, circular, and/or other suitable shapes and may have various different dimensions. For example, the individual first semiconductor dies 102 can each have a length L1 of about 10-11 mm (e.g., 10.7 mm) and a width of about 8-9 mm (e.g., 8.6 mm, 8.7 mm). The second semiconductor die 106 can have a length L2 of about 12-13 mm (e.g., 12.67 mm) and a width of about 8-9 mm (e.g., 8.5 mm, 8.6 mm, etc.). In other embodiments, the first and second semiconductor dies 102 and 106 can have other suitable dimensions and/or the individual first semiconductor dies 102 may have different dimensions from one another.
The peripheral portion 108 (known to those skilled in the art as a “porch” or “shelf”) of the second semiconductor die 106 can be defined by the relative dimensions of the first and second semiconductor dies 102 and 106 and the position of the stack 104 on a forward-facing surface 112 of the second semiconductor die 106. In the embodiment illustrated in FIG. 1, the stack 104 is centered with respect to the length L2 of the second semiconductor die 106 such that the peripheral portion 108 extends laterally beyond two opposite sides of the stack 104. For example, if the length L2 of the second semiconductor die 106 is about 1.0 mm greater than the length L1 of the first semiconductor dies 102, the peripheral portion 108 will extend about 0.5 mm beyond either side of the centered first semiconductor dies 102. The stack 104 may also be centered with respect to the width of the second semiconductor die 106 and, in embodiments where both the width and length of the second semiconductor die 106 are greater than those of the centered stack 104, the peripheral portion 108 may extend around the entire perimeter of the first semiconductor dies 102. In other embodiments, the stack 104 may be offset with respect to the forward-facing surface 112 of the second semiconductor die 106 and/or the peripheral portion 108 of the second semiconductor die 106 may extend around less than the full perimeter of the stack 104. In further embodiments, the first and second semiconductor dies 102 and 106 can be circular, and therefore the relative diameters of the first and second semiconductor dies 102 and 106 define the peripheral portion 108.
As shown in FIG. 1, the first semiconductor dies 102 can be electrically coupled to one another in the stack 104 and to the underlying second semiconductor die 106 by a plurality of electrically conductive elements 114 positioned between adjacent dies 102, 106. Although the stack 104 shown in FIG. 1 includes eight first semiconductor dies 102 electrically coupled together, in other embodiments the stack 104 can include fewer than eight dies (e.g., three dies, four dies, etc.) or more than eight dies (e.g., ten dies, twelve dies, etc.). The electrically conductive elements 114 can have various suitable structures, such as pillars, columns, studs, bumps, and can be made from copper, nickel, solder (e.g., SnAg-based solder), conductor-filled epoxy, and/or other electrically conductive materials. In selected embodiments, for example, the electrically conductive elements 114 can be copper pillars, whereas in other embodiments the electrically conductive elements 114 can include more complex structures, such as bump-on-nitride structures.
As further shown in FIG. 1, the individual first semiconductor dies 102 can each include a plurality of TSVs 116 aligned on one or both sides with corresponding electrically conductive elements 114 to provide electrical connections at opposing sides of the first semiconductor dies 102. Each TSV 116 can include an electrically conductive material (e.g., copper) that passes completely through the individual first semiconductor dies 102 and an electrically insulative material surrounding the electrically conductive material to electrically isolate the TSVs 116 from the remainder of the die 102. Though not shown in FIG. 1, the second semiconductor die 106 can also include a plurality of TSVs 116 to electrically couple the second semiconductor die 106 to higher level circuitry. Beyond electrical communication, the TSVs 116 and the electrically conductive elements 114 can serve as thermal conduits through which heat can be transferred away from the first and second semiconductor dies 102 and 106 (e.g., through the first thermal path T1). In some embodiments, the dimensions of the electrically conductive elements 114 and/or the TSVs 116 can be increased to enhance thermal contact conductance of the stack 104. For example, the individual electrically conductive elements 114 can each have a diameter of about 15-30 μm or other suitable dimensions to enhance the thermal path away from the dies 102, 106. In other embodiments, the first semiconductor dies 102 can be electrically coupled to one another and to the second semiconductor die 106 using other types of electrical connectors (e.g., wirebonds) that may also serve as thermal pathways through the stack 104.
A dielectric underfill material 118 can be deposited or otherwise formed around and/or between the first and second semiconductor dies 102 and 106 to electrically isolate the electrically conductive elements 114 and/or enhance the mechanical connection between the semiconductor dies 102, 106. The underfill material 118 can be a non-conductive epoxy paste (e.g., XS8448-171 manufactured by Namics Corporation of Niigata, Japan), a capillary underfill, a non-conductive film, a molded underfill, and/or include other suitable electrically-insulative materials. In some embodiments, the underfill material 118 can be selected based on its thermal conductivity to enhance heat dissipation through the stack 104.
In various embodiments, the assembly 100 may also include a plurality of thermally conductive elements 120 (shown in broken lines) positioned interstitially between the electrically conductive elements 114. The individual thermally conductive elements 120 can be at least generally similar in structure and composition as that of the electrically conductive elements 114 (e.g., copper pillars). However, the thermally conductive elements 120 are not electrically coupled to the TSVs 116, and therefore do not provide electrical connections between the first semiconductor dies 102. Instead, the thermally conductive elements 120 serve to increase the overall thermal conductivity of the stack 104, thereby facilitating heat transfer through the stack 104 (e.g., along the first thermal path T1). For example, in embodiments where the assembly 100 is configured as a HMC, the addition of the thermally conductive elements 120 between the electrically conductive elements 114 has been shown to decrease the operating temperature of the HMC by several degrees (e.g., about 6-7° C.).
As shown in FIG. 1, the package substrate 130 can provide the dies 102, 106 with electrical connections to external electrical components (e.g., higher-level packaging; not shown). For example, the package substrate 130 can be an interposer or printed circuit board that includes semiconductor components (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive components (e.g., various ceramic substrates, such as aluminum oxide (Al2O3), aluminum nitride (AlN), etc.), and/or conductive portions (e.g., interconnecting circuitry, TSVs, etc.). In the embodiment illustrated in FIG. 1, the package substrate 130 is electrically coupled to the second semiconductor die 106 at a first side 132 a of the package substrate 130 via a first plurality of electrical connectors 134 a and to external circuitry (not shown) at a second side 132 b of the package substrate 130 via a second plurality of electrical connectors 134 b (collectively referred to as “the electrical connectors 134”). The electrical connectors 134 can be solder balls, conductive bumps and pillars, conductive epoxies, and/or other suitable electrically conductive elements. A dielectric underfill (e.g., FP4585 manufactured by Henkel of Diisseldorf, Germany; not shown) can be spaced between the second semiconductor die 106 and the package substrate 130 for enhanced mechanical connection and electrical isolation of the first plurality of electrical connectors 134 a. In various embodiments, the package substrate 130 can be made from a material with a relatively high thermal conductivity to enhance heat dissipation at the back side of the second semiconductor die 106.
As discussed above, the first thermal transfer feature 110 a can thermally contact the peripheral portion 108 of the second semiconductor die 106 to remove heat along the second thermal path T2, and the second thermal transfer feature 110 b can thermally contact the uppermost die 102 in the stack 104 to remove heat along the first thermal path T1. In the embodiment illustrated in FIG. 1, the first thermal transfer feature 110 a has a pillar-like structure that extends vertically from the peripheral portion 108 to an elevation generally corresponding to that of the outermost die 102 in the stack 104 to define a substantially vertical thermal path from which heat can be removed from the peripheral portion 108. As shown in FIG. 1, the underfill material 118 and/or other thermally transmissive materials may be spaced between the first thermal transfer feature 110 a and the peripheral portion 108 (e.g., for adhesive purposes). In other embodiments, the first thermal transfer feature 110 a can extend vertically a lesser or greater elevation with respect to the elevation of the stacked first semiconductor dies 102 to define other vertical thermal paths. As described in greater detail below, in other embodiments the first thermal transfer feature 110 a can have different configurations and may define thermal paths that transfer heat laterally outward (i.e., rather than vertically away) from the peripheral portion 108.
In the illustrated embodiment, the second thermal transfer feature 110 b extends across a forward-facing surface 111 of the first semiconductor die 102 spaced furthest from the second semiconductor die 106 (e.g., the uppermost die 102 in the stack 104). The second thermal transfer feature 110 b can therefore absorb heat directly from the stack 104 (e.g., through the electrically conductive elements 114 and TSVs 116) and transfer it away from the dies 102, 106. In other embodiments, the second thermal transfer element 110 b can have other suitable configurations, and/or the first and second thermal transfer elements 110 a and 110 b can be an integral structure formed on the peripheral portion 108 and over the stack 104. In further embodiments, the second thermal transfer feature 110 a can be omitted.
The thermal transfer features 110 can be made from materials with relatively high thermal conductivities to increase the thermal conductance of heat away from the dies 102, 106. For example, the first thermal transfer feature 110 a can be made from blank silicon, which can have a thermal conductivity dependent on temperature (e.g., about 149 W/m° K at 25° C. and/or about 105 W/m ° K at 100° C.). In other embodiments, the first and/or second thermal transfer features 110 can be made from what are known in the art as “thermal interface materials” or “TIMs”, which are designed to increase the thermal contact conductance at surface junctions (e.g., between a die surface and a heat spreader). TIMs can include silicone-based greases, gels, or adhesives that are doped with conductive materials (e.g., carbon nano-tubes, solder materials, diamond-like carbon (DLC), etc.), as well as phase-change materials. In some embodiments, for example, the second thermal transfer feature 110 b can be made from X-23-7772-4 TIM manufactured by Shin-Etsu MicroSi, Inc. of Phoenix, Ariz., which has a thermal conductivity of about 3-4 W/m° K. In other embodiments, the thermal transfer features 110 can be made from metals (e.g., copper) and/or other suitable thermally conductive materials.
In various embodiments, the thermal transfer features 110 can be pre-formed members (e.g., pads, pillars, and/or other suitable structures) that can be attached to the peripheral portion 108 of the second semiconductor die 106 and/or superimposed with the first semiconductor dies 102 (e.g., via a thermally transmissive adhesive, curing, etc.). In other embodiments, the thermal transfer features 110 may be deposited or otherwise formed on the forward-facing surface 112 of the peripheral portion 108 and/or on the forward-facing surface 111 of the stack 104 using formation methods known to those in the art, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).
As shown in FIG. 1, the first and second thermal transfer features 110 a and 110 b can thermally contact a thermally conductive casing 122 (“casing 122”) that extends at least partially around the first and second semiconductor dies 102 and 106. The casing 122 can include an outer portion 124 spaced laterally apart from the second semiconductor die 106 on the package substrate 130 and a cap portion 126 carried by the outer portion 124. In the illustrated embodiment, the outer portion 124 and the cap portion 126 form a recess 136 configured such that both the vertically-extending first thermal transfer feature 110 a and the second thermal transfer feature 110 b thermally contact an underside of the cap portion 126. In other embodiments, however, the casing 122 and/or the thermal transfer features 110 can have other suitable configurations such that the thermal transfer features 110 thermally contact other portions of the casing 122.
The casing 122 can serve as a heat spreader to absorb and dissipate the heat from the first and second thermal paths T1 and T2. The casing 122 can accordingly be made from a thermally conductive material, such as nickel, copper, aluminum, ceramic materials with high thermal conductivities (e.g., aluminum nitride), and/or other suitable thermally conductive materials. As shown in FIG. 1, the outer portion 124 and the cap portion 126 can be joined together and to the underlying package substrate 130 using an adhesive 128. The adhesive 128 may be the same material as the underfill material 118, a TIM (e.g., the TIM used for thermal transfer features 110), another thermally transmissive adhesive, and/or other suitable adhesive materials. In other embodiments, the casing 122 can be formed integrally and/or have other suitable cross-sectional shapes. In various embodiments, the casing 122 may include a heat sink (not shown) with a plurality of fins and/or other surface enhancing structures for enhanced heat dissipation.
Several embodiments of the assembly 100 shown in FIG. 1 can provide enhanced thermal properties that lower the operating temperatures of the individual dies 102, 106 in the assembly 100 such that they stay below their designated maximum temperatures (Tmax). In conventional stacked semiconductor die packages, the heat generated by the semiconductor dies is typically dispersed through a single thermal path provided by the die stack. Therefore, the heat generated at a peripheral portion of a larger underlying semiconductor die must travel laterally inward toward the die stack before being transferred vertically away from the underlying die. This extended thermal path results in a concentration of heat at the peripheral portion. In addition, when the assembly 100 is arranged as a HMC, the larger underlying logic die typically operates at a much higher power level than the memory dies stacked above it (e.g., 5.24 W compared to 0.628 W), and therefore the logic die generates a significant amount of heat that concentrates at the peripheral portion. The logic die may also have a higher power density at the peripheral portion, resulting in a further concentration of heat and temperature rise at the peripheral portion.
FIG. 2A, for example, is a schematic partial side view illustrating a temperature profile of a HMC assembly 200 a with stacked memory dies 202 and an underlying logic die 206. As shown in FIG. 2A, thermal energy is removed from a peripheral portion 208 of the logic die 206 along a thermal path (illustrated by arrow T) that first extends laterally inward toward a medial portion 231 of the logic die 206 and then vertically through the stacked memory dies 202. During operation, this single thermal path and the high power density of the logic die 206 (especially at the peripheral portion 208) concentrate thermal energy at the peripheral portion 208. In the embodiment illustrated in FIG. 2A, for example, the operational temperature of the logic die 206 is at its highest (e.g., above 113° C.) at the peripheral portion 208 of the logic die 206, and may exceed the maximum operating temperature (Tmax) of the logic die 206.
The assembly 100 shown in FIG. 1 is expected to avoid the problems of other stacked semiconductor die packages by providing an additional thermal path at the peripheral portion 108 of the second semiconductor die 106, and thereby promotes heat dissipation directly away from the peripheral portion 108. FIG. 2B, for example, is a schematic partial side view illustrating a temperature profile of an HMC assembly 200 b configured in accordance with the present technology. As shown in FIG. 2B, the stacked memory dies 202 provide a first thermal path (indicated by arrow T1) that transfers heat vertically away from a medial portion 231 of the logic die 206, and a thermal transfer feature 210 provides a second thermal path (indicated by arrow T2) spaced laterally apart from the stacked memory dies 202 that transfers heat vertically away from a peripheral portion 208 of the logic die 206. The addition of the separate second thermal path T2, which is thermally isolated from the first thermal path T1 at the logic die 206, can reduce the operational temperature at peripheral portion 208 of the logic die 206 (where the power density of the logic die 206 may be the highest), and the operating temperatures of the logic die 206 as a whole and/or the stacked memory dies 202 several degrees such that they can be maintained below their respective maximum operating temperatures (Tmax). In the embodiment illustrated in FIG. 2B, for example, the addition of the second thermal path T2 lowers the operating temperature at the peripheral portion 208 of the logic die 206 from over 113° C. (FIG. 2A) to less than 93° C., and lowers the maximum temperature seen by the logic die 206 from over 113° C. (FIG. 2A) to less than 100° C. (now moved to the medial portion 231). In addition, the overall change in temperature (ΔT) across the logic die 206 may also be decreased (e.g., from about ΔT=19° C. to about ΔT=4.5° C.). The addition of the thermal transfer feature 210 at the peripheral portion 208 of the logic die 206 can accordingly reduce the overall temperature of the logic die 206 within an acceptable range and below maximum temperature specifications.
FIG. 3 is a cross-sectional view of a semiconductor die assembly 300 (“assembly 300”) configured in accordance with other embodiments of the present technology. The assembly 300 can include features generally similar to the features of the assembly 100 described above with reference to FIG. 1. For example, the assembly 300 can include a plurality of first semiconductor dies 302 (e.g., memory dies) arranged in a stack 304 and a larger underlying second semiconductor die 306 (e.g., a high-speed logic die) carried by a package substrate 330. In the illustrated embodiment, the first semiconductor dies 302 are offset with respect to length on a forward-facing surface 312 of the second semiconductor die 306 such that a peripheral portion 308 of the second semiconductor die 306 extends laterally beyond one side of the first semiconductor dies 302 (e.g., a single side). A thermal transfer feature 310 extends vertically from the peripheral portion 308 to an elevation corresponding to that of the outermost die 302 in the stack 304. The assembly 300 can therefore include a first thermal path (indicated by arrow T1) provided by the stack 304 and a second thermal path (indicated by arrow T2) provided by the thermal transfer feature 310, and therefore allows heat to be removed vertically away from the peripheral portion 308 of the second semiconductor die 306. Though not shown in FIG. 3, the peripheral portion 308 may also extend beyond the width of the first semiconductor dies 302 (from one or both sides) with the thermal transfer feature 310 positioned thereon.
In the embodiment illustrated in FIG. 3, the assembly 300 further includes a thermally conductive casing 322 (“casing 322”) attached to the package substrate 330 via an adhesive 328 (e.g., similar to the adhesive 128 of FIG. 1). Rather than extending over the first and second semiconductor dies 302 and 306, the casing 322 includes an outer portion 324 spaced laterally outward from the first and second semiconductor dies 302 and 306 and extending around the perimeter of the stacked semiconductor dies 302, 306. The casing 322 may be configured to dissipate heat laterally or radially outward from the semiconductor dies 302, 306 and vertically away from the assembly 300. In other embodiments, the casing 322 can include a thermally conductive cap (e.g., the cap portion 126 of FIG. 1) and/or a second thermal transfer feature (e.g., the second thermal transfer feature 110 b of FIG. 1) that can be positioned on the stack 304 to further facilitate thermal energy transfer away from the stacked dies 302, 306.
FIG. 4 is a partially schematic cross-sectional view of a semiconductor die assembly 400 (“assembly 400”) configured in accordance with further embodiments of the present technology. The assembly 400 can include features generally similar to the features of the assemblies 100, 300 shown in FIGS. 1 and 3. For example, the assembly 400 can include a stack 404 of first semiconductor dies (shown schematically), a larger underlying second semiconductor die 406, and a thermally conductive casing 422 (“casing 422”) extending at least partially around the stack 404 and the second semiconductor die 406. The assembly 400 can also include a first thermal transfer feature 410 a aligned with a peripheral portion 408 of the second semiconductor die 406 to facilitate thermal energy transfer directly from the peripheral portion 408 (e.g., rather than through the stack 404). Instead of extending vertically from the peripheral portion 408 to an elevation corresponding to the full height of the stack 404, the first thermal transfer feature 410 a has a thickness (e.g., about 50 μm) such that the casing 422 interfaces with the first thermal transfer feature 410 a proximate to the peripheral portion 408. For example, the first thermal transfer feature 410 a can be a thin pre-formed tab or may be deposited as a thin layer on a forward-facing surface 412 of the peripheral portion 408. An optional second thermal transfer feature 410 b can be spaced between the stack 404 and the casing 422 to facilitate heat transfer therebetween. In various embodiments, the first and second thermal transfer features 410 a and 410 b can have the same thickness, whereas in other embodiments their thicknesses may differ.
The casing 422 can be generally similar to the casing 122 described above with reference to FIG. 1. For example, the casing 422 can be made from a thermally conductive material (e.g., copper) and can be attached to an underlying package substrate 430 with an adhesive 428 (e.g., an adhesive TIM). However, as shown in FIG. 4, the casing 422 can include a cavity 436 that is configured to at least generally surround or encase the perimeter of the die stack 404 and the second semiconductor die 406. In the illustrated embodiment, for example, the cavity 436 includes a notched or stepped portion 438 that extends around the peripheral portion 408 of the second semiconductor die 406 and a main cavity portion 439 that receives the die stack 404. As shown in FIG. 4, the cavity 436 can also be configured such that the stepped portion 438 is spaced laterally outward from the second semiconductor die 406 on the package substrate 430 by a relatively small distance D (e.g., about 0.5 mm). This proximity to the second semiconductor die 406 can further enhance heat dissipation, as well as reduce the overall package size.
In various embodiments, the casing 422 can be made from a metal material and the cavity 436 can be formed by a plurality of metal coining steps known to persons skilled in the art. This allows the cavity 436 to be customized for the particular arrangement of the stacked dies 402, 406, and may facilitate thermal management of 3D integration (3DI) multi-die packages. In other embodiments, the casing 422 can be formed using other suitable casing formation methods known to those skilled in the art.
Unlike conventional thermally conductive casings, lids or caps that only contact the underlying device at the package substrate (e.g., through a polymeric adhesive or solder alloy) and at the top of the die stack, the multi-tiered cavity 436 shown in FIG. 4 allows the casing 422 to thermally contact the first thermal transfer feature 410 a at the peripheral portion 408 of the second semiconductor die 406, the second thermal transfer feature 410 b at the top of the stack 404, and the package substrate 430 proximate the peripheral portion 408. In various embodiments, for example, the casing 422 can overlap the peripheral portion 408 of the second semiconductor die 406 by about 0.4-0.5 mm on each side. This additional contact provides a greater surface area with which the casing 422 can transfer thermal energy and reduce the thermal resistance of the assembly 400. For example, the casing 422 with the cavity 436 has been shown to reduce the operating temperature at the peripheral portion 408 of a HMC assembly by about 3-5° C. or more (e.g., 10° C.).
FIG. 5 is a partially schematic cross-sectional view of a semiconductor die assembly 500 (“assembly 500”) configured in accordance with still further embodiments of the present technology. The assembly 500 can include features generally similar to the features of the assembly 400 described above with reference to FIG. 4. For example, the assembly 500 can include a thermally conductive casing 522 (“casing 522”) having a cavity 536 that receives a die stack 504 and a second semiconductor die 506. The casing 522 can thermally contact a first thermal transfer feature 510 a at a peripheral portion 508 of the second semiconductor die 506 and a second thermal transfer feature 510 b at an upper portion of a die stack 504. The cavity 536 can also be configured to position the casing 522 proximate to the second semiconductor die 506 at a package substrate 530 to decrease the overall size of the package.
Rather than an integrally formed casing, the casing 522 illustrated in FIG. 5 includes an outer portion 540 and one or more thermally conductive members 542 positioned within the cavity 536 of the outer portion 540. The outer portion 540 can extend around the die stack 504 and the second semiconductor die 506 such that it thermally couples to the top of the stack 504 (e.g., via the second thermal transfer feature 510 b) and the underlying package substrate 530 (e.g., via a thermally transmissive adhesive 528). The conductive members 542 can be pillars, cylinders, rectangular prisms, and/or other suitable structures spaced between the outer portion 540 and the first thermal transfer feature 510 a to direct thermal energy away from the peripheral portion 508 of the second semiconductor die 506. During manufacture, the outer portion 540 can be designed to have a generally standard shape and/or size, whereas the thermally conductive members 542 can be configured to adapt the standard outer portion 540 to a specific configuration of the stacked dies 504, 506. As such, the casing 522 shown in FIG. 5 can simplify manufacturing and provide a cavity 536 that closely fits the stack of semiconductor dies 504, 506 to enhance heat transfer from the dies 504, 506.
FIG. 6 is a partially schematic cross-sectional view of a semiconductor die assembly 600 (“assembly 600”) configured in accordance with additional embodiments of the present technology. The assembly 600 can include features generally similar to the features of the assemblies 400 and 500 described above with reference to FIGS. 4 and 5. For example, the assembly 600 can include a package substrate 630, a stack 604 of first semiconductor dies (shown schematically), a second semiconductor die 606, and a thermally conductive casing 622 (“casing 622”) having a cavity 636 configured to receive the stack 604. However, in the embodiment illustrated in FIG. 6, the casing 622 terminates a distance from the package substrate 630 such that a base portion 644 of the casing 622 can overlap a peripheral portion 608 of the second semiconductor die 606. An adhesive 628 and/or other underfill material can be used to attach the casing 622 to the underlying package substrate 630. As shown in FIG. 6, the casing 622 can thermally contact a first thermal transfer feature 610 a at the peripheral portion 608 of the second semiconductor die 606 and a second thermal transfer feature 610 b at the top of the die stack 604 to provide separate thermal paths (as indicated by the arrows) through which heat can be absorbed and spread through the casing 622. The casing 622 can therefore have a substantially standardized cavity shape around the stack 604, but still provide thermal contact proximate the peripheral portion 608 of the second semiconductor die 606 to facilitate heat dissipation from the second semiconductor die 606.
FIG. 7 is a partially schematic cross-sectional view of a semiconductor die assembly 700 (“assembly 700”) configured in accordance with other embodiments of the present technology. The assembly 700 can include features generally similar to the features of the assemblies 400, 500, 600 described above with reference to FIGS. 4-6, such as a stack 704 of first semiconductor dies (shown schematically) carried by a second semiconductor die 706 having a larger footprint than that of the stack 704. In the illustrated embodiment, the assembly 700 includes a thermally conductive casing 722 (“casing 722”) having a cavity 736 and one or more flanges 746 extending laterally into the cavity 736. The flange 746 can be in thermal contact with a first thermal transfer feature 710 a at a peripheral portion 708 of the second semiconductor die 706, and an underside 748 of the casing 722 can in thermal contact with a second thermal transfer feature 710 b on the stack 704. The casing 722 therefore provides an increased thermal contact area with at least two separate thermal paths, one being directed laterally outward via the flanged portion 746 and another being directed vertically through the die stack 704 to the casing 722. As such, the assembly 700 can reduce the concentration of heat at the peripheral portion 708 of the second semiconductor die 706 and reduce the operating temperature of the second semiconductor die 706.
Any one of the stacked semiconductor die assemblies described above with reference to FIGS. 1-7 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system 800 shown schematically in FIG. 8. The system 800 can include a semiconductor die assembly 810, a power source 820, a driver 830, a processor 840, and/or other subsystems or components 850. The semiconductor die assembly 810 can include features generally similar to those of the stacked semiconductor die assemblies described above, and can therefore include multiple thermal paths that enhance heat dissipation. The resulting system 800 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems 800 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of the system 800 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 800 can also include remote devices and any of a wide variety of computer readable media.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, although many of the embodiments of the semiconductor dies assemblies are described with respect to HMCs, in other embodiments the semiconductor die assemblies can be configured as other memory devices or other types of stacked die assemblies. In addition, the semiconductor die assemblies illustrated in FIGS. 1-7 include a plurality of first semiconductor dies arranged in a stack on the second semiconductor die. In other embodiments, however, the semiconductor die assemblies can include one first semiconductor die stacked on the second semiconductor die. Certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

Claims (16)

We claim:
1. A method of forming a semiconductor die assembly, the method comprising:
electrically coupling a plurality of first semiconductor dies together in a single stack;
electrically coupling the single stack of first semiconductor dies to a second semiconductor die such that the stack of first semiconductor dies is centered with respect to the second semiconductor die along at least one axis, the second semiconductor die having a peripheral portion that extends laterally outward beyond at least one side of the stack of first semiconductor dies, and wherein the stack of first semiconductor dies forms a first thermal path that transfers heat away from the second semiconductor die;
depositing an underfill material between the first semiconductor dies, wherein the underfill material extends from between the first semiconductor dies onto the peripheral portion of the second semiconductor die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the second semiconductor die adjacent to at most a first side and a second side of the single stack of first semiconductor dies and spaced laterally apart from the at most first and second sides of the single stack of first semiconductor dies, wherein the thermal transfer feature is a blank silicon member, and wherein the thermal transfer feature forms a second thermal path away from the second semiconductor die that is separate from the first thermal path; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation generally corresponding to that of a topmost one of the first semiconductor dies in the stack of first semiconductor dies, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation generally corresponding to that of the topmost one of the first semiconductor dies.
2. The method of claim 1 wherein:
the first semiconductor dies are memory dies; and
electrically coupling the stack of first semiconductor dies to the second semiconductor die comprises electrically coupling the stack of memory dies to a logic die.
3. The method of claim 1 wherein disposing the thermally conductive casing includes disposing the thermally conductive casing around at least a portion of the first and second semiconductor dies, and wherein the thermally conductive casing includes a cavity configured to receive at least a portion of the first and second semiconductor dies.
4. The method of claim 1, further comprising:
electrically coupling the second semiconductor die to a package substrate; and
thermally contacting a base portion of the thermally conductive casing with the package substrate.
5. The method of claim 1 wherein the thermal transfer feature is a first thermal transfer feature, and wherein the method further comprises superimposing a second thermal transfer feature with the first semiconductor dies.
6. The method of claim 5 wherein superimposing the second thermal transfer feature with the first semiconductor dies comprises positioning an upper surface of the second thermal transfer feature to be generally coplanar with an upper surface of the first thermal transfer feature, and wherein the method further comprises thermally contacting the thermally conductive casing with the upper surface of the second thermal transfer feature.
7. The method of claim 5 wherein the second thermal transfer feature is a blank silicon member.
8. The method of claim 1, further comprising forming a plurality of thermally conductive elements extending between the first and second semiconductor dies, wherein the thermally conductive elements are electrically isolated from the first and second semiconductor dies.
9. A method of forming a semiconductor die assembly, the method comprising:
electrically coupling a plurality of memory dies together in a single stack;
electrically coupling the single stack of memory dies to a logic die such that the stack of memory dies is centered with respect to the logic die along at least one axis, wherein the logic die includes a peripheral portion extending laterally outward beyond at least one side of the memory dies;
depositing an underfill material between the memory dies, wherein the underfill material extends from between the memory dies onto the peripheral portion of the logic die;
adhering, via the underfill material, a thermal transfer feature to the peripheral portion of the logic die adjacent to at most a first side and a second side of the single stack of memory dies and spaced laterally apart from the at most first and second sides of the stack of memory dies, wherein the thermal transfer feature is a blank silicon member, wherein the memory dies and the thermal transfer feature provide separate thermal paths that transfer heat away from the logic die; and
thermally contacting a thermally conductive casing with the thermal transfer feature at an elevation proximate that of the memory die spaced farthest from the logic die, wherein the blank silicon member extends continuously vertically from the underfill material on the peripheral portion to the elevation proximate that of the memory die spaced farthest from the logic die.
10. The method of claim 9 wherein electrically coupling the plurality of memory dies together in a single stack comprises electrically coupling at least eight memory dies together.
11. The method of claim 9 wherein the thermally conductive casing has a cavity that is shaped to receive the memory dies and the logic die, and wherein the thermally conductive casing comprises a metal.
12. The method of claim 9 wherein the thermally conductive casing thermally contacts the memory die spaced farthest from the logic die.
13. The method of claim 9 wherein the thermally conductive casing thermally contacts the memory dies to define a first thermal path and thermally contacts the thermal transfer feature to define a second thermal path spaced laterally apart from the memory dies.
14. The method of claim 9, further comprising forming a plurality of thermally conductive elements extending between the memory dies and between the logic die and the lowermost memory die, wherein the thermally conductive elements are electrically isolated from the memory and logic dies.
15. The method of claim 9 wherein the thermal transfer feature is a first thermal transfer feature, and wherein the method further comprises superimposing a second thermal transfer feature with the memory dies, wherein the first and second thermal transfer features are pre-formed blank silicon members.
16. The method of claim 15 wherein superimposing the second thermal transfer feature with the memory dies comprises positioning an upper surface of the second thermal transfer feature to be generally coplanar with an upper surface of the first thermal transfer feature, and wherein the method further comprises thermally contacting the thermally conductive casing with the upper surface of the second thermal transfer feature.
US14/825,009 2011-11-14 2015-08-12 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods Active US10170389B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/825,009 US10170389B2 (en) 2011-11-14 2015-08-12 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US16/229,257 US10741468B2 (en) 2011-11-14 2018-12-21 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US16/936,639 US11594462B2 (en) 2011-11-14 2020-07-23 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161559664P 2011-11-14 2011-11-14
US201161559659P 2011-11-14 2011-11-14
US13/613,540 US9153520B2 (en) 2011-11-14 2012-09-13 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US14/825,009 US10170389B2 (en) 2011-11-14 2015-08-12 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/613,540 Division US9153520B2 (en) 2011-11-14 2012-09-13 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/229,257 Continuation US10741468B2 (en) 2011-11-14 2018-12-21 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Publications (2)

Publication Number Publication Date
US20150348956A1 US20150348956A1 (en) 2015-12-03
US10170389B2 true US10170389B2 (en) 2019-01-01

Family

ID=48279803

Family Applications (5)

Application Number Title Priority Date Filing Date
US13/613,235 Active 2033-07-28 US9269646B2 (en) 2011-11-14 2012-09-13 Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
US13/613,540 Active US9153520B2 (en) 2011-11-14 2012-09-13 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US14/825,009 Active US10170389B2 (en) 2011-11-14 2015-08-12 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US16/229,257 Active US10741468B2 (en) 2011-11-14 2018-12-21 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US16/936,639 Active US11594462B2 (en) 2011-11-14 2020-07-23 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US13/613,235 Active 2033-07-28 US9269646B2 (en) 2011-11-14 2012-09-13 Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
US13/613,540 Active US9153520B2 (en) 2011-11-14 2012-09-13 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Family Applications After (2)

Application Number Title Priority Date Filing Date
US16/229,257 Active US10741468B2 (en) 2011-11-14 2018-12-21 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US16/936,639 Active US11594462B2 (en) 2011-11-14 2020-07-23 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Country Status (7)

Country Link
US (5) US9269646B2 (en)
EP (2) EP2780939B1 (en)
JP (3) JP6122863B2 (en)
KR (2) KR101673066B1 (en)
CN (2) CN103988296B (en)
TW (2) TWI515845B (en)
WO (2) WO2013074454A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11075167B2 (en) 2019-02-01 2021-07-27 Dialog Semiconductor (Uk) Limited Pillared cavity down MIS-SIP
US11721669B2 (en) 2019-09-24 2023-08-08 Samsung Electronics Co, Ltd. Semiconductor package including a first semiconductor stack and a second semiconductor stack of different widths

Families Citing this family (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269646B2 (en) 2011-11-14 2016-02-23 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
JP2013197387A (en) * 2012-03-21 2013-09-30 Elpida Memory Inc Semiconductor device
US8816494B2 (en) * 2012-07-12 2014-08-26 Micron Technology, Inc. Semiconductor device packages including thermally insulating materials and methods of making and using such semiconductor packages
KR20140023706A (en) 2012-08-17 2014-02-27 에스케이하이닉스 주식회사 Power tsv of semiconductor device
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9129944B2 (en) 2013-01-18 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8803306B1 (en) * 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US9601406B2 (en) 2013-03-01 2017-03-21 Intel Corporation Copper nanorod-based thermal interface material (TIM)
JP6207190B2 (en) * 2013-03-22 2017-10-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9583415B2 (en) * 2013-08-02 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal interface material on the sidewalls of stacked dies
US9082743B2 (en) 2013-08-02 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packages with heat dissipation structures
KR20150018099A (en) * 2013-08-09 2015-02-23 에스케이하이닉스 주식회사 Stacked semiconductor device
KR102165267B1 (en) * 2013-11-18 2020-10-13 삼성전자 주식회사 Integrated circuit device having through-silicon via structure and method of manufacturing the same
US9735082B2 (en) * 2013-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packaging with hot spot thermal management features
US9287240B2 (en) 2013-12-13 2016-03-15 Micron Technology, Inc. Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
JP6135533B2 (en) * 2014-02-06 2017-05-31 日立金属株式会社 Multi-module
US9281302B2 (en) 2014-02-20 2016-03-08 International Business Machines Corporation Implementing inverted master-slave 3D semiconductor stack
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US10020236B2 (en) 2014-03-14 2018-07-10 Taiwan Semiconductar Manufacturing Campany Dam for three-dimensional integrated circuit
US9269700B2 (en) * 2014-03-31 2016-02-23 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
US20150279431A1 (en) * 2014-04-01 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US20150286529A1 (en) * 2014-04-08 2015-10-08 Micron Technology, Inc. Memory device having controller with local memory
US10418330B2 (en) * 2014-04-15 2019-09-17 Micron Technology, Inc. Semiconductor devices and methods of making semiconductor devices
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
EP3140743B1 (en) 2014-05-08 2021-11-24 Micron Technology, INC. Hybrid memory cube system interconnect directory-based cache coherence methodology
US9520370B2 (en) * 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures
US9431360B2 (en) * 2014-05-27 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
US9653381B2 (en) 2014-06-17 2017-05-16 Micron Technology, Inc. Semiconductor structures and die assemblies including conductive vias and thermally conductive elements and methods of forming such structures
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
US9443744B2 (en) * 2014-07-14 2016-09-13 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
US9691746B2 (en) * 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US9337119B2 (en) * 2014-07-14 2016-05-10 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
US9735130B2 (en) * 2014-08-29 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9496154B2 (en) 2014-09-16 2016-11-15 Invensas Corporation Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
KR102307490B1 (en) * 2014-10-27 2021-10-05 삼성전자주식회사 Semiconductor package
US9543274B2 (en) 2015-01-26 2017-01-10 Micron Technology, Inc. Semiconductor device packages with improved thermal management and related methods
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
US9601374B2 (en) 2015-03-26 2017-03-21 Micron Technology, Inc. Semiconductor die assembly
KR102373543B1 (en) * 2015-04-08 2022-03-11 삼성전자주식회사 Method and device for controlling operation using temperature deviation in multi-chip package
US9780079B2 (en) 2015-04-30 2017-10-03 Micron Technology, Inc. Semiconductor die assembly and methods of forming thermal paths
US9768149B2 (en) * 2015-05-19 2017-09-19 Micron Technology, Inc. Semiconductor device assembly with heat transfer structure formed from semiconductor material
US10215500B2 (en) 2015-05-22 2019-02-26 Micron Technology, Inc. Semiconductor device assembly with vapor chamber
US9645619B2 (en) * 2015-05-29 2017-05-09 Corsair Memory, Inc. Micro heat pipe cooling system
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
KR102445662B1 (en) 2015-07-01 2022-09-22 삼성전자주식회사 Storage device
WO2017052605A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Redistribution layer diffusion barrier
US10163859B2 (en) 2015-10-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
US10068875B2 (en) * 2015-10-22 2018-09-04 Micron Technology, Inc. Apparatuses and methods for heat transfer from packaged semiconductor die
KR20170066843A (en) * 2015-12-07 2017-06-15 삼성전자주식회사 Stacked semiconductor device and method of manufacturing the same
CN109075186B (en) 2015-12-15 2023-09-05 谷歌有限责任公司 Superconducting bump joint
US9875993B2 (en) * 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
US10032695B2 (en) 2016-02-19 2018-07-24 Google Llc Powermap optimized thermally aware 3D chip package
KR102579876B1 (en) * 2016-02-22 2023-09-18 삼성전자주식회사 Semiconductor package
US9960150B2 (en) 2016-06-13 2018-05-01 Micron Technology, Inc. Semiconductor device assembly with through-mold cooling channel formed in encapsulant
US10236229B2 (en) 2016-06-24 2019-03-19 Xilinx, Inc. Stacked silicon package assembly having conformal lid
US9859262B1 (en) 2016-07-08 2018-01-02 Globalfoundries Inc. Thermally enhanced package to reduce thermal interaction between dies
US9978696B2 (en) * 2016-09-14 2018-05-22 Analog Devices, Inc. Single lead-frame stacked die galvanic isolator
US10068879B2 (en) 2016-09-19 2018-09-04 General Electric Company Three-dimensional stacked integrated circuit devices and methods of assembling the same
US10008395B2 (en) * 2016-10-19 2018-06-26 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill
US9761543B1 (en) * 2016-12-20 2017-09-12 Texas Instruments Incorporated Integrated circuits with thermal isolation and temperature regulation
US10062634B2 (en) * 2016-12-21 2018-08-28 Micron Technology, Inc. Semiconductor die assembly having heat spreader that extends through underlying interposer and related technology
US20180197761A1 (en) * 2017-01-10 2018-07-12 Axcelis Technologies, Inc. Active workpiece heating or cooling for an ion implantation system
US9865570B1 (en) * 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
US10199356B2 (en) * 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures
CN107247685B (en) * 2017-05-26 2021-01-12 京信通信技术(广州)有限公司 Method and device for extracting characteristic parameters of MEMS device port
US10096576B1 (en) 2017-06-13 2018-10-09 Micron Technology, Inc. Semiconductor device assemblies with annular interposers
US10090282B1 (en) * 2017-06-13 2018-10-02 Micron Technology, Inc. Semiconductor device assemblies with lids including circuit elements
US10410940B2 (en) * 2017-06-30 2019-09-10 Intel Corporation Semiconductor package with cavity
US10340242B2 (en) * 2017-08-28 2019-07-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
JP2019054181A (en) * 2017-09-19 2019-04-04 東芝メモリ株式会社 Semiconductor package
CN108257927B (en) * 2018-01-17 2020-02-07 深圳市晶存科技有限公司 Semiconductor memory device
US10453820B2 (en) * 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US10573630B2 (en) * 2018-04-20 2020-02-25 Advanced Micro Devices, Inc. Offset-aligned three-dimensional integrated circuit
US10685937B2 (en) * 2018-06-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package having dummy structures and method of forming same
US10790251B2 (en) 2018-06-20 2020-09-29 Micron Technology, Inc. Methods for enhancing adhesion of three-dimensional structures to substrates
US11107747B2 (en) 2018-09-19 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with composite thermal interface material structure and method of forming the same
US11594463B2 (en) * 2018-10-11 2023-02-28 Intel Corporation Substrate thermal layer for heat spreader connection
US11152333B2 (en) * 2018-10-19 2021-10-19 Micron Technology, Inc. Semiconductor device packages with enhanced heat management and related systems
US11672111B2 (en) 2018-12-26 2023-06-06 Ap Memory Technology Corporation Semiconductor structure and method for manufacturing a plurality thereof
US11417628B2 (en) 2018-12-26 2022-08-16 Ap Memory Technology Corporation Method for manufacturing semiconductor structure
US11139270B2 (en) 2019-03-18 2021-10-05 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
WO2020240239A1 (en) * 2019-05-31 2020-12-03 Micron Technology, Inc. Memory component for a system-on-chip device
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
US11043472B1 (en) 2019-05-31 2021-06-22 Kepler Compute Inc. 3D integrated ultra high-bandwidth memory
US10872835B1 (en) * 2019-07-03 2020-12-22 Micron Technology, Inc. Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
US11211378B2 (en) 2019-07-18 2021-12-28 International Business Machines Corporation Heterogeneous integration structure for artificial intelligence computing
US11056443B2 (en) 2019-08-29 2021-07-06 Micron Technology, Inc. Apparatuses exhibiting enhanced stress resistance and planarity, and related methods
JP2021052094A (en) * 2019-09-25 2021-04-01 株式会社ミツバ driver
US11064615B2 (en) * 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package
CN111106079B (en) * 2019-11-21 2021-08-27 青岛歌尔智能传感器有限公司 Heat dissipation chip, manufacturing method thereof and electronic equipment
KR20210065353A (en) 2019-11-27 2021-06-04 삼성전자주식회사 Semiconductor package
CN113035801A (en) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 Memory device and method of manufacturing the same
TWI780666B (en) * 2020-05-07 2022-10-11 愛普科技股份有限公司 Semiconductor structure and method for manufacturing a plurality thereof
KR20220015757A (en) * 2020-07-31 2022-02-08 삼성전자주식회사 semiconductor package and method of manufacturing the same
KR20220019148A (en) 2020-08-06 2022-02-16 삼성전자주식회사 Semiconductor package
CN111933589B (en) * 2020-09-03 2021-02-09 立讯电子科技(昆山)有限公司 Packaging structure and preparation process thereof
CN112164674A (en) * 2020-09-24 2021-01-01 芯盟科技有限公司 Stacked high bandwidth memory
FR3115395A1 (en) 2020-10-16 2022-04-22 Upmem SEMICONDUCTOR DEVICE COMPRISING A STACK OF CHIPS AND CHIPS OF SUCH A STACK
US11637072B2 (en) 2020-11-06 2023-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11574891B2 (en) * 2021-01-26 2023-02-07 Nanya Technology Corporation Semiconductor device with heat dissipation unit and method for fabricating the same
US20220367311A1 (en) * 2021-05-13 2022-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package structure and method for forming the same
KR20220164946A (en) * 2021-06-07 2022-12-14 삼성전자주식회사 Semiconductor package
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
US20230163048A1 (en) * 2021-11-19 2023-05-25 Google Llc Temperature Control Element Utilized in Device Die Packages
US11887908B2 (en) * 2021-12-21 2024-01-30 International Business Machines Corporation Electronic package structure with offset stacked chips and top and bottom side cooling lid
WO2024014360A1 (en) * 2022-07-14 2024-01-18 株式会社村田製作所 Semiconductor apparatus
WO2024014361A1 (en) * 2022-07-14 2024-01-18 株式会社村田製作所 Semiconductor module

Citations (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536907A (en) 1993-12-01 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US5789810A (en) 1995-12-21 1998-08-04 International Business Machines Corporation Semiconductor cap
US6111313A (en) 1998-01-12 2000-08-29 Lsi Logic Corporation Integrated circuit package having a stiffener dimensioned to receive heat transferred laterally from the integrated circuit
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
US6320257B1 (en) 1994-09-27 2001-11-20 Foster-Miller, Inc. Chip packaging technique
US6458609B1 (en) 1997-01-24 2002-10-01 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof
US20030057540A1 (en) 2001-09-26 2003-03-27 Wen-Lo Shieh Combination-type 3D stacked IC package
US6637506B2 (en) 2002-03-08 2003-10-28 Sun Microsystems, Inc. Multi-material heat spreader
US6649443B2 (en) 2001-09-26 2003-11-18 Sun Microsystems, Inc. System for facilitating alignment of silicon die
US20040042178A1 (en) 2002-09-03 2004-03-04 Vadim Gektin Heat spreader with surface cavity
US20040074630A1 (en) 2002-10-18 2004-04-22 Sen Bidyut K. Conformal heat spreader
US20040238944A1 (en) * 2003-05-30 2004-12-02 Jack Bish Integrated heat spreader lid
US20040262372A1 (en) 2003-06-26 2004-12-30 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same
US6853068B1 (en) 2002-05-22 2005-02-08 Volterra Semiconductor Corporation Heatsinking and packaging of integrated circuit chips
US20050170600A1 (en) 2004-01-29 2005-08-04 Yukio Fukuzo Three-dimensional semiconductor package, and spacer chip used therein
JP2006210892A (en) 2004-12-27 2006-08-10 Nec Corp Semiconductor device
US7119433B2 (en) 2004-06-16 2006-10-10 International Business Machines Corporation Packaging for enhanced thermal and structural performance of electronic chip modules
US20060261467A1 (en) 2005-05-19 2006-11-23 International Business Machines Corporation Chip package having chip extension and method
US20070023887A1 (en) 2005-07-29 2007-02-01 Nec Electronics Corporation Multi-chip semiconductor package featuring wiring chip incorporated therein, and method for manufacturing such multi-chip semiconductor package
US7186590B2 (en) 2002-07-16 2007-03-06 International Business Machines Corporation Thermally enhanced lid for multichip modules
US20070145571A1 (en) 2005-12-15 2007-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency
US7239020B2 (en) 2004-05-06 2007-07-03 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Multi-mode integrated circuit structure
US7268020B2 (en) 2004-12-30 2007-09-11 Intel Corporation Embedded heat spreader
US7273090B2 (en) 2005-06-29 2007-09-25 Intel Corporation Systems for integrated cold plate and heat spreader
US20080001277A1 (en) 2006-06-30 2008-01-03 Tsrong Yi Wen Semiconductor package system and method of improving heat dissipation of a semiconductor package
US20080042261A1 (en) 2006-08-15 2008-02-21 Andreas Wolter Integrated circuit package with a heat dissipation device and a method of making the same
US7352068B2 (en) 2004-12-01 2008-04-01 Renesas Technology Corp. Multi-chip module
US20080099909A1 (en) 2006-10-30 2008-05-01 Samsung Electronics Co., Ltd. Wafer stacked package having vertical heat emission path and method of fabricating the same
US20080122067A1 (en) 2006-11-27 2008-05-29 Chung-Cheng Wang Heat spreader for an electrical device
WO2008108335A1 (en) 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device
US20090057880A1 (en) 2007-09-03 2009-03-05 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor package, stacked module, card, system and method of manufacturing the semiconductor device
US7506527B2 (en) 2000-04-10 2009-03-24 Honeywell International, Inc. Making integral heat spreader by coining
US7541217B1 (en) 2008-02-05 2009-06-02 Industrial Technology Research Institute Stacked chip structure and fabrication method thereof
US7547582B2 (en) 2006-09-26 2009-06-16 International Business Machines Corporation Method of fabricating a surface adapting cap with integral adapting material for single and multi chip assemblies
US20090161402A1 (en) 2007-12-20 2009-06-25 Hakjune Oh Data storage and stackable configurations
US20090224400A1 (en) * 2008-03-05 2009-09-10 Xilinx, Inc. Semiconductor assembly having reduced thermal spreading resistance and methods of making same
US20090267194A1 (en) 2008-04-24 2009-10-29 Powertech Technology Inc. Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips
JP2009277334A (en) 2008-04-14 2009-11-26 Hitachi Ltd Information processing device and semiconductor storage device
US20100019377A1 (en) * 2008-07-22 2010-01-28 International Business Machines Corporation Segmentation of a die stack for 3d packaging thermal management
US20100044856A1 (en) * 2008-08-19 2010-02-25 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20100078807A1 (en) 2008-09-19 2010-04-01 Infineon Technologies Ag Power semiconductor module assembly with heat dissipating element
US20100078790A1 (en) 2008-09-29 2010-04-01 Hitachi, Ltd. Semiconductor device
US20100095168A1 (en) 2008-10-15 2010-04-15 Micron Technology, Inc. Embedded processor
JP2010103195A (en) 2008-10-21 2010-05-06 Nikon Corp Multilayer type semiconductor device and method of manufacturing the same
US20100187670A1 (en) 2009-01-26 2010-07-29 Chuan-Yi Lin On-Chip Heat Spreader
US20100230805A1 (en) 2009-03-16 2010-09-16 Ati Technologies Ulc Multi-die semiconductor package with heat spreader
JP2010251427A (en) 2009-04-13 2010-11-04 Hitachi Ltd Semiconductor module
US20100315787A1 (en) 2004-07-08 2010-12-16 Ming Li System and Method for Dissipating Heat from Semiconductor Devices
US20100320588A1 (en) 2009-06-22 2010-12-23 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die
KR20110037066A (en) 2009-10-05 2011-04-13 앰코 테크놀로지 코리아 주식회사 Semiconductor device and fabricating method thereof
US7939364B2 (en) 2008-05-15 2011-05-10 Oracle America, Inc. Optimized lid attach process for thermal management and multi-surface compliant heat removal
US20120038057A1 (en) * 2010-08-13 2012-02-16 International Business Machines Corporation Thermal enhancement for multi-layer semiconductor stacks
US20130119527A1 (en) 2011-11-14 2013-05-16 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462410B1 (en) 2000-08-17 2002-10-08 Sun Microsystems Inc Integrated circuit component temperature gradient reducer
JP3732194B2 (en) * 2003-09-03 2006-01-05 沖電気工業株式会社 Semiconductor device
US7602618B2 (en) 2004-08-25 2009-10-13 Micron Technology, Inc. Methods and apparatuses for transferring heat from stacked microfeature devices
US7514775B2 (en) * 2006-10-09 2009-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
EP2219232A1 (en) * 2007-11-15 2010-08-18 Panasonic Corporation Semiconductor light emitting device
JP2009246258A (en) 2008-03-31 2009-10-22 Nikon Corp Semiconductor device, and manufacturing method thereof
US8299608B2 (en) * 2010-07-08 2012-10-30 International Business Machines Corporation Enhanced thermal management of 3-D stacked die packaging

Patent Citations (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536907A (en) 1993-12-01 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US6320257B1 (en) 1994-09-27 2001-11-20 Foster-Miller, Inc. Chip packaging technique
US5789810A (en) 1995-12-21 1998-08-04 International Business Machines Corporation Semiconductor cap
US6458609B1 (en) 1997-01-24 2002-10-01 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof
US6111313A (en) 1998-01-12 2000-08-29 Lsi Logic Corporation Integrated circuit package having a stiffener dimensioned to receive heat transferred laterally from the integrated circuit
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
US7506527B2 (en) 2000-04-10 2009-03-24 Honeywell International, Inc. Making integral heat spreader by coining
US20030057540A1 (en) 2001-09-26 2003-03-27 Wen-Lo Shieh Combination-type 3D stacked IC package
US6649443B2 (en) 2001-09-26 2003-11-18 Sun Microsystems, Inc. System for facilitating alignment of silicon die
US6637506B2 (en) 2002-03-08 2003-10-28 Sun Microsystems, Inc. Multi-material heat spreader
US6853068B1 (en) 2002-05-22 2005-02-08 Volterra Semiconductor Corporation Heatsinking and packaging of integrated circuit chips
US7186590B2 (en) 2002-07-16 2007-03-06 International Business Machines Corporation Thermally enhanced lid for multichip modules
US20040042178A1 (en) 2002-09-03 2004-03-04 Vadim Gektin Heat spreader with surface cavity
US20040074630A1 (en) 2002-10-18 2004-04-22 Sen Bidyut K. Conformal heat spreader
US20040238944A1 (en) * 2003-05-30 2004-12-02 Jack Bish Integrated heat spreader lid
US7518219B2 (en) 2003-05-30 2009-04-14 Honeywell International Inc. Integrated heat spreader lid
US6906413B2 (en) 2003-05-30 2005-06-14 Honeywell International Inc. Integrated heat spreader lid
US20040262372A1 (en) 2003-06-26 2004-12-30 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same
US20050170600A1 (en) 2004-01-29 2005-08-04 Yukio Fukuzo Three-dimensional semiconductor package, and spacer chip used therein
JP2005217205A (en) 2004-01-29 2005-08-11 Nec Electronics Corp Three-dimensional semiconductor device of chip multilayer structure and spacer chip used therein
US7239020B2 (en) 2004-05-06 2007-07-03 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Multi-mode integrated circuit structure
US7119433B2 (en) 2004-06-16 2006-10-10 International Business Machines Corporation Packaging for enhanced thermal and structural performance of electronic chip modules
US20100315787A1 (en) 2004-07-08 2010-12-16 Ming Li System and Method for Dissipating Heat from Semiconductor Devices
US7352068B2 (en) 2004-12-01 2008-04-01 Renesas Technology Corp. Multi-chip module
JP2006210892A (en) 2004-12-27 2006-08-10 Nec Corp Semiconductor device
US7268020B2 (en) 2004-12-30 2007-09-11 Intel Corporation Embedded heat spreader
US20060261467A1 (en) 2005-05-19 2006-11-23 International Business Machines Corporation Chip package having chip extension and method
US7273090B2 (en) 2005-06-29 2007-09-25 Intel Corporation Systems for integrated cold plate and heat spreader
US20070023887A1 (en) 2005-07-29 2007-02-01 Nec Electronics Corporation Multi-chip semiconductor package featuring wiring chip incorporated therein, and method for manufacturing such multi-chip semiconductor package
TWI331383B (en) 2005-12-15 2010-10-01 Taiwan Semiconductor Mfg Semiconductor package structure, stiffener and method of making same
US20070145571A1 (en) 2005-12-15 2007-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency
US20080001277A1 (en) 2006-06-30 2008-01-03 Tsrong Yi Wen Semiconductor package system and method of improving heat dissipation of a semiconductor package
US20080042261A1 (en) 2006-08-15 2008-02-21 Andreas Wolter Integrated circuit package with a heat dissipation device and a method of making the same
JP2008091879A (en) 2006-08-15 2008-04-17 Qimonda Ag Integrated circuit package with heat radiation device, and its manufacturing method
US7547582B2 (en) 2006-09-26 2009-06-16 International Business Machines Corporation Method of fabricating a surface adapting cap with integral adapting material for single and multi chip assemblies
KR100874910B1 (en) 2006-10-30 2008-12-19 삼성전자주식회사 Stacked semiconductor package having vertical heat dissipation path and manufacturing method thereof
US20080099909A1 (en) 2006-10-30 2008-05-01 Samsung Electronics Co., Ltd. Wafer stacked package having vertical heat emission path and method of fabricating the same
US20080122067A1 (en) 2006-11-27 2008-05-29 Chung-Cheng Wang Heat spreader for an electrical device
WO2008108335A1 (en) 2007-03-06 2008-09-12 Nikon Corporation Semiconductor device
US20120205792A1 (en) 2007-03-06 2012-08-16 Nikon Corporation Semiconductor device
TW200839978A (en) 2007-03-06 2008-10-01 Nikon Corp Semiconductor device
US20090057880A1 (en) 2007-09-03 2009-03-05 Samsung Electronics Co., Ltd. Semiconductor device, semiconductor package, stacked module, card, system and method of manufacturing the semiconductor device
US20090161402A1 (en) 2007-12-20 2009-06-25 Hakjune Oh Data storage and stackable configurations
US7541217B1 (en) 2008-02-05 2009-06-02 Industrial Technology Research Institute Stacked chip structure and fabrication method thereof
US20090224400A1 (en) * 2008-03-05 2009-09-10 Xilinx, Inc. Semiconductor assembly having reduced thermal spreading resistance and methods of making same
JP2009277334A (en) 2008-04-14 2009-11-26 Hitachi Ltd Information processing device and semiconductor storage device
US20090267194A1 (en) 2008-04-24 2009-10-29 Powertech Technology Inc. Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips
US7939364B2 (en) 2008-05-15 2011-05-10 Oracle America, Inc. Optimized lid attach process for thermal management and multi-surface compliant heat removal
US20100019377A1 (en) * 2008-07-22 2010-01-28 International Business Machines Corporation Segmentation of a die stack for 3d packaging thermal management
US7928562B2 (en) 2008-07-22 2011-04-19 International Business Machines Corporation Segmentation of a die stack for 3D packaging thermal management
US7781883B2 (en) 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20100044856A1 (en) * 2008-08-19 2010-02-25 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US20100078807A1 (en) 2008-09-19 2010-04-01 Infineon Technologies Ag Power semiconductor module assembly with heat dissipating element
US20100078790A1 (en) 2008-09-29 2010-04-01 Hitachi, Ltd. Semiconductor device
US20100095168A1 (en) 2008-10-15 2010-04-15 Micron Technology, Inc. Embedded processor
JP2010103195A (en) 2008-10-21 2010-05-06 Nikon Corp Multilayer type semiconductor device and method of manufacturing the same
US20100187670A1 (en) 2009-01-26 2010-07-29 Chuan-Yi Lin On-Chip Heat Spreader
US20100230805A1 (en) 2009-03-16 2010-09-16 Ati Technologies Ulc Multi-die semiconductor package with heat spreader
US7964951B2 (en) 2009-03-16 2011-06-21 Ati Technologies Ulc Multi-die semiconductor package with heat spreader
JP2010251427A (en) 2009-04-13 2010-11-04 Hitachi Ltd Semiconductor module
US20100320588A1 (en) 2009-06-22 2010-12-23 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die
KR20110037066A (en) 2009-10-05 2011-04-13 앰코 테크놀로지 코리아 주식회사 Semiconductor device and fabricating method thereof
US20120038057A1 (en) * 2010-08-13 2012-02-16 International Business Machines Corporation Thermal enhancement for multi-layer semiconductor stacks
US20130119527A1 (en) 2011-11-14 2013-05-16 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management, semiconductor devices including same and related methods

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
Europan Search Report dated Jun. 8, 2015 in Application No. 12849421.8, 6 pages.
International Search Report and Written Opinion dated Mar. 12, 2013 in International Application No. PCT/US2012/064672, 7 pages.
Office Action dated Apr. 20, 2016 in Korea Application No. 10-2014-7015990, 7 pages.
Office Action dated Dec. 22, 2015 in Japan Application No. 2014-541369, 10 pages.
Office Action dated Jul. 26, 2016 in Japan Application No. 2014-541369, 9 pages.
Office Action dated May 5, 2016 in China Application No. 201280061833.8, 30 pages.
Office Action dated Oct. 7, 2015 in Korea Application No. 2014-7015990, 12 pages.
Sikka, K. et al., An Efficient Lid Design for Cooling Stacked Flip-chip 3D Packages, Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2012 13th IEEE Intersociety Conference on, pp. 606-611, May 30, 2012-Jun. 1, 2012. DOI: 10.1109/IT.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11075167B2 (en) 2019-02-01 2021-07-27 Dialog Semiconductor (Uk) Limited Pillared cavity down MIS-SIP
US11532489B2 (en) 2019-02-01 2022-12-20 Dialog Semiconductor (Uk) Limited Pillared cavity down MIS-SiP
US11721669B2 (en) 2019-09-24 2023-08-08 Samsung Electronics Co, Ltd. Semiconductor package including a first semiconductor stack and a second semiconductor stack of different widths

Also Published As

Publication number Publication date
TWI515845B (en) 2016-01-01
EP2780940A4 (en) 2015-06-17
EP2780940A2 (en) 2014-09-24
TW201330218A (en) 2013-07-16
US20190122950A1 (en) 2019-04-25
WO2013074454A3 (en) 2013-07-11
EP2780939A2 (en) 2014-09-24
TWI518872B (en) 2016-01-21
KR20140088183A (en) 2014-07-09
EP2780939B1 (en) 2022-01-19
JP2016139814A (en) 2016-08-04
WO2013074454A2 (en) 2013-05-23
KR101661041B1 (en) 2016-10-10
EP2780939A4 (en) 2015-07-08
CN103988296B (en) 2017-03-22
WO2013074484A2 (en) 2013-05-23
US20200350224A1 (en) 2020-11-05
JP6122863B2 (en) 2017-04-26
TW201327740A (en) 2013-07-01
JP2014533440A (en) 2014-12-11
US20130119527A1 (en) 2013-05-16
US9153520B2 (en) 2015-10-06
WO2013074484A3 (en) 2013-08-15
JP2014533439A (en) 2014-12-11
CN103975428A (en) 2014-08-06
EP2780940B1 (en) 2019-04-17
KR20140098783A (en) 2014-08-08
US10741468B2 (en) 2020-08-11
CN103988296A (en) 2014-08-13
US9269646B2 (en) 2016-02-23
JP6438902B2 (en) 2018-12-19
JP5897729B2 (en) 2016-03-30
CN103975428B (en) 2016-12-21
US20150348956A1 (en) 2015-12-03
US11594462B2 (en) 2023-02-28
US20130119528A1 (en) 2013-05-16
KR101673066B1 (en) 2016-11-04

Similar Documents

Publication Publication Date Title
US11594462B2 (en) Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
US10978427B2 (en) Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US11239095B2 (en) Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill
US10461059B2 (en) Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
US9818625B2 (en) Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
US10153178B2 (en) Semiconductor die assemblies with heat sink and associated systems and methods
US10199356B2 (en) Semiconductor device assembles with electrically functional heat transfer structures
EP3266042A1 (en) Semiconductor device assembly with underfill containment cavity

Legal Events

Date Code Title Description
AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731

AS Assignment

Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4