CN116072625A - 包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法 - Google Patents

包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法 Download PDF

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CN116072625A
CN116072625A CN202211310623.XA CN202211310623A CN116072625A CN 116072625 A CN116072625 A CN 116072625A CN 202211310623 A CN202211310623 A CN 202211310623A CN 116072625 A CN116072625 A CN 116072625A
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semiconductor device
silicon structure
monolithic silicon
device assembly
assembly
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K·R·帕雷克
A·帕雷克
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请案涉及包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法。提供一种半导体装置组合件。所述组合件包含第一半导体装置，其在其上表面上包含多个电触点；单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面；以及第二半导体装置，其安置在所述腔中，所述第二半导体装置包含多个互连件，所述多个互连件各自可操作地耦合到所述多个电触点中的对应者。

Description

包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法
相关申请案的交叉参考
本申请案含有与标题为“包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法(SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICONSTRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME)”的同时申请的美国专利申请案相关的标的物。其公开内容以引用的方式并入本文中的相关申请案转让给美光科技公司(Micron Technology,Inc.)，并且由代理人案号010829-9679.US00及010829-9680.US00识别。
技术领域
本公开大体上涉及半导体装置组合件，且更特定来说，涉及包含用于热耗散的单片硅结构的半导体装置组合件及其制造方法。
背景技术
微电子装置通常具有裸片(即，芯片)，其包含具有高密度的极小组件的集成电路。通常，裸片包含电耦合到集成电路的极小接合垫的阵列。接合垫是供应电压、信号等等通过其传输到集成电路及从集成电路传输的外部电触点。在形成裸片之后，其经“封装”以将接合垫耦合到可更容易耦合到各种电力供应线、信号线及接地线的较大电端子阵列。用于封装裸片的常规工艺包含将裸片上的接合垫电耦合到引线、球垫或其它类型的电端子的阵列且囊封裸片以保护其免受环境因素(例如水分、微粒、静电及物理冲击)影响。
发明内容
本公开的一方面提供一种半导体装置组合件，其包括：第一半导体装置，其在其上表面上包含多个电触点；单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面；以及第二半导体装置，其安置在所述腔中，所述第二半导体装置包含多个互连件，所述多个互连件各自可操作地耦合到所述多个电触点中的对应者。
本公开的另一方面提供一种半导体装置组合件，其包括：第一半导体装置，其包含上表面；单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面；以及第二半导体装置，其直接耦合到所述第一半导体装置并且安置在所述腔中，使得所述第二半导体装置的背表面与所述单片硅结构的所述顶部表面大体上共面。
本公开的另一方面提供一种半导体装置组合件，其包括：第一半导体装置，其包含上表面；第二半导体装置，其直接由所述第一半导体装置的上表面承载；以及单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面，其中所述单片硅结构完全环绕所述第二半导体装置的多个侧壁。
附图说明
图1是根据本公开的一个实施例的用于热耗散的单片硅结构的简化示意性横截面视图。
图2到10是根据本公开的实施例的在制造过程中的各个阶段处的半导体装置组合件的简化示意性横截面视图。
图11到14是根据本公开的实施例的在制造过程中的各个阶段处的用于热耗散的单片硅结构的简化示意性横截面视图。
图15到20是根据本公开的实施例的在制造过程中各个阶段处的半导体装置组合件的简化示意性横截面视图。
图21到25是根据本公开的实施例的在制造过程中的各个阶段处用于热耗散的单片硅结构的简化示意性横截面视图。
图26是根据本公开的一个实施例的半导体装置组合件的简化示意性横截面视图。
图27是展示包含根据本公开的实施例配置的半导体装置组合件的系统的示意图。
具体实施方式
下面描述半导体装置以及相关联系统及方法的若干实施例的特定细节。相关领域的一般技术人员将认识到，可在晶片级或裸片级下执行本文中所描述的方法的合适阶段。因此，取决于其使用上下文，术语“衬底”可指晶片级衬底或经单切裸片级衬底。此外，除非上下文另有指示，否则可使用常规半导体制造技术来形成本文中所公开的结构。可(例如)使用化学气相沉积、物理气相沉积、原子层沉积、镀覆、化学镀、旋转涂布及/或其它合适技术来沉积材料。类似地，可(例如)使用等离子体蚀刻、湿式蚀刻、化学机械平坦化或其它合适技术来去除材料。
一些半导体装置组合件包含经配置以辅助从组合件中的一或多个半导体装置提取热量的结构。这些结构通常由具有高导热性的金属形成，所述金属例如铜、银、铝或其合金。因为这些金属的热膨胀系数(CTE)可能与组合件中半导体装置的CTE相差很大，所以由热循环引起的分层、开裂或其它类型的机械损伤可能对这些组合件构成挑战。此外，用于从这些金属形成结构并使其成形以适应组合件中的额外装置的制造技术，需要与用于大多数其它组装工艺的工具不同的工具，并且可大大增加在其中集成所述结构的组合件的费用。
为解决这些缺点及其它问题，本申请案的各种实施例提供半导体装置组合件，在半导体装置组合件中提供单片硅结构用于多裸片结构中的下裸片的表面与组合件的外(例如，上)表面之间的热耗散。单片硅结构可包含部分或完全延伸穿过其的腔，其中可提供额外半导体装置(例如，裸片、裸片堆叠、封装、组合件等)。额外半导体装置可电耦合到单片硅结构附接到的下裸片的相同表面(例如，通过氧化物-氧化物接合、混合接合、粘合剂、互连件或类似者)。单片硅结构凭借其高导热性以及其热膨胀系数与下裸片的热膨胀系数的紧密匹配，提供经改进热管理而没有与其它热管理结构相关联的损坏风险。
图1是根据本公开的实施例的单片硅结构100的简化示意性部分横截面视图。单片硅结构100包含一或多个腔(说明两个)，其至少部分延伸穿过单片硅结构100的厚度(例如，进入主体)。结构100可例如由空白硅晶片形成，其中已经形成腔(例如，通过遮蔽及定向蚀刻、激光烧蚀等)。结构100可保持在晶片级用于后续晶片级处理步骤，或可任选地在后续处理步骤之前被单切。
根据本公开的一个方面，单片硅结构100在集成到较大半导体装置组合件之前，可在其腔中预先填充有半导体装置。图2是根据本公开的一个实施例在其中安置若干半导体装置的单片硅结构100的简化示意性横截面视图。如参考图2可见，半导体装置102(例如，个别裸片、经互连裸片的竖直堆叠、装置封装、装置组合件等)经安置到单片硅结构100的腔中。每一半导体装置102可通过半导体装置的背表面与腔的面向内表面之间的粘合剂(例如，热界面材料)固定在对应腔中。腔可经定大小使得小间隙103(例如，任选地填充有粘合剂、底填料、囊封剂或类似者)保持围绕半导体装置102以使将其安置在腔中的过程容易。在其它实施例中，可通过仔细匹配半导体装置102与腔的外部尺寸来最小化或甚至消除间隙103。为促进将半导体装置102及单片硅结构100集成到较大组合件中，可形成重布层104，其包含与单片硅结构100对准的一或多个热垫105(例如，包括铜、银、铝或与金属-金属接合操作兼容的其它金属)及可操作地耦合到半导体装置102的一或多个互连件106(例如，垫、支柱、UBM、引脚、焊球等)。在其它实施例中，可省略重布层，并且半导体装置102可在填充到单片硅结构100之前提供有互连件(例如，与单片硅结构100的接合表面共面)。
转到图3，说明根据本公开的一个实施例的在准备接合到另一半导体装置(例如，组合件中的前述下半导体装置)时对准的经填充单片硅结构100。下半导体装置110包含电介质层109，其中安置有电触点107及热触点108。经填充单片硅结构100可接合到下半导体装置110，使得热垫105耦合到热触点107且互连件106耦合到电触点108以形成半导体装置组合件400，如在图4中根据本公开的一个实施例所说明。接合操作可为混合接合操作，其中在重布层104的电介质与在下半导体装置110上方形成的电介质层109之间形成电介质-电介质接合(例如，氧化物-氧化物接合)，并且在热垫105及热触点107中的对应者之间以及在互连件106及电触点108中的对应者之间形成金属-金属接合。
尽管在前述实例实施例中，半导体装置组合件400已被说明为通过混合接合操作形成，但在其它实施例中可用粘合剂层(例如，热界面材料(TIM))、具有或不具有底填料的焊接互连件或所属领域的技术人员众所周知的任何其它接合方法实现经填充单片硅结构与下半导体装置之间的接合。
根据本公开的额外方面，半导体装置组合件400可任选性地进行进一步处理，以去除单片硅结构100的上覆于半导体装置102已安置在其中的腔的部分，以便降低组合件的高度及/或提供额外连接性选项。在此方面，图5是半导体装置组合件500的简化示意性横截面视图，其中类似于图4所说明的组合件的组合件已进行背侧减薄操作(例如，通过化学机械抛光(CMP)、研磨等)以从单片硅结构100去除材料的部分以便于暴露半导体装置102的背表面并降低组合件500的整体高度。
在其中半导体装置102包含用于进一步连接性的背侧触点的实施例中，从覆盖半导体装置102的背表面的单片硅结构100去除材料的部分可允许将额外装置集成到半导体装置组合件中。图6中展示一个此布置，在图6中说明半导体装置组合件600的简化示意性横截面视图。如参考图6可见，类似于图5中所说明的组合件的组合件具有连接到半导体装置102的暴露背侧触点(例如，通过传统倒装芯片互连、焊球阵列、混合接合等)的额外半导体装置111(例如，个别裸片、经互连裸片的竖直堆叠、装置封装、装置组合件等)。然后，额外半导体装置111可由一层模制材料112囊封以对其提供机械保护。
替代地，在另一实施例中，一或多个额外经预先填充单片硅结构(例如，类似于图2中所说明的经预先填充单片硅结构)可接合到图5中所说明的半导体组合件500以提供具有高装置密度的组合件同时保持良好热性能，而非个别地将额外半导体装置连接到半导体装置102的暴露背侧触点，如在图6中所说明。图7中展示一个此组合件，在图7中说明半导体装置组合件700的简化示意性横截面视图，其中类似于图5中所说明的组合件的组合件具有额外单片硅结构113，额外单片硅结构113填充有接合到其的半导体装置。
如所属领域的技术人员将容易了解，图5及7中所说明的过程可迭代地重复，使得根据本公开的一个方面，额外经填充单片硅结构本身可进行另一背侧减薄操作以暴露其中的半导体装置的背侧触点用于接合到另一经填充单片硅结构。
替代地或额外地，在另一实施例中，覆盖填充在其腔中的半导体装置的背表面的单片硅结构的材料仅可被充分减薄以允许穿过经减薄材料形成通路(例如，穿硅通路(TSV))以连接到半导体装置的背侧触点，而非进行完全去除覆盖填充在其腔中的半导体装置的背表面的单片硅结构的材料的背侧减薄操作。参考图8可更容易理解这一点，图8中展示类似于图4的组合件的组合件，其已进行去除覆盖腔中的半导体装置的背表面的材料的一部分的背侧减薄操作，并且已进一步进行TSV形成操作(例如，穿过硅材料形成开口，钝化开口，从开口的底部去除钝化以暴露背侧触点，将导体镀覆到开口中等)，从而提供延伸穿过经减薄材料以接触半导体装置的背侧触点以促进进一步连接性的TSV 114。
转到图9，说明半导体装置组合件900的简化示意性横截面视图，其中类似于图8中展示的组合件的组合件使额外半导体装置111(例如，个别裸片、经互连裸片的竖直堆叠、装置封装、装置组合件等)连接到延伸穿过单片硅结构100到半导体装置102(例如，通过传统倒装芯片互连、焊球阵列、混合接合等)的TSV 114。然后，额外半导体装置111可由一层模制材料112囊封以对其提供机械保护，如上文参考图6更详细地描述。
替代地，在另一实施例中，一或多个额外经预先填充单片硅结构(例如，类似于图2中所说明的经预先填充单片硅结构)可接合到图8中所说明的半导体组合件以提供具有高装置密度的组合件同时保持良好热性能，而非个别地将额外半导体装置连接到TSV 114，如在图9中所说明。图10中展示一个此组合件，在图10中说明半导体装置组合件100的简化示意性横截面视图，其中类似于图8中所说明的组合件的组合件具有额外单片硅结构113，额外单片硅结构113填充有接合到其的半导体装置。
如上文阐述，可经由用于在硅中形成开口或腔的传统蚀刻技术从空白硅晶片制造单片硅结构。替代地或额外地，根据本公开的各种实施例，用于制造单片硅结构的方法可包含高度可控且高速的蚀刻工艺，如下面更详细阐述。
转到图11，根据本公开的一个实施例，在形成过程的一步骤处，以简化部分横截面视图展示将从其形成单片硅结构的前体结构。前体结构包含硅晶片1100，在其上已形成钝化层1101(例如，电介质材料)，在钝化层1101中形成一或多个热垫1102。在钝化层1101上方形成掩模层1103，其图案对应于将在硅晶片1100中形成的腔。更特定来说，掩模层1103包含上覆于硅晶片1100中将形成腔的区的小开口的图案(例如，对应于窄柱状或鳍状结构)。如参考图12可见，可将小开口1104至少部分蚀刻到硅晶片1100的厚度中以从将形成腔的地方移除材料中的一些。从腔蚀刻少量材料而不是蚀刻整个腔的优点是，与掩模开口对应于最终腔开口的全尺寸相比，定向蚀刻操作可更快地完成。在从硅晶片1100各向异性地蚀刻出这些材料“长条”之后，可执行后续各向同性(例如，湿式)蚀刻操作，以从其中将形成腔的硅晶片1100去除剩余材料。在图13中说明此操作的结果，图13展示根据本公开的一个实施例的通过此两步各向异性及各向同性蚀刻工艺形成的腔1105。如在图14中展示，在去除掩模层1103的剩余物(例如，经由化学及/或机械去除工艺)之后，单片硅结构1400(包含热垫1102及腔1105)准备好进行上文参考图2到10先前更详细描述的过程。
作为在将单片硅结构附接到组合件中的下半导体装置之前用半导体装置预先填充类似于图1或14的单片硅结构的单片硅结构的替代方案，本公开的一些实施例可涉及将单片硅结构附接到半导体装置，背侧减薄单片硅结构以揭露其中的腔，且随后在腔内部安置半导体装置。根据本公开的各种实施例，在图15到20中的过程中的各个阶段处展示形成半导体装置组合件的一种此方法。
转到图15，展示根据本公开的一个方面的在已接合到下半导体装置1401之后的图14的单片硅结构1400。在此方面，单片硅结构1400接合到下半导体装置1401，使得热垫1102耦合到下半导体装置1401的热触点1402。接合操作可为混合接合操作，其中在单片硅结构的电介质1101与形成在下半导体装置1401上方的电介质层1403之间形成电介质-电介质接合(例如，氧化物-氧化物接合)，并且在热垫1102及热触点1402中的对应者之间形成金属-金属接合。
单片硅结构1400在接合到下半导体装置1401之后可进行背侧减薄操作(例如，通过化学机械抛光(CMP)、研磨等)，以从单片硅结1400去除材料的部分，以便暴露腔1105，如在图16中说明。在腔1105因此打开的情况下，半导体装置(例如，个别裸片、经互连裸片的竖直堆叠、装置封装、装置组合件等)1701可安置在腔1105中，且囊封剂(例如，模制材料)1702可安置在半导体装置1701上方(并且任选地围绕半导体装置1701，这取决于半导体装置1701及腔1105的相对大小)，以生产半导体装置组合件1700，如在图17中所展示。此时可执行后续处理步骤(例如，从晶片或面板级单切组合件1700、减薄并提供到下半导体装置1401的外部连接等)(并且为保持本公开的清晰性未说明后续处理步骤)。
替代地，半导体装置组合件1700可进行额外处理操作，以去除囊封材料1702的上覆部分，并且暴露半导体装置1701的背表面，类似于上文参考图4及5所描述的过程，以便减薄组合件1700及/或使组合件为额外连接性做准备。在此方面，图18是半导体装置组合件1800的简化示意性横截面视图，其中类似于图17中所说明的组合件的组合件已经进行背侧减薄操作(例如，通过化学机械抛光(CMP)、研磨等)以去除囊封剂1702的上覆部分，以便暴露(并任选地平坦化)半导体装置1701的背表面并降低组合件1800的整体高度。
在其中半导体装置1701包含用于进一步连接性的背侧触点的实施例中，从覆盖半导体装置1701的背表面的囊封剂1702去除材料的部分可允许将额外装置集成到半导体装置组合件中，如上文关于图6及7更详细描述。在此方面，额外半导体装置可直接附接到半导体装置1701的暴露背侧触点，且接着由一层模制材料囊封(例如，类似于图6中所说明的布置)。替代地，在另一实施例中，一或多个额外经预先填充单片硅结构(例如，类似于图2中所说明的)可接合到图18中所说明的半导体组合件1800以提供具有高装置密度的组合件同时保持良好热性能，而非个别地将额外半导体装置连接到半导体装置1701的暴露背侧触点。在另一实施例中，图15到18中所说明的过程可在图18的组合件1800上迭代执行(例如，在组合件1800上方安置另一单片硅结构1400，减薄单片硅结1400以打开其中的腔1105，在暴露腔中安置额外半导体装置，用模制材料囊封，并且任选地减薄上覆模制材料)，以提供具有高装置密度的组合件同时保持良好热性能。如所属领域的技术人员将容易理解样，可混合、匹配及迭代地重复前述过程，使得可提供半导体装置的额外层级，直到实现所需装置密度。
半导体装置组合件已被说明为形成在下半导体装置1401上方，下半导体装置1401尚未被减薄或提供有背侧触点(例如，在所说明定向上的其下表面上)。图19说明根据本公开的一个方面的通过其可对下半导体装置1401进行减薄并向其提供TSV及背侧触点的过程。如参考图19可见，半导体装置组合件1800通过安置在单片硅结构1400及半导体装置1701的暴露背表面上方的一层粘合剂1902接合到临时载体晶片1901。在由载体晶片1901机械支撑下，下半导体装置1401的背表面可被减薄(例如，通过CMP、研磨等)，以降低组合件的总高度并允许穿过下半导体装置1401的剩余厚度形成TSV 1903。可使用所属领域的技术人员已知的许多方法中的任一者来形成背侧触点(例如，垫、支柱、凸块下金属化(UBM)等)，例如那些承载焊球阵列1904的触点。在另一实施例中，可仅仅通过图19中所说明的减薄操作暴露已在更早的处理阶段处形成在下半导体装置1401中的掩埋TSV，而非在减薄下半导体装置1401之后形成通孔1903。一旦减薄及触点形成完成，就可去除临时载体晶片1901及粘合剂1902，从而形成完成的半导体装置组合件2000，如在图20中所说明。
尽管前述单片硅结构的硅材料享有高导热性，但在一些情况下，在单片硅结构的一些区中包含铜、银、铝或其它高导热金属以进一步增强其热管理能力同时最小化所述结构与组合件中的半导体装置之间的CTE的差异可能是有利的。在此方面，图21到26说明包含金属热量提取结构的单片硅结构的一个实施例的制造及集成。
转到图21，根据本公开的一个实施例，在形成过程的一步骤处，以简化部分横截面视图展示将从其形成单片硅结构的前体结构。前体结构包含硅晶片2100，在其上已形成钝化层2101(例如，电介质材料)，在钝化层2101中可任选地形成一或多个热垫(未说明)。在钝化层2101上方形成掩模层2102，其图案对应于将在硅晶片2100中形成的腔及金属热量提取结构。更特定来说，掩模层2102包含小开口的图案(例如，对应于窄柱状或鳍状结构)，其上覆于硅晶片2100中待形成腔的区及硅晶片2100中待形成金属热量提取结构的区。
如参考图22可见，可将小开口2103至少部分蚀刻到硅晶片2100的厚度中，以从将形成腔的地方移除材料中的一些并创建在其中可镀覆金属热量提取结构的开口。在从硅晶片2100各向异性地蚀刻出将这些材料“长条”之后，接着可形成镀覆操作，以用金属结构填充小开口2103，两者都在其中待形成腔的区及其中待保留金属热量提取结构2105的区中。可去除多余的金属材料(例如，通过CMP操作、研磨操作、湿式蚀刻操作等)，并且可在硅晶片2100上方安置另一掩模结构2106，其开口暴露其中待形成腔的区中的金属材料，但不暴露金属热量提取结构2105。
可执行后续各向同性(例如，湿式)蚀刻操作，以从在其中待形成腔的硅晶片2100去除金属结构及剩余硅材料。图25中说明此操作的结果，图25展示根据本公开的一个实施例的已通过此过程形成的腔2107及金属热量提取结构2105。在去除掩模层2106的剩余物之后(例如，通过化学及/或机械去除工艺)，单片硅结构2500(包含金属热量提取结构2105及腔2107)准备好进行上文参考图2到10及/或15到20先前更详细描述的过程。在此方面，图26说明根据本公开的一个实施例的半导体装置组合件2600的简化示意性横截面视图。组合件2600包含单片硅结构2500，其中安置金属热量提取结构2105用于从下半导体装置2602提取热量(例如，通过与下半导体装置2602中的热触点接触)。组合件2600进一步包含耦合到下半导体装置2602的单片硅结构的腔中的一或多个半导体装置(说明两个)。
如所属领域的技术人员将容易理解，尽管前述实例是用部分横截面图来说明的，其中单个下半导体装置接合到单个单片结构，但本公开的实施例设想晶片级处理，其中包括多个下半导体装置的未经单切晶片接合到晶片级单片硅结构以提供晶片级中间结构，从其可单切个别组合件。替代地，在另一实施例中，经单切单片硅结构可个别地接合到包括多个下半导体装置的未经单切晶片上。在又一实施例中，经单切单片硅结构可个别地接合到经单切下半导体装置。
尽管在前述实例实施例中，单片硅结构已被说明及描述为包含与下半导体装置上的对应热触点接触的热垫或金属热量提取结构，但在其它实施例中可省略这些特征件，并且单片硅结构可在没有任何中间金属结构的情况下接合到下半导体装置的表面。
尽管在前述实例实施例中，单片硅结构已经被说明及描述为包含具有相同深度及平面面积的两个腔以及其中大小类似的半导体装置，但所属领域的技术人员将很容易了解，腔的数目并不是如此有限，并且在其它实施例中的单片硅结构可具有更多或更少的腔、不同平面面积及/或深度的腔以容纳不同大小及形状的半导体装置(或其它电气组件，包含无源电路组件)。
此外，尽管在前述实例实施例中，单片硅结构被说明及描述为安置在与单片硅结构具有相同平面面积的下半导体裸片上，但所属领域的技术人员将容易了解，单片硅结构可用于其它布置(例如，接合到多于一个下裸片，接合到装置衬底等)，并且无需具有与在其上所承载的装置相同的平面面积。
根据本公开的一个方面，上文说明及描述的半导体装置组合件可包含存储器裸片，例如动态随机存取存储器(DRAM)裸片、“与非”(NAND)存储器裸片、“或非”(NOR)存储器裸片、磁随机存取存储器(MRAM)裸片、相变存储器(PCM)裸片、铁电随机存取存储器(FeRAM)裸片、静态随机存储器(SRAM)裸片等。在其中在单个组合件中提供多个裸片的实施例中，半导体装置可为相同种类的存储器裸片(例如，两者均为NAND、两者均为DRAM等)或不同种类的存储器裸片(例如，一者为DRAM且一者为NAND等)。根据本公开的另一方面，上文所说明及描述的组合件的半导体裸片可包含逻辑裸片(例如，控制器裸片、处理器裸片等)，或者逻辑及存储器裸片的混合(例如，存储器控制器裸片及由其控制的存储器裸片)。
上文描述的半导体装置及半导体装置组合件中的任一者可并入无数更大及/或更复杂的系统中的任一者中，其代表性实例是图27中示意性展示的系统2700。系统2700可包含半导体装置组合件(例如，或离散半导体装置)2702、电源2704、驱动器2706、处理器2708及/或其它子系统或组件2710。半导体装置组合件2702可包含大体上类似于上文描述的半导体装置的特征件的特征件。所得系统2700可执行各种各样的功能中的任一者，例如存储器存储、数据处理及/或其它合适的功能。因此，代表性系统2700可包含(但不限于)手持装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、交通工具、器械及其它产品。系统2700的组件可被容置在单个单元中或分布在多个互连单元上方(例如，通过通信网络)。系统2700的组件还可包含远程装置及各种各样的计算机可读媒体中的任一者。
本文中所论述的装置(包含存储器装置)可形成于半导体衬底或裸片(例如硅、锗、硅锗合金、砷化镓、氮化镓等)上。在一些情况下，衬底是半导体晶片。在其它情况中，衬底可为绝缘体上硅(SOI)衬底，例如玻璃上硅(SOG)或蓝宝石上硅(SOP)，或另一衬底上的半导体材料的外延层。可通过使用各种化学物种(包含但不限于：磷、硼或砷)的掺杂来控制衬底或衬底子区域的导电性。掺杂可在衬底的初始形成或生长期间通过离子植入或通过任何其它掺杂方法而执行。
可在硬件、由处理器执行的软件、固件或其任何组合中实施本文中描述的功能。其它实例及实施方案是在本公开及所附权利要求书的范围内。实施功能的特征件还可在物理上定位在各种位置处，包含经分布使得在不同物理位置处实施功能的部分。
如本文中使用，包含权利要求书中，如在项目列表(例如，前面标有例如“中的至少一者”或“中的一或多者”的短语的项目列表)中使用的“或”指示包含列表使得(例如)A、B或C中的至少一者的列表意味着A或B或C或AB或AC或BC或ABC(即，A及B及C)。此外，如本文中使用，短语“基于”不应理解为对一组封闭条件的引用。举例来说，描述为“基于条件A”的实例步骤可基于条件A及条件B两者而不脱离本公开的范围。换句话说，如本文中使用，短语“基于”应以与短语“至少部分基于”的相同方式理解。
如本文中所使用，术语“垂直”、“横向”、“上”、“下”、“之上”及“之下”可指代鉴于图中所展示的定向的半导体装置中的特征件的相对方向或位置。举例来说，“上”或“最上”可指代定位成比另一构件更接近于页的顶部的构件。然而，这些术语应被广义解释为包含具有其它定向(例如其中顶部/底部、上方/下方、之上/之下及左/右可取决于定向而互换的相反或倾斜定向)的半导体装置。
应注意，上文所描述的方法描述可能的实施方案，且操作及步骤可经重新布置或以其它方式修改，且其它实施方案是可能的。此外，可组合来自方法中的两者或两者以上的实施例。
可从上文了解，本文已为了说明而描述本发明的特定实施例，但可在不背离本发明的范围的情况下作出各种修改。而是，在前述描述中，讨论众多特定细节以提供本技术的实施例的透彻及可行描述。然而，相关领域的技术人员将认识到，可在无一或多个特定细节的情况下实践本公开。在其它例子中，未展示或未详细描述通常与存储器系统及装置相关联的众所周知结构或操作以免使本技术的其它方面不清楚。一般来说，应了解，除本文中所公开的特定实施例之外，各种其它装置、系统及方法也可在本技术的范围内。

Claims (20)

1.一种半导体装置组合件，其包括：
第一半导体装置，其在其上表面上包含多个电触点；
单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面；以及
第二半导体装置，其安置在所述腔中，所述第二半导体装置包含多个互连件，所述多个互连件各自可操作地耦合到所述多个电触点中的对应者。
2.根据权利要求1所述的半导体装置组合件，其中所述单片硅结构具有在大小及形状上对应于所述第一半导体装置的平面区域的平面区域。
3.根据权利要求1所述的半导体装置组合件，其中所述第一半导体装置的所述上表面包含与所述单片硅结构的所述下表面直接接触的多个热触点。
4.根据权利要求3所述的半导体装置组合件，其中所述单片硅结构包含与所述多个热触点直接接触并且完全延伸穿过所述单片硅结构的所述主体的多个金属热量提取结构。
5.根据权利要求4所述的半导体装置组合件，其中所述多个金属热量提取结构中的每一者包括金属材料的柱或鳍。
6.根据权利要求1所述的半导体装置组合件，其中所述单片硅结构的所述下表面通过电介质接合而接合到所述第一半导体装置的所述上表面。
7.根据权利要求1所述的半导体装置组合件，其中所述多个互连件是第一多个互连件，所述腔是第一腔，所述单片结构包含第二腔，所述第二腔从所述下表面完全延伸穿过所述单片硅结构的所述主体到所述单片硅结构的所述顶部表面，并且进一步包括安置在所述第二腔中并且包含第二多个互连件的第三半导体装置，所述第二多个互连件各自可操作地耦合到所述多个电触点中的对应者。
8.根据权利要求1所述的半导体装置组合件，其中所述第二半导体装置包含电耦合的存储器装置的竖直堆叠。
9.根据权利要求1所述的半导体装置组合件，其中所述第一半导体装置的所述上表面及所述单片硅结构的所述下表面中的一或多者包含重布层。
10.一种半导体装置组合件，其包括：
第一半导体装置，其包含上表面；
单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面；以及
第二半导体装置，其直接耦合到所述第一半导体装置并且安置在所述腔中，使得所述第二半导体装置的背表面与所述单片硅结构的所述顶部表面大体上共面。
11.根据权利要求10所述的半导体装置组合件，其中所述单片硅结构包含多个金属热量提取结构，所述多个金属热量提取结构与所述腔横向间隔开并且完全延伸穿过所述单片硅结构的所述主体。
12.根据权利要求11所述的半导体装置组合件，其中所述多个金属热量提取结构中的每一者包括金属材料的柱或鳍。
13.根据权利要求11所述的半导体装置组合件，其中所述多个金属热量提取结构中的每一者具有与所述单片硅结构的所述顶部表面大体上共面的暴露上表面。
14.根据权利要求10所述的半导体装置组合件，其进一步包括安置在所述第二半导体装置的所述背表面上并且电耦合到所述背表面的第三半导体装置。
15.根据权利要求14所述的半导体装置组合件，其中所述第三半导体装置由模制材料囊封。
16.根据权利要求15所述的半导体装置组合件，其中所述第三半导体装置安置在第二单片硅结构的第二腔中，所述第二单片硅结构安置在所述第一单片硅结构上方。
17.一种半导体装置组合件，其包括：
第一半导体装置，其包含上表面；
第二半导体装置，其直接由所述第一半导体装置的上表面承载；以及
单片硅结构，其具有与所述第一半导体装置的所述上表面接触的下表面，所述单片硅结构包含腔，所述腔从所述下表面完全延伸穿过所述单片硅结构的主体到所述单片硅结构的顶部表面，
其中所述单片硅结构完全环绕所述第二半导体装置的多个侧壁。
18.根据权利要求17所述的半导体装置组合件，其中所述单片硅结构包含多个金属热量提取结构，所述多个金属热量提取结构与所述腔横向间隔开并且完全延伸穿过所述单片硅结构的所述主体。
19.根据权利要求18所述的半导体装置组合件，其中所述多个金属热量提取结构中的每一者包括金属材料的柱或鳍。
20.根据权利要求18所述的半导体装置组合件，其中所述多个金属热量提取结构中的每一者具有与所述单片硅结构的所述顶部表面大体上共面的暴露上表面。
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TW202326963A (zh) 2023-07-01
KR20230063317A (ko) 2023-05-09

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