CN112086443A - 封装体及其形成方法 - Google Patents

封装体及其形成方法 Download PDF

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Publication number
CN112086443A
CN112086443A CN201910993012.1A CN201910993012A CN112086443A CN 112086443 A CN112086443 A CN 112086443A CN 201910993012 A CN201910993012 A CN 201910993012A CN 112086443 A CN112086443 A CN 112086443A
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Prior art keywords
substrate
die
conductive
layer
forming
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CN201910993012.1A
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吴俊毅
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112086443A publication Critical patent/CN112086443A/zh
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Abstract

一种半导体封装体及其形成方法。在实施例中，一种封装体包括：衬底；第一管芯，设置在衬底内；重布线结构，位于衬底及第一管芯之上；以及经包封器件，位于重布线结构之上，重布线结构将第一管芯耦合到所述经包封器件。

Description

封装体及其形成方法
技术领域
本发明实施例涉及一种封装体及其形成方法。
背景技术
半导体行业通过不断缩小最小特征大小来不断地提高各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，以使得更多的组件(因而更多功能)能够被集成到给定区域中。具有高功能的集成电路需要许多输入/输出接垫。然而，对于小型化很重要的应用而言可能需要小的封装体。
集成扇出型(integrated fan-out，InFO)封装技术正变得越来越受欢迎，尤其是当与晶片级封装(wafer-level packaging，WLP)技术相结合时。InFO封装体可包括封装在封装体中的集成电路，所述封装体通常包括重布线层(redistribution layer，RDL)或后钝化后内连线，所述重布线层或后钝化内连线用于对封装体的接触垫进行扇出型配线，以使得可以比集成电路的接触垫更大的节距来进行电接触。所得封装结构以相对低的成本及高性能封装来提供高功能密度。
发明内容
根据本发明的实施例，一种封装体包括衬底、第一管芯、重布线结构以及经包封器件。第一管芯设置在所述衬底内。重布线结构位于所述衬底及所述第一管芯之上。经包封器件位于所述重布线结构之上，所述重布线结构将所述第一管芯耦合到所述经包封器件。
根据本发明的实施例，一种形成封装体的方法包括：在衬底中形成空腔；将第一管芯贴合到所述衬底，所述第一管芯设置在所述空腔内；在所述衬底的第一侧以及所述第一管芯之上形成重布线结构；以及将半导体器件贴合到所述重布线结构，所述半导体器件包括被包封体包封的第二管芯。
根据本发明的实施例，一种形成封装体的方法包括：在衬底中形成空腔；将所述衬底安装在载体上；将第一器件贴合到所述衬底及所述空腔内；以及将第二器件耦合到所述第一器件，所述第二器件被包封体包封，所述第二器件在垂直于所述衬底的主表面的方向上设置在所述第一器件之上。
附图说明
结合附图阅读以下详细说明会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1示出根据一些实施例的核心衬底。
图2示出根据一些实施例在核心衬底中形成开口。
图3示出根据一些实施例在核心衬底中形成导电迹线及导电插塞。
图4示出根据一些实施例在核心衬底之上形成介电层及保护层。
图5示出根据一些实施例在核心衬底中形成空腔。
图6示出根据一些实施例将衬底接合到载体。
图7A示出根据一些实施例将第一管芯贴合在空腔内。
图7B示出根据一些实施例的多层陶瓷电容器。
图8示出根据一些实施例形成环绕无源器件的底部填充胶。
图9到图15示出根据一些实施例在衬底及无源器件之上形成前侧重布线结构。
图16示出根据一些实施例在前侧重布线结构中形成开口。
图17A示出根据一些实施例在前侧重布线结构上形成导电连接件。
图17B及图17C示出根据一些实施例在载体之上形成的第一封装体。
图18示出根据一些实施例将载体剥离。
图19示出根据一些实施例对经封装半导体器件进行接合。
图20示出根据一些实施例对环形结构进行贴合。
图21示出根据一些实施例在衬底的背侧上形成导电连接件。
[符号的说明]
100、154、164：绝缘层；
101：第一封装体；
102：导电层；
104：衬底；
106、172：开口；
108：第一导电迹线；
110：导电插塞；
112：第二导电迹线；
114、134、138、144、148、158、170：介电层；
116：保护层；
118：空腔；
120：空腔衬底；
122：载体衬底；
124：释放层；
126：第一管芯；
128、196：粘合剂；
130、222：连接端子；
132：底部填充胶；
136、142、146、150：金属化图案；
140：前侧重佈线结构；
152、162：导电柱；
156、160、166：导电迹线；
168：凸块下金属；
174、198：导电连接件；
180：经封装半导体器件；
182：处理器管芯；
184：管芯；
186：包封材料；
188：集成扇出型结构；
190：外部接触件；
192：底部填充材料；
194：环形结构；
200：系统集成衬底(SoIS)；
220：MLCC；
224：陶瓷；
226：电极；
T1：厚度。
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，在以下说明中，在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外，本公开在各种实例中可重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见，且自身并不表示所讨论的各个实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。除附图中所绘示的取向以外，所述空间相对性用语旨在涵盖器件在使用或操作中的不同取向。设备可被另外取向(旋转90度或处于其他取向)，且本文所使用的空间相对性用语可同样相应地作出解释。
各种实施例涉及经封装半导体器件及其形成方法。经封装半导体器件可为系统集成衬底(system on integrated substrate，SoIP)封装体、系统级封装体(system-in-package，SiP)等。可在核心衬底中形成空腔，且可将例如多层陶瓷电容器(multilayerceramic capacitor，MLCC)、集成无源器件(integrated passive device，IPD)、集成电压调节器(integrated voltage regulator，IVR)、静态随机存取存储器(static randomaccess memory，SRAM)等电子组件贴合到空腔中的核心衬底。可在核心衬底及电子组件之上形成重布线层(redistribution layer，RDL)，且可将例如晶片上芯片(chip-on-wafer，CoW)、集成扇出型(InFO)封装体、管芯或另一封装体等电子器件贴合到重布线层。使电子组件嵌入核心衬底中会缩短电子组件与电子器件之间的距离，此会减小电子组件与电子器件之间的电压降，并提高经封装半导体器件的电源完整性及总体性能。
首先参照图1，图1示出根据一些实施例的衬底104，衬底104包括绝缘层100以及位于绝缘层100的两侧上的导电层102。衬底104可为核心衬底(core substrate)。在一些实施例中，衬底104是双面覆铜叠层板(double-sided copper clad laminate，CCL)。绝缘层100可为有机衬底、陶瓷衬底、预浸渍复合纤维(预浸体)、味之素构成膜(Ajinomoto Build-upFilm，ABF)、纸、玻璃纤维、无纺玻璃织物、其他绝缘材料或其组合。导电层102可为叠层或形成在绝缘层100的相对侧上的一层或多层铜、镍、铝、其他导电材料或其组合。
参照图2，在衬底104中形成多个开口106。在一些实施例中，开口106是通过激光钻孔来形成。也可使用其他工艺，例如机械钻孔、刻蚀等。在俯视图中，开口106可具有矩形、圆形或其他形状。
参照图3，根据一些实施例，填充开口106(参见图2)以形成多个导电插塞110、多个第一导电迹线108及多个第二导电迹线112。导电迹线(例如第一导电迹线108及第二导电迹线112)可用于形成布线线以对电信号进行重布线，或者用作管芯连接件可贴合的管芯连接件接垫。在开口106内沉积导电材料之前，可执行表面准备工艺。表面准备工艺可包括用一种或多种清洁溶液(例如硫酸、铬酸、中和碱性溶液、水冲洗液等)来清洁衬底104的被暴露表面(例如导电层102的表面及开口106中的绝缘层100的表面)，以移除或减少污物、油和/或天然氧化物膜。可执行除胶渣(desmear)工艺来清洁开口106附近的区域，所述区域可能已被绝缘层100的已移除以形成开口106的材料弄脏。除胶渣可以机械方式(例如，用湿浆料中的细磨料进行喷砂)、化学方式(例如，用有机溶剂的组合、高锰酸盐等进行冲洗)或者通过机械除胶渣与化学除胶渣的组合来实现。在清洁后，可使用化学调节剂(chemicalconditioner)进行处理，此有利于吸附在随后的无电镀覆期间使用的活化剂。在一些实施例中，在调节步骤之后可对导电层102进行微刻蚀，以将导电层102的导电表面微粗糙化，从而在导电层102与稍后沉积的导电材料之间进行更好地接合。
形成导电插塞110、第一导电迹线108及第二导电迹线112可包括：形成图案化掩模层，且利用金属无电镀覆技术在图案化掩模层的开口中选择性地沉积导电材料(例如，铜、其他金属、金属合金等)。图案化掩模层可通过以下方式来形成：用光刻胶层来涂布表面、将光刻胶层曝光于光学图案、以及对被曝光的光刻胶层进行显影以在光刻胶层中形成开口，所述开口界定可选择性地沉积导电材料的区域的图案。
在形成第一导电迹线108及第二导电迹线112之后，可剥除图案化掩模层(例如，光刻胶)。可使用合适的刻蚀工艺来移除导电层102的曾被图案化掩模层覆盖的部分。移除导电层102的不需要的部分可防止在被图案化掩模层暴露的区域中形成的导电特征之间的不需要的电短路。导电插塞110、第一导电迹线108及第二导电迹线112可以上述方式形成在衬底104的两侧上。图3所示剖视图示出在导电层102如上所述被刻蚀之后的衬底104的状态。
如下文更详细论述，衬底104将充当形成包含空腔的核心衬底(空腔衬底120)(未在图3中示出，但在图5中示出)的基底。在图3中，第一导电迹线108形成在绝缘层100的一侧上，在后续处理步骤期间在绝缘层100的所述侧中形成空腔118(未在图3中示出，但在图5中示出)。根据一些实施例，第一导电迹线108可从随后可形成空腔的区域(例如，此实例中为最内导电插塞110之间的区域)省略。
尽管在此实例中未示出，然而理解到可重复地执行使用覆金属叠层板、形成延伸穿过覆金属叠层板的开口、形成图案化导电迹线层(例如，使用无电沉积或电镀等)以及移除不需要的金属包覆层的方法，以垂直地堆叠绝缘材料与导电迹线的多个交替层以及导电插塞，从而垂直地连接导电迹线的相邻层。
参照图4，衬底104之上且分别在第一导电迹线108及第二导电迹线112之上形成介电层114及保护层116。在一些实施例中，介电层114是由可使用光刻掩模(lithographymask)进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺、苯环丁烷(benzocyclobuten，BCB)等感光性材料。介电层114可通过旋转涂布、叠层、化学气相沉积(chemical vapor deposition，CVD)、类似工艺或其组合来形成。将介电层114图案化以形成暴露出第一导电迹线108的部分的开口。当介电层114是感光性材料时，图案化可通过将介电层114暴露于光并对介电层114进行显影来实现。介电层114也可由以下不具有感光性的材料形成，例如氮化硅、氧化硅、磷硅酸盐玻璃(phosphosilicateglass，PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass，BPSG)等。在介电层114是由非感光性的材料形成的实施例中，介电层114可通过经由图案化光刻胶掩模用合适的刻蚀工艺(例如，各向异性反应离子刻蚀)进行刻蚀来图案化。
在各种实施例中，保护层116可为形成在第二导电迹线112之上的阻焊剂等，以保护绝缘层100的区域免受外部损坏。可将保护层116图案化以形成暴露出第二导电迹线112的部分的开口。在保护层116由感光性材料形成的实施例中，图案化可通过将保护层116暴露于光并对保护层116进行显影来实现。在保护层116是由非感光性的材料形成的实施例中，保护层116可通过经由图案化光刻胶掩模用合适的刻蚀工艺(例如，各向异性反应离子刻蚀)进行刻蚀来图案化。暴露出第二导电迹线112的开口可用作管芯连接件接垫，导电连接件198(未在图4中示出，但在图21中示出)可随后贴合到管芯连接件接垫。
在图5中，根据一些实施例，通过移除绝缘层100的一部分来形成空腔(cavity)118。移除绝缘层100的所述部分不会影响位于绝缘层100的通过移除工艺而凹陷的同一侧上的第一导电迹线108。如上参照图3所述，用于形成第一导电迹线108的图案化掩模可被设计成排除第一导电迹线108形成在绝缘层100的形成有空腔118的一部分之上的情况。移除材料以形成空腔118可通过计算机数控(computer numeric control，CNC)加工工艺来执行，其中材料是通过机械钻孔来移除。如图5所示，所得结构是空腔衬底120。空腔衬底120的绝缘层100可具有从约25μm到约2,000μm(例如约250μm或约500μm)的厚度T1。空腔118可具有从约10μm到约1,000μm(例如约70μm或约400μm)的深度。空腔118可具有从约1mm乘1mm到约20mm乘20mm(例如约1.5mm乘1.5mm或约5.0mm乘4.0mm)的面积。在一些实施例中，绝缘层100的一部分可沿着空腔118的底部保留，且可具有从约20μm到约1600μm(例如约30μm或约800μm)的厚度。也可使用其他工艺来形成空腔118，例如激光钻孔、刻蚀和/或类似工艺。
在图6中，根据一些实施例，使用释放层124将空腔衬底120贴合到载体衬底122。如图6所示，空腔衬底120可使用释放层124贴合到载体衬底122，以使空腔118与释放层124相对。载体衬底122可为玻璃载体衬底、陶瓷载体衬底等。释放层124可为聚合物系材料、环氧系热释放材料(例如光-热转换(light-to-heat-conversion，LTHC)释放涂层)或者紫外(ultra-violet，UV)胶(例如，当暴露于紫外光时失去其粘合性质的胶)。释放层124可有助于在后续处理期间移除载体衬底122。释放层124可在后续处理期间与载体衬底122一起被移除。
在图7A中，根据一些实施例，将第一管芯126放置在空腔118(示于图6中)内。第一管芯126可使用拾取及放置(pick-and-place，PnP)工具放置在空腔118内。第一管芯126可为无源器件，例如多层陶瓷芯片(multilayer ceramic chip，MLCC)电容器；集成无源器件(IPD)；集成电压调节器(integrated voltage regulator，IVR)等或其组合；或者有源器件，例如存储器管芯(例如，静态随机存取存储器(SRAM)管芯、动态随机存取存储器(dynamic random-access memory，DRAM)管芯、高带宽存储器(high bandwidth memory，HBM)管芯等)、逻辑芯片、模拟芯片、微机电系统(microelectromechanical system，MEMS)芯片、射频(radio frequency，RF)芯片、类似芯片或其组合。在一些实施例中，通过粘合剂128将第一管芯126粘合到绝缘层100。尽管图7A示出将一个第一管芯126放置在空腔118中，然而应理解也可将多个管芯或器件放置在空腔衬底120的空腔118中。例如，在一些实施例中，第一管芯126可为彼此横向邻近放置和/或堆叠在彼此上的多个器件，其中所述多个器件可具有相同或不同的大小。在将第一管芯126放置到空腔衬底120上之前，可根据适用的制造工艺对第一管芯126进行处理，以形成相应的器件结构。第一管芯126可包括进行外部连接的连接端子130(例如，铝垫、铜垫等)。第一管芯126可具有从约30μm到约350μm的高度、从约0.5mm到约0.8mm的长度以及从约0.5mm到约0.8mm的宽度。
粘合剂128可贴合到第一管芯126的背侧，且可将第一管芯126贴合到绝缘层100。粘合剂128可为任何合适的粘合剂、环氧树脂、管芯贴合膜(die attach film，DAF)等。粘合剂128可在将第一管芯126单体化之前施加到第一管芯126的背侧。可例如通过锯切(sawing)或切割(dicing)而将第一管芯126单体化，并使用例如PnP工具通过粘合剂128而将第一管芯126粘合到绝缘层100。在一些实施例中，粘合剂128可在将第一管芯126放置在空腔118中之前贴合到空腔衬底120。
图7B示出可用作第一管芯126的MLCC 220。如图7B所示，MLCC 220包括夹置在陶瓷224层之间的多个电极226。MLCC 220还包括用于外部连接的多个连接端子222。
在图8中，根据一些实施例，在第一管芯126的多个侧壁与空腔衬底120之间形成底部填充胶132。底部填充胶132可在第一管芯126被贴合之后通过毛细管流动工艺(capillary flow process)而形成，或可在第一管芯126被贴合之前通过合适的沉积方法而形成。底部填充胶132可为例如模制化合物、环氧树脂、底部填充胶、模制底部填充胶(molding underfill，MUF)、树脂等材料。底部填充胶132可减小第一管芯126与空腔衬底120之间的应力，且可帮助将第一管芯126固定在空腔118中。如图8所示，底部填充胶132的上表面可为凹面；然而，在一些实施例中，底部填充胶132的上表面可为凸面或平面。
图9到图15示出根据一些实施例在第一管芯126的连接端子130及空腔衬底120的第一导电迹线108之上形成前侧重布线结构140(示于图15中)。前侧重布线结构140包括介电质与导电迹线的交替层的垂直堆叠。每层导电迹线通过介电层与垂直邻近的导电迹线层分隔开。导电迹线延伸穿过下伏介电层，以形成用于将垂直邻近的导电迹线内连的导通孔。前侧重布线结构140与空腔衬底120一起形成第一封装体101(示于图15中)。
在图9中，在空腔衬底120、底部填充胶132及第一管芯126之上形成介电层134。在一些实施例中，介电层134是由可使用光刻掩模进行图案化的聚合物形成，所述聚合物可为例如PBO、聚酰亚胺、BCB等感光性材料。介电层134可通过旋转涂布、叠层、化学气相沉积(CVD)、类似工艺或其组合来形成。将介电层134图案化以形成暴露出多个连接端子130及多个第一导电迹线108的部分的多个开口。当介电层134是感光性材料时，图案化可通过将介电层134暴露于光来实现。介电层134也可由以下不具有感光性的材料形成，例如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)等。在介电层134是由非感光性的材料形成的实施例中，介电层134可通过经由图案化光刻胶掩模用合适的刻蚀工艺(例如，各向异性反应离子刻蚀)进行刻蚀来图案化。
在图10中，在介电层134上形成金属化图案136且金属化图案136延伸穿过介电层134。作为形成金属化图案136的实例，在介电层134之上形成晶种层(未单独示出)。在一些实施例中，晶种层为金属层，所述金属层可为单一层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。晶种层可利用例如物理气相沉积(physical vapor deposition，PVD)、CVD等来形成。接着在晶种层上形成光刻胶(未单独示出)并将所述光刻胶图案化。光刻胶可通过旋转涂布等形成，可暴露于图案化的光或另一图案化的能量源，且可暴露于显影剂以移除光刻胶的被暴露部分或未暴露部分。光刻胶的图案对应于金属化图案136。所述图案化穿过光刻胶形成开口以暴露出晶种层。在光刻胶的开口中且在晶种层的被暴露部分上形成导电材料(未单独示出)。所述导电材料可通过例如电镀、无电镀覆等镀覆来形成。导电材料可包含例如铜、钛、钨、铝等金属。接着，移除光刻胶以及晶种层的未形成导电材料的部分。光刻胶可例如使用氧等离子体等、通过可接受的灰化工艺或剥除工艺来移除。一旦光刻胶被移除，便使用可接受的刻蚀工艺(例如湿式刻蚀或干式刻蚀)来移除晶种层的被暴露部分。晶种层的其余部分及导电材料会形成金属化图案136。金属化图案136包括沿介电层134的顶表面形成的导电迹线以及穿过介电层134的导通孔。通孔将金属化图案136的导电迹线电连接并实体连接到介电层134正下方的金属图案(例如，第一导电迹线108及连接端子130)。
形成介电层134(参照图9论述)及金属化图案136的导电迹线及导通孔(参照图10论述)的方法仅被阐述作为实例。应理解，形成介电层134及金属化图案136的工艺可基于设计规格(例如，图案的期望最小尺寸)而变化。例如，在一些实施例中，可利用镶嵌工艺(例如，单镶嵌工艺或双镶嵌工艺)。前侧重布线结构140可通过垂直地堆叠附加介电层及金属化图案来构建。
图11示出在介电层134及金属化图案136的顶表面之上形成的附加的介电层138、介电层144及介电层148。图11中还示出金属化图案142、金属化图案146及金属化图案150。金属化图案142、金属化图案146及金属化图案150包括沿相应介电层138、介电层144及介电层148的顶表面形成的导电迹线以及延伸穿过相应介电层138、介电层144及介电层148的导通孔。金属化图案142、金属化图案146及金属化图案150的通孔将金属化图案142、金属化图案146及金属化图案150的导电迹线电连接并实体连接到相应介电层138、介电层144及介电层148正下方的相应金属化图案(例如，相应金属化图案136、金属化图案142及金属化图案146)。可重复与以上关于介电层134及金属化图案136阐述的工艺、技术及材料相似的工艺、技术及材料，以形成介电层138、介电层144及介电层148以及金属化图案142、金属化图案146及金属化图案150。
在图12中，在金属化图案150上形成多个导电柱152。作为形成导电柱152的实例，在介电层148及金属化图案150之上形成晶种层(未单独示出)。在一些实施例中，晶种层为金属层，所述金属层可为单一层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。晶种层可使用例如PVD、CVD等来形成。接着在晶种层上形成光刻胶(未单独示出)并将所述光刻胶图案化。光刻胶可通过旋转涂布等形成，可暴露于图案化的光或另一图案化的能量源，且可暴露于显影剂以移除光刻胶的被暴露部分或未暴露部分。光刻胶的图案对应于导电柱152。所述图案化穿过光刻胶形成开口以暴露出晶种层。在光刻胶的开口中且在晶种层的被暴露部分上形成导电材料(未单独示出)。所述导电材料可通过例如电镀、无电镀覆等镀覆来形成。导电材料可包含例如铜、钛、钨、铝等金属。接着，移除光刻胶以及晶种层的未形成导电材料的部分。光刻胶可例如使用氧等离子体等、通过可接受的灰化工艺或剥除工艺来移除。一旦光刻胶被移除，便使用可接受的刻蚀工艺(例如湿式刻蚀或干式刻蚀)来移除晶种层的被暴露部分。晶种层的其余部分及导电材料会形成导电柱152。导电柱152电连接并实体连接到金属化图案150。
现在参照图13，可通过以下方式使导电柱152嵌于绝缘层154中：例如，层叠例如ABF或预浸体等积层膜，且使用回蚀或平坦化工艺(例如化学机械抛光(chemical-mechanical polishing，CMP)、研磨等)来暴露出导电柱152的顶表面。在一些实施例中，绝缘层154可沉积为模制到介电层148及金属化图案150上并环绕导电柱152的液体模制化合物。
在图14中，在导电柱152及绝缘层154之上形成多个导电迹线156。导电迹线156可使用与以上关于图10所示的形成金属化图案136阐述的工艺、技术及材料相似的工艺、技术及材料来形成，其中沉积晶种层，在晶种层之上形成图案化掩模，执行镀覆工艺以形成金属化图案，移除图案化掩模，且移除晶种层的未使用部分。
在图15中，在导电迹线156及绝缘层154之上形成介电层158、多个导电迹线160、多个导电柱162、绝缘层164、多个导电迹线166及多个凸块下金属(under-bumpmetallization，UBM)168。介电层158可使用与以上关于图9所示的形成介电层134阐述的工艺、技术及材料相似的工艺、技术及材料来形成。导电迹线160及导电迹线166以及导电柱162可使用与以上关于图10所示的形成金属化图案136阐述的工艺、技术及材料相似的工艺、技术及材料来形成，其中沉积晶种层，在晶种层之上形成图案化掩模，执行镀覆工艺以形成金属化图案，移除图案化掩模，且移除晶种层的未使用部分。尽管图15中未示出，然而可形成延伸穿过介电层158并将导电迹线160电连接到导电迹线156的导通孔。绝缘层164可使用与以上关于图13所示的形成绝缘层154阐述的工艺、技术及材料相似的工艺、技术及材料来形成。
UBM 168可形成在绝缘层164及导电柱162之上。UBM 168包括可焊接金属表面，所述可焊接金属表面可用作随后形成的焊料凸块(例如，图17A所示的导电连接件174)与前侧重布线结构140之间的界面。如图15所示，UBM 168可电连接并实体连接到导电柱162。UBM168可使用与图10所示的用于形成金属化图案136的工艺、技术及材料相似的工艺、技术及材料来形成。然后可使用与以上关于图9所示的形成介电层134阐述的工艺、技术及材料相似的工艺、技术及材料在绝缘层164、导电迹线166及UBM 168之上形成介电层170。
可在前侧重布线结构140中形成更多或更少的介电层、绝缘层、金属化图案、导电迹线及导电柱。在一些实施例中，前侧重布线结构140可包括1到10个介电层/绝缘层；然而，前侧重布线结构140可为可选的，且在一些实施例中可不包括前侧重布线结构140。如果将形成更少的介电层及金属化图案，则可省略以上论述的步骤及工艺。如果将形成更多介电层及金属化图案，则可重复以上论述的步骤及工艺。介电层134、介电层138、介电层144、介电层148、介电层158及介电层170中的每一者以及绝缘层154及绝缘层164中的每一者可具有从约5μm到约100μm(例如约30μm)的厚度。
在上述实施例中，在前侧重布线结构140中包括两个绝缘层(绝缘层154及绝缘层164)。绝缘层154及绝缘层164可由模制化合物材料形成，所述模制化合物材料具有比用于形成介电层134、介电层138、介电层144、介电层148、介电层158及介电层170的介电材料更低的阻抗。如此，绝缘层154及绝缘层164可包括在前侧重布线结构140中，以控制前侧重布线结构140的阻抗并将前侧重布线结构的阻抗匹配到期望值。例如，包括绝缘层154及绝缘层164的前侧重布线结构140的阻抗可介于约90Ω与约100Ω之间，例如约100Ω。
在图16中，将介电层170图案化以形成暴露出多个UBM 168的部分的多个开口172。当介电层170是感光性材料时，图案化可通过将介电层170暴露于光来实现。在介电层170是由非感光性的材料形成的实施例中，介电层170可通过经由图案化光刻胶掩模用合适的刻蚀工艺(例如，各向异性反应离子刻蚀)进行刻蚀来图案化。
在图17A中，在多个UBM 168上形成多个导电连接件174。导电连接件174可为球栅阵列(ball grid array、BGA)连接件、焊料球、导电柱、受控塌陷芯片连接(controlledcollapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金技术(electrolessnickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导电连接件174可包含例如焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合等导电材料。在一些实施例中，导电连接件174是通过利用例如蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ball placement)等工艺在图16所示结构之上初始地形成焊料层来形成。一旦焊料层已形成，则可执行回焊(reflow)以便将焊料材料成型成期望的凸块形状。在另一实施例中，导电连接件174为通过溅镀(sputtering)、印刷、电镀、无电镀覆、CVD等而形成的导电柱(例如铜柱)。导电连接件174可为无焊料的，且可具有实质上垂直的侧壁。在一些实施例中，在导电柱的顶部上形成金属盖层(metal cap layer)(未单独示出)。金属盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料或其组合，且可通过镀覆工艺来形成。
可在单个载体衬底122上形成多个第一封装体101。如图17B所示，第一封装体101可具有矩形形状，载体衬底122可具有圆的形状(例如圆形形状)，且载体衬底122可被称为晶片。如图17C所示，第一封装体101可具有矩形形状，载体衬底122可具有矩形形状，且载体衬底122可被称为面板。第一封装体101可例如通过锯切、切割等彼此单体化。第一封装体101可在移除载体衬底122之前被单体化。尽管在图17B中示出四个第一封装体101且在图17C中示出九个第一封装体101，然而可在载体衬底122上形成任何数目的第一封装体101，例如从单个第一封装体101到数千个第一封装体101。
在图18中，根据一些实施例，执行载体衬底剥离(carrier substrate de-bonding)工艺以将载体衬底122从空腔衬底120的保护层116脱离(剥离)。在释放层124是光敏粘合剂的实施例中，所述剥离可通过将例如激光或紫外光等光投射在释放层124上以使得释放层124分解且可移除载体衬底122来执行。可执行清洁工艺以从保护层116移除释放层124的残留物。将载体衬底122脱离会暴露出保护层116及其中的多个开口。
在图19中，将经封装半导体器件180接合到导电连接件174。根据实施例，经封装半导体器件180可例如通过拾取及放置机器(未单独示出)布置在前侧重布线结构140之上。然而，可利用将经封装半导体器件180布置在前侧重布线结构140上的任何其他替代方法。
在实施例中，经封装半导体器件180可包括处理器管芯182(例如，赛斯灵处理单元(Xilinx processing unit，xPU))，例如中央处理器(central processing unit，CPU)、微控制单元(micro control unit，MCU)、图形处理单元(graphics processing unit，GPU)、应用处理器(application processor，AP)等。经封装半导体器件180还可包括附加管芯184，例如存储器管芯(例如动态随机存取存储器(DRAM)管芯、宽输入/输出(input/output，I/O)管芯、磁性随机存取存储器(magnetic random-access memory，MRAM)管芯、电阻式随机存取存储器(resistive random-access memory，RRAM)管芯、与非(NAND)管芯、静态随机存取存储器(SRAM)管芯等)、存储器立方体(例如高带宽存储器(HBM)、混合存储器立方体(hybrid memory cube，HMC)等)、高数据速率收发器管芯、I/O接口管芯、集成无源器件(IPD)管芯、电源管理管芯(例如，电源管理集成电路(power management integratedcircuit，PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)、单片三维异质芯片堆叠管芯(monolithic 3Dheterogeneous chiplet stacking die)等或其组合。处理器管芯182与附加管芯184可通过HMC链路、硅穿孔(through-silicon via，TSV)及微凸块的组合链接在一起，且可嵌入包封材料186中。在一些实施例中，经封装半导体器件180可为单个晶片上芯片(CoW)器件、系统芯片(system on chip，SoC)器件、集成扇出型(InFO)器件、单个管芯或包括一个或多个管芯的封装体。经封装半导体器件180的外部接触件可设置在经封装半导体器件180的第一表面上，所述第一表面与经封装半导体器件180的减薄的背侧第二表面相对。
此外，经封装半导体器件180可包括具有多个外部接触件190的集成扇出型(InFO)结构188。InFO结构188可包括多个介电层及重布线层(RDL)，以用于将布置在InFO结构188的第一侧上的经封装半导体器件180的外部接触件内连到布置在InFO结构188的与InFO结构188的第一侧相对的第二侧上的外部接触件190。
在实施例中，外部接触件190可为例如导电柱，例如铜柱或铜支柱。在一些实施例中，外部接触件190可为焊料凸块、铜凸块或其他合适的外部接触件190，外部接触件190可被制作成通过例如导电连接件174及前侧重布线结构140提供从经封装半导体器件180到其他外部器件的电连接。所有此种外部接触件均旨在包含于实施例的范围内。
如图19进一步所示，在实施例中，经封装半导体器件180可布置在前侧重布线结构140之上，以使得经封装半导体器件180的外部接触件190对准前侧重布线结构140上的导电连接件174并被放置成接触导电连接件174。一旦被布置，可执行接合步骤以将经封装半导体器件180接合到前侧重布线结构140。外部接触件可使用金属对金属接合、焊料接合等接合到导电连接件174。
可在InFO结构188与前侧重布线结构140之间的开口中且环绕导电连接件174及外部接触件190形成底部填充材料192。底部填充材料192可在经封装半导体器件180已被贴合之后通过毛细管底部填充工艺形成。在另一实施例中，底部填充材料192可在经封装半导体器件180被贴合之前通过合适的沉积工艺来提供。
图19示出经封装半导体器件180通过前侧重布线结构140、导电连接件174及InFO结构188连接到第一管芯126。在空腔衬底120的空腔118中设置第一管芯126能够减小第一管芯126与经封装半导体器件180之间的距离。例如，第一管芯126与经封装半导体器件180之间的距离可小于约0.3mm或者从约0.1mm到约0.5mm。相反，替代封装结构可具有大于约10mm的第一管芯126与经封装半导体器件180之间的距离。减小此距离会减小第一管芯126与经封装半导体器件180之间的电压降，这会提高包括第一管芯126及经封装半导体器件180的经封装半导体器件(例如，下文参照图21论述的SoIS 200)的电源完整性(powerintegrity)。
在图20中，将环形结构194贴合到前侧重布线结构140且环绕经封装半导体器件180。环形结构194可被贴合以保护经封装半导体器件180，增加第一封装体101的稳定性，并散逸来自经封装半导体器件180及第一封装体101的热量。环形结构194可由以下具有高导热性的材料形成，例如钢、不锈钢、铜、铝、其组合等。在一些实施例中，环形结构194可为涂布有另一种金属(例如金)的金属。在各种实施例中，环形结构194可为覆盖经封装半导体器件180的上表面的盖体。可使用粘合剂196来将环形结构194固定到前侧重布线结构140。
在图21中，在第二导电迹线112上形成多个导电连接件198，以形成系统集成衬底(SoIS)200。导电连接件198可为BGA连接件、焊料球、导电柱、C4凸块、微凸块、ENEPIG形成的凸块等。导电连接件198可包含例如焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合等导电材料。在一些实施例中，导电连接件198是通过利用例如蒸镀、电镀、印刷、焊料转移、植球等工艺在图20所示结构之上初始地形成焊料层来形成。一旦焊料层已形成，则可执行回焊以便将焊料材料成型成期望的凸块形状。在另一实施例中，导电连接件198为通过溅镀、印刷、电镀、无电镀覆、CVD等而形成的导电柱(例如铜柱)。导电连接件198可为无焊料的，且可具有实质上垂直的侧壁。在一些实施例中，在导电柱的顶部上形成金属盖层(未单独示出)。金属盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料或其组合，且可通过镀覆工艺来形成。
将第一管芯126贴合在空腔衬底120的空腔118中然后通过前侧重布线结构140、导电连接件174及InFO结构188将经封装半导体器件180连接到第一管芯126会使第一管芯126与经封装半导体器件180之间的距离最小化。这会减小第一管芯126与经封装半导体器件180之间的电压降，从而提高SoIS 200的电源完整性及总体性能。
根据实施例，一种封装体包括：衬底；第一管芯，设置在所述衬底内；重布线结构，位于所述衬底及所述第一管芯之上；以及经包封器件，位于所述重布线结构之上，所述重布线结构将所述第一管芯耦合到所述经包封器件。在实施例中，所述第一管芯包括多层陶瓷电容器(MLCC)。在实施例中，所述第一管芯包括集成无源器件(IPD)。在实施例中，所述第一管芯包括集成电压调节器(IVR)。在实施例中，所述第一管芯包括静态随机存取存储器(SRAM)管芯。在实施例中，所述经包封器件与所述第一管芯之间的距离小于0.3mm。在实施例中，重布线结构包括一个或多个模制化合物层。在实施例中，所述一个或多个模制化合物层中的每一者具有从5μm到100μm的厚度。在实施例中，所述封装体还包括贴合到所述重布线结构的环形结构，所述环形结构环绕所述经包封器件。在实施例中，所述封装体还包括环绕所述第一管芯的多个侧壁的底部填充材料。
根据另一实施例，一种方法包括：在衬底中形成空腔；将第一管芯贴合到所述衬底，所述第一管芯设置在所述空腔内；在所述衬底的第一侧及所述第一管芯之上形成重布线结构；以及将半导体器件贴合到所述重布线结构，所述半导体器件包括被包封体包封的第二管芯。在实施例中，所述方法还包括在将所述第一管芯贴合到所述衬底之后，用底部填充胶来填充所述空腔。在实施例中，使用粘合剂将所述第一管芯贴合到所述衬底。在实施例中，形成所述重布线结构包括在所述衬底的所述第一侧以及所述第一管芯之上形成通孔，且形成环绕所述通孔的模制化合物，所述模制化合物与所述衬底侧向共端(coterminous)。
根据又一实施例，一种方法包括：在衬底中形成空腔；将所述衬底安装在载体上；将第一器件贴合到所述衬底及所述空腔内；以及将第二器件耦合到所述第一器件，所述第二器件由包封体包封，所述第二器件在垂直于所述衬底的主表面的方向上设置在所述第一器件之上。在实施例中，所述方法还包括沉积环绕所述第一器件的底部填充胶。在实施例中，所述方法还包括在所述衬底的前侧以及所述第一器件之上形成前侧重布线结构，所述前侧重布线结构包括一个或多个模制化合物层，所述第二器件通过所述前侧重布线结构耦合到所述第一器件。在实施例中，在将所述第二器件耦合到所述第一器件之前，从所述衬底剥离所述载体。在实施例中，所述方法还包括在剥离所述载体之后，在所述衬底的背侧之上形成多个电连接件。在实施例中，所述空腔是使用机械钻孔来形成。
以上内容概述了若干实施例的特征以使所属领域中的技术人员可更好地理解本公开内容的各个方面。所属领域中的技术人员应理解，其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (10)

1.一种封装体，包括：
衬底；
第一管芯，设置在所述衬底内；
重布线结构，位于所述衬底及所述第一管芯之上；以及
经包封器件，位于所述重布线结构之上，所述重布线结构将所述第一管芯耦合到所述经包封器件。
2.根据权利要求1所述的封装体，其中所述重布线结构包括一个或多个模制化合物层。
3.根据权利要求1所述的封装体，还包括贴合到所述重布线结构的环形结构，所述环形结构环绕所述经包封器件。
4.根据权利要求1所述的封装体，还包括环绕所述第一管芯的多个侧壁的底部填充材料。
5.一种形成封装体的方法，包括：
在衬底中形成空腔；
将第一管芯贴合到所述衬底，所述第一管芯设置在所述空腔内；
在所述衬底的第一侧以及所述第一管芯之上形成重布线结构；以及
将半导体器件贴合到所述重布线结构，所述半导体器件包括被包封体包封的第二管芯。
6.根据权利要求5所述的方法，其中使用粘合剂将所述第一管芯贴合到所述衬底。
7.根据权利要求5所述的方法，其中形成所述重布线结构包括在所述衬底的所述第一侧以及所述第一管芯之上形成通孔，且形成环绕所述通孔的模制化合物，其中所述模制化合物与所述衬底侧向共端。
8.一种形成封装体的方法，所述方法包括：
在衬底中形成空腔；
将所述衬底安装在载体上；
将第一器件贴合到所述衬底及所述空腔内；以及
将第二器件耦合到所述第一器件，所述第二器件被包封体包封，所述第二器件在垂直于所述衬底的主表面的方向上设置在所述第一器件之上。
9.根据权利要求8所述的方法，还包括沉积环绕所述第一器件的底部填充胶。
10.根据权利要求8所述的方法，其中所述空腔是使用机械钻孔形成。
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