TW202046457A - 封裝體及其形成方法 - Google Patents
封裝體及其形成方法 Download PDFInfo
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- TW202046457A TW202046457A TW108137366A TW108137366A TW202046457A TW 202046457 A TW202046457 A TW 202046457A TW 108137366 A TW108137366 A TW 108137366A TW 108137366 A TW108137366 A TW 108137366A TW 202046457 A TW202046457 A TW 202046457A
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Abstract
一種半導體封裝體及其形成方法。在實施例中,一種封裝體包括:基底;第一晶粒,設置在基底內;重佈線結構,位於基底及第一晶粒之上;以及經包封元件,位於重佈線結構之上,重佈線結構將第一晶粒耦合到所述經包封元件。
Description
半導體行業通過不斷縮小最小特徵大小來不斷地提高各種電子組件(例如,晶體管、二極管、電阻器、電容器等)的積體密度,以使得更多的組件(因而更多功能)能夠被整合到給定區域中。具有高功能的積體電路需要許多輸入/輸出接墊。然而,對於小型化很重要的應用而言可能需要小的封裝體。
積體扇出型(integrated fan-out,InFO)封裝技術正變得越來越受歡迎,尤其是當與晶圓級封裝(wafer-level packaging,WLP)技術相結合時。InFO封裝體可包括封裝在封裝體中的積體電路,所述封裝體通常包括重佈線層(redistribution layer,RDL)或後鈍化後內連線,所述重佈線層或後鈍化內連線用於對封裝體的接觸墊進行扇出型配線,以使得可以比積體電路的接觸墊更大的節距來進行電接觸。所得封裝結構以相對低的成本及高性能封裝來提供高功能密度。
以下公開內容提供用於實施本發明的不同特徵的許多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本公開。當然,這些僅為實例而非旨在進行限制。舉例來說,在以下說明中,在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見,且自身並不表示所討論的各個實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在...之下”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。除附圖中所繪示的取向以外,所述空間相對性用語旨在涵蓋元件在使用或操作中的不同取向。設備可被另外取向(旋轉90度或處於其他取向),且本文所使用的空間相對性用語可同樣相應地作出解釋。
各種實施例涉及經封裝半導體元件及其形成方法。經封裝半導體元件可為系統積體基底(system on integrated substrate,SoIP)封裝體、系統級封裝體(system-in-package,SiP)等。可在核心基底中形成空腔,且可將例如多層陶瓷電容器(multilayer ceramic capacitor,MLCC)、積體被動元件(integrated passive device,IPD)、積體電壓調節器(integrated voltage regulator ,IVR)、靜態隨機存取記憶體(static random access memory,SRAM)等電子組件貼合到空腔中的核心基底。可在核心基底及電子組件之上形成重佈線層(redistribution layer,RDL),且可將例如晶圓上晶片(chip-on-wafer,CoW)、積體扇出型(InFO)封裝體、晶粒或另一封裝體等電子元件貼合到重佈線層。使電子組件嵌入核心基底中會縮短電子組件與電子元件之間的距離,此會減小電子組件與電子元件之間的電壓降,並提高經封裝半導體元件的電源完整性及總體性能。
首先參照圖1,圖1示出根據一些實施例的基底104,基底104包括絕緣層100以及位於絕緣層100的兩側上的導電層102。基底104可為核心基底(core substrate)。在一些實施例中,基底104是雙面覆銅疊層板(double-sided copper clad laminate,CCL)。絕緣層100可為有機基底、陶瓷基底、預浸漬複合纖維(預浸體)、味之素構成膜(Ajinomoto Build-up Film,ABF)、紙、玻璃纖維、無紡玻璃織物、其他絕緣材料或其組合。導電層102可為疊層或形成在絕緣層100的相對側上的一層或多層銅、鎳、鋁、其他導電材料或其組合。
參照圖2,在基底104中形成多個開口106。在一些實施例中,開口106是通過雷射鑽孔來形成。也可使用其他製程,例如機械鑽孔、蝕刻等。在俯視圖中,開口106可具有矩形、圓形或其他形狀。
參照圖3,根據一些實施例,填充開口106(參見圖2)以形成多個導電插塞110、多個第一導電跡線108及多個第二導電跡線112。導電跡線(例如第一導電跡線108及第二導電跡線112)可用於形成佈線線以對電訊號進行重佈線,或者用作晶粒連接件可貼合的晶粒連接件接墊。在開口106內沉積導電材料之前,可執行表面準備製程。表面準備製程可包括用一種或多種清潔溶液(例如硫酸、鉻酸、中和鹼性溶液、水沖洗液等)來清潔基底104的被暴露表面(例如導電層102的表面及開口106中的絕緣層100的表面),以移除或減少汙物、油和/或天然氧化物膜。可執行除膠渣(desmear)製程來清潔開口106附近的區域,所述區域可能已被絕緣層100的已移除以形成開口106的材料弄髒。除膠渣可以機械方式(例如,用濕漿料中的細磨料進行噴砂)、化學方式(例如,用有機溶劑的組合、高錳酸鹽等進行沖洗)或者通過機械除膠渣與化學除膠渣的組合來實現。在清潔後,可使用化學調節劑(chemical conditioner)進行處理,此有利於吸附在隨後的無電鍍覆期間使用的活化劑。在一些實施例中,在調節步驟之後可對導電層102進行微蝕刻,以將導電層102的導電表面微粗糙化,從而在導電層102與稍後沉積的導電材料之間進行更好地接合。
形成導電插塞110、第一導電跡線108及第二導電跡線112可包括:形成圖案化罩幕層,且利用金屬無電鍍覆技術在圖案化罩幕層的開口中選擇性地沉積導電材料(例如,銅、其他金屬、金屬合金等)。圖案化罩幕層可通過以下方式來形成:用光阻層來塗布表面、將光阻層曝光於光學圖案、以及對被曝光的光阻層進行顯影以在光阻層中形成開口,所述開口界定可選擇性地沉積導電材料的區域的圖案。
在形成第一導電跡線108及第二導電跡線112之後,可剝除圖案化罩幕層(例如,光阻)。可使用合適的蝕刻製程來移除導電層102的曾被圖案化罩幕層覆蓋的部分。移除導電層102的不需要的部分可防止在被圖案化罩幕層暴露的區域中形成的導電特徵之間的不需要的電短路。導電插塞110、第一導電跡線108及第二導電跡線112可以上述方式形成在基底104的兩側上。圖3所示剖視圖示出在導電層102如上所述被蝕刻之後的基底104的狀態。
如下文更詳細論述,基底104將充當形成包含空腔的核心基底(空腔基底120)(未在圖3中示出,但在圖5中示出)的基底。在圖3中,第一導電跡線108形成在絕緣層100的一側上,在後續處理步驟期間在絕緣層100的所述側中形成空腔118(未在圖3中示出,但在圖5中示出)。根據一些實施例,第一導電跡線108可從隨後可形成空腔的區域(例如,此實例中為最內導電插塞110之間的區域)省略。
儘管在此實例中未示出,然而理解到可重複地執行使用覆金屬疊層板、形成延伸穿過覆金屬疊層板的開口、形成圖案化導電跡線層(例如,使用無電沉積或電鍍等)以及移除不需要的金屬包覆層的方法,以垂直地堆疊絕緣材料與導電跡線的多個交替層以及導電插塞,從而垂直地連接導電跡線的相鄰層。
參照圖4,基底104之上且分別在第一導電跡線108及第二導電跡線112之上形成介電層114及保護層116。在一些實施例中,介電層114是由可使用微影罩幕(lithography mask)進行圖案化的聚合物形成,所述聚合物可為例如聚苯並惡唑(polybenzoxazole,PBO)、聚醯亞胺、苯環丁烷(benzocyclobuten,BCB)等感光性材料。介電層114可通過旋轉塗布、疊層、化學氣相沉積(chemical vapor deposition,CVD)、類似製程或其組合來形成。將介電層114圖案化以形成暴露出第一導電跡線108的部分的開口。當介電層114是感光性材料時,圖案化可通過將介電層114暴露於光並對介電層114進行顯影來實現。介電層114也可由以下不具有感光性的材料形成,例如氮化矽、氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)等。在介電層114是由非感光性的材料形成的實施例中,介電層114可通過經由圖案化光阻罩幕用合適的蝕刻製程(例如,各向異性反應離子蝕刻)進行蝕刻來圖案化。
在各種實施例中,保護層116可為形成在第二導電跡線112之上的阻焊劑等,以保護絕緣層100的區域免受外部損壞。可將保護層116圖案化以形成暴露出第二導電跡線112的部分的開口。在保護層116由感光性材料形成的實施例中,圖案化可通過將保護層116暴露於光並對保護層116進行顯影來實現。在保護層116是由非感光性的材料形成的實施例中,保護層116可通過經由圖案化光阻罩幕用合適的蝕刻製程(例如,各向異性反應離子蝕刻)進行蝕刻來圖案化。暴露出第二導電跡線112的開口可用作晶粒連接件接墊,導電連接件198(未在圖4中示出,但在圖21中示出)可隨後貼合到晶粒連接件接墊。
在圖5中,根據一些實施例,通過移除絕緣層100的一部分來形成空腔(cavity)118。移除絕緣層100的所述部分不會影響位於絕緣層100的通過移除製程而凹陷的同一側上的第一導電跡線108。如上參照圖3所述,用於形成第一導電跡線108的圖案化罩幕可被設計成排除第一導電跡線108形成在絕緣層100的形成有空腔118的一部分之上的情況。移除材料以形成空腔118可通過電腦數控(computer numeric control,CNC)加工製程來執行,其中材料是通過機械鑽孔來移除。如圖5所示,所得結構是空腔基底120。空腔基底120的絕緣層100可具有從約25 µm到約2,000 µm(例如約250 µm 或約500 µm)的厚度T1。空腔118可具有從約10 µm到約1,000 µm(例如約70 µm 或約400 µm)的深度。空腔118可具有從約1 mm乘1 mm到約20 mm乘20 mm(例如約1.5 mm乘1.5 mm或約5.0 mm乘4.0 mm)的面積。在一些實施例中,絕緣層100的一部分可沿著空腔118的底部保留,且可具有從約20 µm到約1600 µm(例如約30 µm或約800 µm)的厚度。也可使用其他製程來形成空腔118,例如雷射鑽孔、蝕刻和/或類似製程。
在圖6中,根據一些實施例,使用釋放層124將空腔基底120貼合到載體基底122。如圖6所示,空腔基底120可使用釋放層124貼合到載體基底122,以使空腔118與釋放層124相對。載體基底122可為玻璃載體基底、陶瓷載體基底等。釋放層124可為聚合物系材料、環氧系熱釋放材料(例如光-熱轉換(light-to-heat-conversion,LTHC)釋放塗層)或者紫外(ultra-violet,UV)膠(例如,當暴露於紫外光時失去其黏合性質的膠)。釋放層124可有助於在後續處理期間移除載體基底122。釋放層124可在後續處理期間與載體基底122一起被移除。
在圖7A中,根據一些實施例,將第一晶粒126放置在空腔118(示於圖6中)內。第一晶粒126可使用拾取及放置(pick-and-place,PnP)工具放置在空腔118內。第一晶粒126可為被動元件,例如多層陶瓷晶片(multilayer ceramic chip,MLCC)電容器;積體被動元件(IPD);積體電壓調節器(integrated voltage regulator,IVR)等或其組合;或者有源元件,例如記憶體晶粒(例如,靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(dynamic random-access memory,DRAM)晶粒、高帶寬記憶體(high bandwidth memory,HBM)晶粒等)、邏輯晶片、類比晶片、微機電系統(microelectromechanical system,MEMS)晶片、射頻(radio frequency,RF)晶片、類似晶片或其組合。在一些實施例中,通過黏合劑128將第一晶粒126黏合到絕緣層100。儘管圖7A示出將一個第一晶粒126放置在空腔118中,然而應理解也可將多個晶粒或元件放置在空腔基底120的空腔118中。例如,在一些實施例中,第一晶粒126可為彼此橫向鄰近放置和/或堆疊在彼此上的多個元件,其中所述多個元件可具有相同或不同的大小。在將第一晶粒126放置到空腔基底120上之前,可根據適用的製造製程對第一晶粒126進行處理,以形成相應的元件結構。第一晶粒126可包括進行外部連接的連接端子130(例如,鋁墊、銅墊等)。第一晶粒126可具有從約30 µm到約350 µm的高度、從約0.5 mm到約0.8 mm的長度以及從約0.5 mm到約0.8 mm的寬度。
黏合劑128可貼合到第一晶粒126的背側,且可將第一晶粒126貼合到絕緣層100。黏合劑128可為任何合適的黏合劑、環氧樹脂、晶粒貼合膜(die attach film,DAF)等。黏合劑128可在將第一晶粒126單體化之前施加到第一晶粒126的背側。可例如通過鋸切(sawing)或切割(dicing)而將第一晶粒126單體化,並使用例如PnP工具通過黏合劑128而將第一晶粒126黏合到絕緣層100。在一些實施例中,黏合劑128可在將第一晶粒126放置在空腔118中之前貼合到空腔基底120。
圖7B示出可用作第一晶粒126的MLCC 220。如圖7B所示,MLCC 220包括夾置在陶瓷224層之間的多個電極226。MLCC 220還包括用於外部連接的多個連接端子222。
在圖8中,根據一些實施例,在第一晶粒126的多個側壁與空腔基底120之間形成底部填充膠132。底部填充膠132可在第一晶粒126被貼合之後通過毛細管流動製程(capillary flow process)而形成,或可在第一晶粒126被貼合之前通過合適的沉積方法而形成。底部填充膠132可為例如模製化合物、環氧樹脂、底部填充膠、模製底部填充膠(molding underfill,MUF)、樹脂等材料。底部填充膠132可減小第一晶粒126與空腔基底120之間的應力,且可幫助將第一晶粒126固定在空腔118中。如圖8所示,底部填充膠132的上表面可為凹面;然而,在一些實施例中,底部填充膠132的上表面可為凸面或平面。
圖9到圖15示出根據一些實施例在第一晶粒126的連接端子130及空腔基底120的第一導電跡線108之上形成前側重佈線結構140(示於圖15中)。前側重佈線結構140包括介電質與導電跡線的交替層的垂直堆疊。每層導電跡線通過介電層與垂直鄰近的導電跡線層分隔開。導電跡線延伸穿過下伏介電層,以形成用於將垂直鄰近的導電跡線內連的導通孔。前側重佈線結構140與空腔基底120一起形成第一封裝體101(示於圖15中)。
在圖9中,在空腔基底120、底部填充膠132及第一晶粒126之上形成介電層134。在一些實施例中,介電層134是由可使用微影罩幕進行圖案化的聚合物形成,所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料。介電層134可通過旋轉塗布、疊層、化學氣相沉積(CVD)、類似製程或其組合來形成。將介電層134圖案化以形成暴露出多個連接端子130及多個第一導電跡線108的部分的多個開口。當介電層134是感光性材料時,圖案化可通過將介電層134暴露於光來實現。介電層134也可由以下不具有感光性的材料形成,例如氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)等。在介電層134是由非感光性的材料形成的實施例中,介電層134可通過經由圖案化光阻罩幕用合適的蝕刻製程(例如,各向異性反應離子蝕刻)進行蝕刻來圖案化。
在圖10中,在介電層134上形成金屬化圖案136且金屬化圖案136延伸穿過介電層134。作為形成金屬化圖案136的實例,在介電層134之上形成晶種層(未單獨示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可利用例如物理氣相沉積(physical vapor deposition,PVD)、CVD等來形成。接著在晶種層上形成光阻(未單獨示出)並將所述光阻圖案化。光阻可通過旋轉塗布等形成,可暴露於圖案化的光或另一圖案化的能量源,且可暴露於顯影劑以移除光阻的被暴露部分或未暴露部分。光阻的圖案對應於金屬化圖案136。所述圖案化穿過光阻形成開口以暴露出晶種層。在光阻的開口中且在晶種層的被暴露部分上形成導電材料(未單獨示出)。所述導電材料可通過例如電鍍、無電鍍覆等鍍覆來形成。導電材料可包含例如銅、鈦、鎢、鋁等金屬。接著,移除光阻以及晶種層的未形成導電材料的部分。光阻可例如使用氧電漿等、通過可接受的灰化製程或剝除製程來移除。一旦光阻被移除,便使用可接受的蝕刻製程(例如濕式蝕刻或幹式蝕刻)來移除晶種層的被暴露部分。晶種層的其餘部分及導電材料會形成金屬化圖案136。金屬化圖案136包括沿介電層134的頂表面形成的導電跡線以及穿過介電層134的導通孔。通孔將金屬化圖案136的導電跡線電連接並實體連接到介電層134正下方的金屬圖案(例如,第一導電跡線108及連接端子130)。
形成介電層134(參照圖9論述)及金屬化圖案136的導電跡線及導通孔(參照圖10論述)的方法僅被闡述作為實例。應理解,形成介電層134及金屬化圖案136的製程可基於設計規格(例如,圖案的期望最小尺寸)而變化。例如,在一些實施例中,可利用鑲嵌製程(例如,單鑲嵌製程或雙鑲嵌製程)。前側重佈線結構140可通過垂直地堆疊附加介電層及金屬化圖案來構建。
圖11示出在介電層134及金屬化圖案136的頂表面之上形成的附加的介電層138、介電層144及介電層148。圖11中還示出金屬化圖案142、金屬化圖案146及金屬化圖案150。金屬化圖案142、金屬化圖案146及金屬化圖案150包括沿相應介電層138、介電層144及介電層148的頂表面形成的導電跡線以及延伸穿過相應介電層138、介電層144及介電層148的導通孔。金屬化圖案142、金屬化圖案146及金屬化圖案150的通孔將金屬化圖案142、金屬化圖案146及金屬化圖案150的導電跡線電連接並實體連接到相應介電層138、介電層144及介電層148正下方的相應金屬化圖案(例如,相應金屬化圖案136、金屬化圖案142及金屬化圖案146)。可重複與以上關於介電層134及金屬化圖案136闡述的製程、技術及材料相似的製程、技術及材料,以形成介電層138、介電層144及介電層148以及金屬化圖案142、金屬化圖案146及金屬化圖案150。
在圖12中,在金屬化圖案150上形成多個導電柱152。作為形成導電柱152的實例,在介電層148及金屬化圖案150之上形成晶種層(未單獨示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如PVD、CVD等來形成。接著在晶種層上形成光阻(未單獨示出)並將所述光阻圖案化。光阻可通過旋轉塗布等形成,可暴露於圖案化的光或另一圖案化的能量源,且可暴露於顯影劑以移除光阻的被暴露部分或未暴露部分。光阻的圖案對應於導電柱152。所述圖案化穿過光阻形成開口以暴露出晶種層。在光阻的開口中且在晶種層的被暴露部分上形成導電材料(未單獨示出)。所述導電材料可通過例如電鍍、無電鍍覆等鍍覆來形成。導電材料可包含例如銅、鈦、鎢、鋁等金屬。接著,移除光阻以及晶種層的未形成導電材料的部分。光阻可例如使用氧電漿等、通過可接受的灰化製程或剝除製程來移除。一旦光阻被移除,便使用可接受的蝕刻製程(例如濕式蝕刻或幹式蝕刻)來移除晶種層的被暴露部分。晶種層的其餘部分及導電材料會形成導電柱152。導電柱152電連接並實體連接到金屬化圖案150。
現在參照圖13,可通過以下方式使導電柱152嵌於絕緣層154中:例如,層疊例如ABF或預浸體等積層膜,且使用回蝕或平坦化製程(例如化學機械拋光(chemical-mechanical polishing,CMP)、研磨等)來暴露出導電柱152的頂表面。在一些實施例中,絕緣層154可沉積為模製到介電層148及金屬化圖案150上並環繞導電柱152的液體模製化合物。
在圖14中,在導電柱152及絕緣層154之上形成多個導電跡線156。導電跡線156可使用與以上關於圖10所示的形成金屬化圖案136闡述的製程、技術及材料相似的製程、技術及材料來形成,其中沉積晶種層,在晶種層之上形成圖案化罩幕,執行鍍覆製程以形成金屬化圖案,移除圖案化罩幕,且移除晶種層的未使用部分。
在圖15中,在導電跡線156及絕緣層154之上形成介電層158、多個導電跡線160、多個導電柱162、絕緣層164、多個導電跡線166及多個凸塊下金屬(under-bump metallization,UBM)168。介電層158可使用與以上關於圖9所示的形成介電層134闡述的製程、技術及材料相似的製程、技術及材料來形成。導電跡線160及導電跡線166以及導電柱162可使用與以上關於圖10所示的形成金屬化圖案136闡述的製程、技術及材料相似的製程、技術及材料來形成,其中沉積晶種層,在晶種層之上形成圖案化罩幕,執行鍍覆製程以形成金屬化圖案,移除圖案化罩幕,且移除晶種層的未使用部分。儘管圖15中未示出,然而可形成延伸穿過介電層158並將導電跡線160電連接到導電跡線156的導通孔。絕緣層164可使用與以上關於圖13所示的形成絕緣層154闡述的製程、技術及材料相似的製程、技術及材料來形成。
UBM 168可形成在絕緣層164及導電柱162之上。UBM 168包括可焊接金屬表面,所述可焊接金屬表面可用作隨後形成的焊料凸塊(例如,圖17A所示的導電連接件174)與前側重佈線結構140之間的界面。如圖15所示,UBM 168可電連接並實體連接到導電柱162。UBM 168可使用與圖10所示的用於形成金屬化圖案136的製程、技術及材料相似的製程、技術及材料來形成。然後可使用與以上關於圖9所示的形成介電層134闡述的製程、技術及材料相似的製程、技術及材料在絕緣層164、導電跡線166及UBM 168之上形成介電層170。
可在前側重佈線結構140中形成更多或更少的介電層、絕緣層、金屬化圖案、導電跡線及導電柱。在一些實施例中,前側重佈線結構140可包括1到10個介電層/絕緣層;然而,前側重佈線結構140可為可選的,且在一些實施例中可不包括前側重佈線結構140。如果將形成更少的介電層及金屬化圖案,則可省略以上論述的步驟及製程。如果將形成更多介電層及金屬化圖案,則可重複以上論述的步驟及製程。介電層134、介電層138、介電層144、介電層148、介電層158及介電層170中的每一者以及絕緣層154及絕緣層164中的每一者可具有從約5 µm到約100 µm(例如約30 µm)的厚度。
在上述實施例中,在前側重佈線結構140中包括兩個絕緣層(絕緣層154及絕緣層164)。絕緣層154及絕緣層164可由模製化合物材料形成,所述模製化合物材料具有比用於形成介電層134、介電層138、介電層144、介電層148、介電層158及介電層170的介電材料更低的阻抗。如此,絕緣層154及絕緣層164可包括在前側重佈線結構140中,以控制前側重佈線結構140的阻抗並將前側重佈線結構的阻抗匹配到期望值。例如,包括絕緣層154及絕緣層164的前側重佈線結構140的阻抗可介於約90 Ω與約100 Ω之間,例如約100 Ω。
在圖16中,將介電層170圖案化以形成暴露出多個UBM 168的部分的多個開口172。當介電層170是感光性材料時,圖案化可通過將介電層170暴露於光來實現。在介電層170是由非感光性的材料形成的實施例中,介電層170可通過經由圖案化光阻罩幕用合適的蝕刻製程(例如,各向異性反應離子蝕刻)進行蝕刻來圖案化。
在圖17A中,在多個UBM 168上形成多個導電連接件174。導電連接件174可為球柵陣列(ball grid array、BGA)連接件、焊料球、導電柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。導電連接件174可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。在一些實施例中,導電連接件174是通過利用例如蒸鍍(evaporation)、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等製程在圖16所示結構之上初始地形成焊料層來形成。一旦焊料層已形成,則可執行回焊(reflow)以便將焊料材料成型成期望的凸塊形狀。在另一實施例中,導電連接件174為通過濺鍍(sputtering)、印刷、電鍍、無電鍍覆、CVD等而形成的導電柱(例如銅柱)。導電連接件174可為無焊料的,且可具有實質上垂直的側壁。在一些實施例中,在導電柱的頂部上形成金屬蓋層(metal cap layer)(未單獨示出)。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可通過鍍覆製程來形成。
可在單個載體基底122上形成多個第一封裝體101。如圖17B所示,第一封裝體101可具有矩形形狀,載體基底122可具有圓的形狀(例如圓形形狀),且載體基底122可被稱為晶圓。如圖17C所示,第一封裝體101可具有矩形形狀,載體基底122可具有矩形形狀,且載體基底122可被稱為面板。第一封裝體101可例如通過鋸切、切割等彼此單體化。第一封裝體101可在移除載體基底122之前被單體化。儘管在圖17B中示出四個第一封裝體101且在圖17C中示出九個第一封裝體101,然而可在載體基底122上形成任何數目的第一封裝體101,例如從單個第一封裝體101到數千個第一封裝體101。
在圖18中,根據一些實施例,執行載體基底剝離(carrier substrate de-bonding)製程以將載體基底122從空腔基底120的保護層116脫離(剝離)。在釋放層124是光敏黏合劑的實施例中,所述剝離可通過將例如雷射或紫外光等光投射在釋放層124上以使得釋放層124分解且可移除載體基底122來執行。可執行清潔製程以從保護層116移除釋放層124的殘留物。將載體基底122脫離會暴露出保護層116及其中的多個開口。
在圖19中,將經封裝半導體元件180接合到導電連接件174。根據實施例,經封裝半導體元件180可例如通過拾取及放置機器(未單獨示出)佈置在前側重佈線結構140之上。然而,可利用將經封裝半導體元件180佈置在前側重佈線結構140上的任何其他替代方法。
在實施例中,經封裝半導體元件180可包括處理器晶粒182(例如,賽斯靈處理單元(Xilinx processing unit,xPU)),例如中央處理器(central processing unit,CPU)、微控制單元(micro control unit,MCU)、圖形處理單元(graphics processing unit,GPU)、應用處理器(application processor,AP)等。經封裝半導體元件180還可包括附加晶粒184,例如記憶體晶粒(例如動態隨機存取記憶體(DRAM)晶粒、寬輸入/輸出(input/output,I/O)晶粒、磁性隨機存取記憶體(magnetic random-access memory,MRAM)晶粒、電阻式隨機存取記憶體(resistive random-access memory,RRAM)晶粒、反及(NAND)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、記憶體立方體(例如高帶寬記憶體(HBM)、混合記憶體立方體(hybrid memory cube,HMC)等)、高數據速率收發器晶粒、I/O介面晶粒、積體被動元件(IPD)晶粒、電源管理晶粒(例如,電源管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如,數字訊號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)、單片三維異質晶片堆疊晶粒(monolithic 3D heterogeneous chiplet stacking die)等或其組合。處理器晶粒182與附加晶粒184可通過HMC鏈路、矽穿孔(through-silicon via,TSV)及微凸塊的組合鏈接在一起,且可嵌入包封材料186中。在一些實施例中,經封裝半導體元件180可為單個晶圓上晶片(CoW)元件、系統晶片(system on chip,SoC)元件、積體扇出型(InFO)元件、單個晶粒或包括一個或多個晶粒的封裝體。經封裝半導體元件180的外部接觸件可設置在經封裝半導體元件180的第一表面上,所述第一表面與經封裝半導體元件180的減薄的背側第二表面相對。
此外,經封裝半導體元件180可包括具有多個外部接觸件190的積體扇出型(InFO)結構188。InFO結構188可包括多個介電層及重佈線層(RDL),以用於將佈置在InFO結構188的第一側上的經封裝半導體元件180的外部接觸件內連到佈置在InFO結構188的與InFO結構188的第一側相對的第二側上的外部接觸件190。
在實施例中,外部接觸件190可為例如導電柱,例如銅柱或銅支柱。在一些實施例中,外部接觸件190可為焊料凸塊、銅凸塊或其他合適的外部接觸件190,外部接觸件190可被製作成通過例如導電連接件174及前側重佈線結構140提供從經封裝半導體元件180到其他外部元件的電連接。所有此種外部接觸件均旨在包含於實施例的範圍內。
如圖19進一步所示,在實施例中,經封裝半導體元件180可佈置在前側重佈線結構140之上,以使得經封裝半導體元件180的外部接觸件190對準前側重佈線結構140上的導電連接件174並被放置成接觸導電連接件174。一旦被佈置,可執行接合步驟以將經封裝半導體元件180接合到前側重佈線結構140。外部接觸件可使用金屬對金屬接合、焊料接合等接合到導電連接件174。
可在InFO結構188與前側重佈線結構140之間的開口中且環繞導電連接件174及外部接觸件190形成底部填充材料192。底部填充材料192可在經封裝半導體元件180已被貼合之後通過毛細管底部填充製程形成。在另一實施例中,底部填充材料192可在經封裝半導體元件180被貼合之前通過合適的沉積製程來提供。
圖19示出經封裝半導體元件180通過前側重佈線結構140、導電連接件174及InFO結構188連接到第一晶粒126。在空腔基底120的空腔118中設置第一晶粒126能夠減小第一晶粒126與經封裝半導體元件180之間的距離。例如,第一晶粒126與經封裝半導體元件180之間的距離可小於約0.3 mm或者從約0.1 mm到約0.5 mm。相反,替代封裝結構可具有大於約10 mm的第一晶粒126與經封裝半導體元件180之間的距離。減小此距離會減小第一晶粒126與經封裝半導體元件180之間的電壓降,這會提高包括第一晶粒126及經封裝半導體元件180的經封裝半導體元件(例如,下文參照圖21論述的SoIS 200)的電源完整性(power integrity)。
在圖20中,將環形結構194貼合到前側重佈線結構140且環繞經封裝半導體元件180。環形結構194可被貼合以保護經封裝半導體元件180,增加第一封裝體101的穩定性,並散逸來自經封裝半導體元件180及第一封裝體101的熱量。環形結構194可由以下具有高導熱性的材料形成,例如鋼、不銹鋼、銅、鋁、其組合等。在一些實施例中,環形結構194可為塗布有另一種金屬(例如金)的金屬。在各種實施例中,環形結構194可為覆蓋經封裝半導體元件180的上表面的蓋體。可使用黏合劑196來將環形結構194固定到前側重佈線結構140。
在圖21中,在第二導電跡線112上形成多個導電連接件198,以形成系統積體基底(SoIS)200。導電連接件198可為BGA連接件、焊料球、導電柱、C4凸塊、微凸塊、ENEPIG形成的凸塊等。導電連接件198可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。在一些實施例中,導電連接件198是通過利用例如蒸鍍、電鍍、印刷、焊料轉移、植球等製程在圖20所示結構之上初始地形成焊料層來形成。一旦焊料層已形成,則可執行回焊以便將焊料材料成型成期望的凸塊形狀。在另一實施例中,導電連接件198為通過濺鍍、印刷、電鍍、無電鍍覆、CVD等而形成的導電柱(例如銅柱)。導電連接件198可為無焊料的,且可具有實質上垂直的側壁。在一些實施例中,在導電柱的頂部上形成金屬蓋層(未單獨示出)。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可通過鍍覆製程來形成。
將第一晶粒126貼合在空腔基底120的空腔118中然後通過前側重佈線結構140、導電連接件174及InFO結構188將經封裝半導體元件180連接到第一晶粒126會使第一晶粒126與經封裝半導體元件180之間的距離最小化。這會減小第一晶粒126與經封裝半導體元件180之間的電壓降,從而提高SoIS 200的電源完整性及總體性能。
根據實施例,一種封裝體包括:基底;第一晶粒,設置在所述基底內;重佈線結構,位於所述基底及所述第一晶粒之上;以及經包封元件,位於所述重佈線結構之上,所述重佈線結構將所述第一晶粒耦合到所述經包封元件。在實施例中,所述第一晶粒包括多層陶瓷電容器(MLCC)。在實施例中,所述第一晶粒包括積體被動元件(IPD)。在實施例中,所述第一晶粒包括積體電壓調節器(IVR)。在實施例中,所述第一晶粒包括靜態隨機存取記憶體(SRAM)晶粒。在實施例中,所述經包封元件與所述第一晶粒之間的距離小於0.3 mm。在實施例中,重佈線結構包括一個或多個模製化合物層。在實施例中,所述一個或多個模製化合物層中的每一者具有從5 µm到100 µm的厚度。在實施例中,所述封裝體還包括貼合到所述重佈線結構的環形結構,所述環形結構環繞所述經包封元件。在實施例中,所述封裝體還包括環繞所述第一晶粒的多個側壁的底部填充材料。
根據另一實施例,一種方法包括:在基底中形成空腔;將第一晶粒貼合到所述基底,所述第一晶粒設置在所述空腔內;在所述基底的第一側及所述第一晶粒之上形成重佈線結構;以及將半導體元件貼合到所述重佈線結構,所述半導體元件包括被包封體包封的第二晶粒。在實施例中,所述方法還包括在將所述第一晶粒貼合到所述基底之後,用底部填充膠來填充所述空腔。在實施例中,使用黏合劑將所述第一晶粒貼合到所述基底。在實施例中,形成所述重佈線結構包括在所述基底的所述第一側以及所述第一晶粒之上形成通孔,且形成環繞所述通孔的模製化合物,所述模製化合物與所述基底側向共端(coterminous)。
根據又一實施例,一種方法包括:在基底中形成空腔;將所述基底安裝在載體上;將第一元件貼合到所述基底及所述空腔內;以及將第二元件耦合到所述第一元件,所述第二元件由包封體包封,所述第二元件在垂直於所述基底的主表面的方向上設置在所述第一元件之上。在實施例中,所述方法還包括沉積環繞所述第一元件的底部填充膠。在實施例中,所述方法還包括在所述基底的前側以及所述第一元件之上形成前側重佈線結構,所述前側重佈線結構包括一個或多個模製化合物層,所述第二元件通過所述前側重佈線結構耦合到所述第一元件。在實施例中,在將所述第二元件耦合到所述第一元件之前,從所述基底剝離所述載體。在實施例中,所述方法還包括在剝離所述載體之後,在所述基底的背側之上形成多個電連接件。在實施例中,所述空腔是使用機械鑽孔來形成。
以上內容概述了若干實施例的特徵以使所屬領域中的技術人員可更好地理解本公開內容的各個方面。所屬領域中的技術人員應理解,其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
100、154、164:絕緣層
101:第一封裝體
102:導電層
104:基底
106、172:開口
108:第一導電跡線
110:導電插塞
112:第二導電跡線
114、134、138、144、148、158、170:介電層
116:保護層
118:空腔
120:空腔基底
122:載體基底
124:釋放層
126:第一晶粒
128、196:黏合劑
130、222:連接端子
132:底部填充膠
136、142、146、150:金屬化圖案
140:前側重佈線結構
152、162:導電柱
156、160、166:導電跡線
168:凸塊下金屬
174、198:導電連接件
180:經封裝半導體元件
182:處理器晶粒
184:晶粒
186:包封材料
188:積體扇出型結構
190:外部接觸件
192:底部填充材料
194:環形結構
200:系統積體基底(SoIS)
220:MLCC
224:陶瓷
226:電極
T1:厚度
結合附圖閱讀以下詳細說明會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的核心基底。
圖2示出根據一些實施例在核心基底中形成開口。
圖3示出根據一些實施例在核心基底中形成導電跡線及導電插塞。
圖4示出根據一些實施例在核心基底之上形成介電層及保護層。
圖5示出根據一些實施例在核心基底中形成空腔。
圖6示出根據一些實施例將基底接合到載體。
圖7A示出根據一些實施例將第一晶粒貼合在空腔內。
圖7B示出根據一些實施例的多層陶瓷電容器。
圖8示出根據一些實施例形成環繞被動元件的底部填充膠。
圖9到圖15示出根據一些實施例在基底及被動元件之上形成前側重佈線結構。
圖16示出根據一些實施例在前側重佈線結構中形成開口。
圖17A示出根據一些實施例在前側重佈線結構上形成導電連接件。
圖17B及圖17C示出根據一些實施例在載體之上形成的第一封裝體。
圖18示出根據一些實施例將載體剝離。
圖19示出根據一些實施例對經封裝半導體元件進行接合。
圖20示出根據一些實施例對環形結構進行貼合。
圖21示出根據一些實施例在基底的背側上形成導電連接件。
100、154、164:絕緣層
101:第一封裝體
108:第一導電跡線
110:導電插塞
112:第二導電跡線
114、134、138、144、148、158、170:介電層
116:保護層
120:空腔基底
126:第一晶粒
128:黏合劑
130:連接端子
132:底部填充膠
136、142、146、150:金屬化圖案
140:前側重佈線結構
152、162:導電柱
156、160、166:導電跡線
168:凸塊下金屬
174:導電連接件
180:經封裝半導體元件
182:處理器晶粒
184:晶粒
186:包封材料
188:積體扇出型結構
190:外部接觸件
192:底部填充材料
Claims (20)
- 一種封裝體,包括: 基底; 第一晶粒,設置在所述基底內; 重佈線結構,位於所述基底及所述第一晶粒之上;以及 經包封元件,位於所述重佈線結構之上,所述重佈線結構將所述第一晶粒耦合到所述經包封元件。
- 如申請專利範圍第1項所述的封裝體,其中所述第一晶粒包括多層陶瓷電容器。
- 如申請專利範圍第1項所述的封裝體,其中所述第一晶粒包括積體被動元件。
- 如申請專利範圍第1項所述的封裝體,其中所述第一晶粒包括積體電壓調節器。
- 如申請專利範圍第1項所述的封裝體,其中所述第一晶粒包括靜態隨機存取記憶體晶粒。
- 如申請專利範圍第1項所述的封裝體,其中所述經包封元件與所述第一晶粒之間的距離小於0.3 mm。
- 如申請專利範圍第1項所述的封裝體,其中所述重佈線結構包括一個或多個模製化合物層。
- 如申請專利範圍第7項所述的封裝體,其中所述一個或多個模製化合物層中的每一者具有從5 µm到100 µm的厚度。
- 如申請專利範圍第1項所述的封裝體,還包括貼合到所述重佈線結構的環形結構,所述環形結構環繞所述經包封元件。
- 如申請專利範圍第1項所述的封裝體,還包括環繞所述第一晶粒的多個側壁的底部填充材料。
- 一種方法,包括: 在基底中形成空腔; 將第一晶粒貼合到所述基底,所述第一晶粒設置在所述空腔內; 在所述基底的第一側以及所述第一晶粒之上形成重佈線結構;以及 將半導體元件貼合到所述重佈線結構,所述半導體元件包括被包封體包封的第二晶粒。
- 如申請專利範圍第11項所述的方法,還包括在將所述第一晶粒貼合到所述基底之後,用底部填充膠來填充所述空腔。
- 如申請專利範圍第11項所述的方法,其中使用黏合劑將所述第一晶粒貼合到所述基底。
- 如申請專利範圍第11項所述的方法,其中形成所述重佈線結構包括在所述基底的所述第一側以及所述第一晶粒之上形成通孔,且形成環繞所述通孔的模製化合物,其中所述模製化合物與所述基底側向共端。
- 一種形成封裝體的方法,所述方法包括: 在基底中形成空腔; 將所述基底安裝在載體上; 將第一元件貼合到所述基底及所述空腔內;以及 將第二元件耦合到所述第一元件,所述第二元件被包封體包封,所述第二元件在垂直於所述基底的主表面的方向上設置在所述第一元件之上。
- 如申請專利範圍第15項所述的方法,還包括沉積環繞所述第一元件的底部填充膠。
- 如申請專利範圍第16項所述的方法,還包括在所述基底的前側以及所述第一元件之上形成前側重佈線結構,所述前側重佈線結構包括一個或多個模製化合物層,其中所述第二元件通過所述前側重佈線結構耦合到所述第一元件。
- 如申請專利範圍第17項所述的方法,其中在將所述第二元件耦合到所述第一元件之前,從所述基底剝離所述載體。
- 如申請專利範圍第18項所述的方法,還包括在剝離所述載體之後,在所述基底的背側之上形成多個電連接件。
- 如申請專利範圍第15項所述的方法,其中所述空腔是使用機械鑽孔形成。
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